Commit Graph

3825 Commits

Author SHA1 Message Date
John Baldwin 5c887dd5f6 Honor an existing CC_FOR_BUILD in the environment for sim.
This matches the equivalent bits in bfd/acinclude.m4

sim/ChangeLog:

	* configure.ac: Honor existing CC_FOR_BUILD in environment.
	* configure: Regenerate.

sim/aarch64/ChangeLog:

	* configure: Regenerate.

sim/arm/ChangeLog:

	* configure: Regenerate.

sim/avr/ChangeLog:

	* configure: Regenerate.

sim/bfin/ChangeLog:

	* configure: Regenerate.

sim/common/ChangeLog:

	* acinclude.m4 (SIM_AC_COMMON) Honor existing CC_FOR_BUILD in
	environment.

sim/cr16/ChangeLog:

	* configure: Regenerate.

sim/cris/ChangeLog:

	* configure: Regenerate.

sim/d10v/ChangeLog:

	* configure: Regenerate.

sim/erc32/ChangeLog:

	* configure: Regenerate.

sim/frv/ChangeLog:

	* configure: Regenerate.

sim/ft32/ChangeLog:

	* configure: Regenerate.

sim/h8300/ChangeLog:

	* configure: Regenerate.

sim/iq2000/ChangeLog:

	* configure: Regenerate.

sim/lm32/ChangeLog:

	* configure: Regenerate.

sim/m32c/ChangeLog:

	* configure: Regenerate.

sim/m32r/ChangeLog:

	* configure: Regenerate.

sim/m68hc11/ChangeLog:

	* configure: Regenerate.

sim/mcore/ChangeLog:

	* configure: Regenerate.

sim/microblaze/ChangeLog:

	* configure: Regenerate.

sim/mips/ChangeLog:

	* configure: Regenerate.

sim/mn10300/ChangeLog:

	* configure: Regenerate.

sim/moxie/ChangeLog:

	* configure: Regenerate.

sim/msp430/ChangeLog:

	* configure: Regenerate.

sim/rl78/ChangeLog:

	* configure: Regenerate.

sim/rx/ChangeLog:

	* configure: Regenerate.

sim/sh/ChangeLog:

	* configure: Regenerate.

sim/sh64/ChangeLog:

	* configure: Regenerate.

sim/v850/ChangeLog:

	* configure: Regenerate.
2017-09-06 10:16:12 -07:00
John Baldwin 625ce09c1c Define an error function in the PPC simulator library.
Previously this used the error function from GDB directly when linked
against GDB instead of the error method in the host callbacks
structure.  This was exposed via a link error when GDB was converted
to C++.  The error function invokes the error callback similar to
sim_io_error.

Note that there are also error functions in sim/ppc/main.c and
sim/ppc/misc.c.  The ppc libsim.a expects each consumer to provide
several symbols used by the library including "error".  sim-calls.c
provides these symbols when the library is linked into gdb.  The dgen,
igen, tmp-filter, tmp-ld-decode, tmp-ld-cache, and tmp-ld-insn programs
use the functions from misc.c.  psim uses the functions from main.c.

sim/ppc/ChangeLog:

	PR sim/20863
	* sim_calls.c (error): New function.
2017-09-04 19:56:00 -07:00
Anthony Green 6c869779da Fix simulator 2017-09-04 10:00:37 -04:00
Jozef Lawrynowicz 3819af136d Fix simulation of MSP430's open system call.
* sim/msp430/msp430-sim.c (maybe_perform_syscall): Fix passing of
	arguments for variadic syscall "open".
2017-08-29 14:09:58 +01:00
Michael Eager e7cd2680e0 Correct check for endianness
* interp.c: (target_big_endian): target endianess recognition fix.
2017-06-02 08:04:59 -07:00
Yao Qi 003ca0fd22 Refactor disassembler selection
Nowadays, opcodes/disassemble.c:disassembler selects the proper
disassembler according to ABFD only.  However, it actually
selects disassemblers according to arch, mach, endianess, and
abfd.  This patch adds them to the parameters of disassembler,
so that its caller can still select disassemblers in case that
abfd is NULL (a typical case in GDB).

There isn't any functionality change.

binutils:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* objdump.c (disassemble_data): Caller update.

include:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* dis-asm.h (disassembler): Update declaration.

opcodes:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* disassemble.c (disassembler): Add arguments a, big and mach.
	Use them.

sim/common:

2017-05-24  Yao Qi  <yao.qi@linaro.org>

	* sim-trace.c (trace_disasm): Caller update.
2017-05-24 17:23:52 +01:00
Jim Wilson bf1554384b Fix ldn/stn multiple instructions. Fix testcases with unaligned data.
sim/aarch64/
	* simulator.c (vec_load): Add M argument.  Rewrite to iterate over
	registers based on structure size.
	(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
	(LD1_1): Replace with call to vec_load.
	(vec_store): Add new M argument.  Rewrite to iterate over registers
	based on structure size.
	(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
	(ST1_1): Replace with call to vec_store.

	sim/testsuite/sim/aarch64/
	* fcvtz.s, fstur.s, ldn_single.s, ldnr.s, mla.s, mls.s, uzp.s: Align
	data.
	* sumulh.s: Delete unnecessary data alignment.
	* stn_single.s: Align data.  Fix unaligned ldr insns.  Adjust cmp
	arguments to match change.
	* ldn_multiple.s, stn_multiple.s: New.
2017-04-22 16:36:01 -07:00
Jim Wilson b630840c9c Add support for fcvtl and fcvtl2.
sim/aarch64/
	* simulator.c (do_vec_FCVTL): New.
	(do_vec_op1): Call do_vec_FCVTL.

	sim/testsuite/sim/aarch64/
	* fcvtl.s: New.
2017-04-08 12:08:20 -07:00
Jim Wilson ae27d3fe76 Support the fcmXX zero instructions.
sim/aarch64/
	* simulator.c (do_scalar_FCMGE_zero): New.
	(do_scalar_FCMLE_zero, do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero)
	(do_scalar_FCMLT_zero): Likewise.
	(do_scalar_vec): Add calls to new functions.

	sim/testsuite/sim/aarch64/
	* fcmXX.s: New.
2017-04-08 07:10:38 -07:00
Jim Wilson f124168208 Fix bug with cmn/adds where C flag was incorrectly set.
sim/aarch64/
	* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
	flag check.

	sim/testsuite/sim/aarch64/
	* adds.s: Add checks for values -2 and 1, where C is not set.
2017-03-25 20:32:02 -07:00
Jim Wilson 8ecbe595e6 Fix umulh and smulh bugs. Fix bugs in last week's sumov.s testsuite.
sim/aarch64/
	* simulator.c (mul64hi): Shift carry left by 32.
	(smulh): Change signum to negate.  If negate, invert result, and add
	carry bit if low part of multiply result is zero.

	sim/testsuite/sim/aarch64/
	* sumov.s: Correct compare test values.
	* sumulh.s: New.
2017-03-03 13:10:45 -08:00
Jim Wilson 152e1e1bc9 Add missing smov support, and clean up existing umov support.
sim/aarch64/
	* simulator.c (do_vec_SMOV_into_scalar): New.
	(do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
	Rewritten.
	(do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
	(do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
	do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
	do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.

	sim/testsuite/sim/aarch64/
	* sumov.s: New.
2017-02-25 20:06:36 -08:00
Jim Wilson ac189e7bf8 Add missing cnt (popcount) instruction support.
sim/aarch64/
	* simulator.c (popcount): New.
	(do_vec_CNT): New.
	(do_vec_op1): Add do_vec_CNT call.

	sim/testsuite/sim/aarch64/
	* cnt.s: New.
2017-02-25 20:04:09 -08:00
Jim Wilson 2e7e5e2890 Fix for aarch64 sim sxtl/uxtl insns, plus another fix for addv.
sim/aarch64/
	* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
	with type set to input type size.
	(do_vec_xtl): Change bias from 3 to 4 for byte case.

	sim/testsuite/sim/aarch64/
	* bit.s: Change cmp immediates to account for addv bug fix.
	* cmtst.s, ldn_single.s, stn_single.s: Likewise.
	* xtl.s: New.
2017-02-19 13:16:56 -08:00
Jim Wilson 742e3a7781 Add self to aarch64 maintainers. Fix mla instruction.
sim/
	* MAINTAINTERS (aarch64): Add myself.

	sim/aarch64/
	* simulator.c (do_vec_MLA): Rewrite switch body.

	sim/testsuite/sim/aarch64/
	* mla.s: New.
2017-02-14 15:23:12 -08:00
Jim Wilson bf25e9a0f1 Fix bit/bif instructions.
sim/aarch64/
	* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
	2.  Move test_false if inside loop.  Fix logic for computing result
	stored to vd.

	sim/testsuite/sim/aarch64
	* bit.s: New.
2017-02-14 14:35:57 -08:00
Jim Wilson e8f42b5e36 Add ldn/stn single support, fix ldnr support.
sim/aarch64/
	* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
	(do_vec_LDn_single, do_vec_STn_single): New.
	(do_vec_LDnR): Add and set new nregs var.  Replace switch on nregs with
	loop over nregs using new var n.  Add n times size to address in loop.
	Add n to vd in loop.
	(do_vec_load_store): Add comment for instruction bit 24.  New var
	single to hold instruction bit 24.  Add new code to use single.  Move
	ldnr support inside single if statements.  Fix ldnr register counts
	inside post if statement.  Change HALT_NYI calls to HALT_UNALLOC.

	sim/testsuite/sim/aarch64/
	* ldn_single.s: New.
	* ldnr.s: New.
	* stn_single.s: New.
2017-02-14 14:31:03 -08:00
Mike Frysinger 13a590ca65 sim: use ARRAY_SIZE instead of ad-hoc sizeof calculations 2017-02-13 01:26:21 -05:00
Jim Wilson fbf32f638c Add support for cmtst.
sim/aarch64/
	* simulator.c (do_vec_compare): Add case 0x23 for CMTST.

	sim/testsuite/sim/aarch64/
	* cmtst.s: New.
2017-01-23 17:26:53 -08:00
Jim Wilson 05b3d79d26 Fixes for addv and xtn2 instructions.
sim/aarch64/
	* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
	aarch64_set_reg_u64.  In case 2, call HALT_UNALLOC if not full.  In
	case 3, call HALT_UNALLOC unconditionally.
	(do_vec_XTN): Delete shifts.  In case 2, change index from i + 4 to
	i + 2.  Delete if on bias, change index to i + bias * X.

	sim/testsuite/sim/aarch64/
	* addv.s: New.
	* xtn.s: New.
2017-01-17 16:11:09 -08:00
Jim Wilson a4fb5981b7 Fix problems with the implementation of the uzp1 and uzp2 instructions.
sim/aarch64/
	* simulator.c (do_vec_UZP): Rewrite.
	sim/testsuite/sim/aarch64/
	* uzp.s: New.
2017-01-09 15:44:57 -08:00
Jim Wilson c0386d4d54 Five fixes, for fcsel, fcvtz, fminnm, mls, and non-widening mul.
sim/aarch64/
	* cpustate.c: Include math.h.
	(aarch64_set_FP_float): Use signbit to check for signed zero.
	(aarch64_set_FP_double): Likewise.
	* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
	(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
	args same size as third arg.
	(fmaxnm): Use isnan instead of fpclassify.
	(fminnm, dmaxnm, dminnm): Likewise.
	(do_vec_MLS): Reverse order of subtraction operands.
	(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
	aarch64_get_FP_float to get source register contents.
	(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
	DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
	DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
	(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
	raise_exception calls.

	sim/testsuite/sim/aarch64/
	* fcsel.s: New.
	* fcvtz.s: New.
	* fminnm.s: New.
	* mls.s: New.
	* mul.s: New.
2017-01-04 16:07:50 -08:00
Joel Brobecker 61baf725ec update copyright year range in GDB files
This applies the second part of GDB's End of Year Procedure, which
updates the copyright year range in all of GDB's files.

gdb/ChangeLog:

        Update copyright year range in all GDB files.
2017-01-01 10:52:34 +04:00
Jim Wilson 87903eafb0 Fix bugs with float compare and Inf operands.
sim/aarch64/
	* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
	Add comment to document NaN issue.
	(set_flags_for_double_compare): Likewise.

	sim/testsuite/sim/aarch64/
	* fcmp.s: New.
2016-12-21 12:33:12 -08:00
Maciej W. Rozycki cadf97cf20 MAINTAINERS: Add myself as a MIPS maintainer
* MAINTAINERS (Maintainers for particular sims): Add myself as
	a MIPS maintainer.
2016-12-14 22:19:08 +00:00
Jim Wilson 963201cf5d Fix aarch64 sim bug with adds64, and add testcases for last 3 bug fixes.
sim/aarch64
	* simulator.c (NEG, POS): Move before set_flags_for_add64.
	(set_flags_for_add64): Replace with a modified copy of
	set_flags_for_sub64.

	sim/testsuite/sim/aarch64
	* testutils.inc (pass): Move .Lpass to start.
	(fail): Move .Lfail to start.  Return 1 instead of 0.
	(start): Moved .Lpass and .Lfail to here.
	* adds.s: New.
	* fstur.s: New.
	* tbnz.s: New.
2016-12-13 08:44:31 -08:00
Jim Wilson 668650d58d Fix bugs with tbnz/tbz instructions.
sim/aarch64
	* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
	(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
2016-12-03 17:29:44 -08:00
Jim Wilson 88256e713c Fix typo in ChangeLog entry. 2016-12-01 09:07:55 -08:00
Jim Wilson 88ddd4a1ef Fix bug with FP stur instructions.
sim/aarch64
	* simulator.c (fsturs): Switch use of rn and st variables.
	(fsturd, fsturq): Likewise
2016-12-01 09:06:07 -08:00
Mike Frysinger 6cb2202baa sim: mips: add PR info to ChangeLog 2016-11-12 01:02:23 -05:00
Mike Frysinger 91588b3af8 sim: mips: fix dv-tx3904cpu build error
When building for mipstx39-rtems4.12 targets, some funcs use SD and CPU
implicitly.  Restore the defines for these to the local sd and cpu vars.

This was broken by the clean up in commit d47f5b30d8.

Reported-by: Joel Sherrill <joel.sherrill@oarcorp.com>
2016-11-11 01:29:21 -05:00
Mike Frysinger e04659e860 sim: mips: fix builds for r3900 cpus due to missing check_u64 2016-11-11 01:28:36 -05:00
Mike Frysinger 333ec25d7e sim: avr: move changelog entries to subdir 2016-10-18 01:04:53 -04:00
Mike Frysinger fa0843f502 sim: m68hc11: use standard STATIC_INLINE helper
Rather than redefine inline locally, use the common STATIC_INLINE.
2016-08-16 06:12:39 -07:00
Mike Frysinger 5357150c97 sim: unify symbol table handling
The common sim tracing code already handles loading and tracking of
symbols from the target program so that it can show symbol info in
trace/disassembly calls.  Once we touch up the trace code and add a
few API callbacks, ports don't need to do loading and searching of
symbol tables themselves anymore.
2016-08-15 07:00:11 -07:00
Mike Frysinger 6f64fd48c5 sim: m68hc11: standardize sim_cpu naming
We use "sim_cpu *cpu" in the sim code base, not "struct _sim_cpu" or
the name "proc", so clean up this sim to follow along.
2016-08-13 22:54:05 -07:00
Mike Frysinger 527aaa4a31 sim: m68hc11: fix up various prototype related warnings
A few funcs are only used locally, so mark them static to avoid warnings
due to -Wmissing-prototypes.

Some funcs cast the return value wrong, so drop them (and let void * just
work by default).

Update some prototypes to be new style.
2016-08-13 22:46:27 -07:00
Mike Frysinger 4c171e25a8 sim: cgen: constify mode_names 2016-08-13 22:38:04 -07:00
Mike Frysinger 6b97945424 sim: cgen: drop unused argv/envp definitions
The common argv/envp are used now by all ports, so drop this old
cgen fragment.
2016-08-13 13:47:27 -07:00
Mike Frysinger 474a2d9f5f sim: bfin: split out common mach/model defines into arch.h [PR sim/20438]
The current machs.h mixes common enums with Blackfin-specific defines.
This causes us troubles with header inclusion order such that we can't
drop the old SIM_CPU typedef (which is duplicated in common code).  By
splitting the two up, we can unwind this dependency chain, and drop the
old typedef.  It also fixes building with older gcc versions.
2016-08-13 12:47:11 -07:00
Nick Clifton b14bdb3bab Undo the previous change to the aarch64 sim - exporting aarch64_step() - and instead make aarch64_run correctly process sim events.
* simulator.c (aarch64_step): Revert pervious delta.
	(aarch64_run): Call sim_events_tick after each
	instruction is simulated, and if necessary call
	sim_events_process.
	* simulator.h: Revert previous delta.
2016-08-12 11:35:32 +01:00
Nick Clifton 6a2775793d Export the single step function from the AArch64 simulator.
* interp.c (sim_create_inferior): Allow for being called with a
	NULL abfd parameter.  If a bfd is provided, initialise the sim
	with that start address.
	* simulator.c (HALT_NYI): Just print out the numeric value of the
	instruction when not tracing.
	(aarch64_step): Change from static to global.
	* simulator.h: Add a prototype for aarch64_step().
2016-08-11 15:04:40 +01:00
Alan Modra 293acfae4e Wean gdb and sim off private libbfd.h header
The major reason this header was needed, bfd_default_set_arch_mach,
has now moved to bfd.h.

gdb/
	* amd64-darwin-tdep.c: Don't include libbfd.h.
	* i386-darwin-tdep.c: Likewise.
	* rs6000-nat.c: Likewise.
	* rs6000-tdep.c: Likewise.
sim/aarch64/
	* memory.c: Don't include libbfd.h.
sim/rl78/
	* load.c: Don't include libbfd.h.
	(rl78_load): Don't use private iovec seek or read.
sim/rx/
	* load.c: Don't include libbfd.h.
	(rx_load): Don't use private iovec seek or read.
2016-07-27 09:01:45 +09:30
Nick Clifton 0c66ea4c5e Fix typo fsqrt -> sqrtf. 2016-07-21 09:23:16 +01:00
Nick Clifton 0f118bc7a6 Use fsqrt() to calculate float (rather than double) square root.
* simulator.c (fsqrts): Use fsqrt rather than sqrt.
2016-07-21 09:19:24 +01:00
Denis Chertykov 59f48f5a45 Update PC when simulate break instruction.
PR target/ 19401
	* avr/interp.c (step_once): Pass break instruction address to
	sim_engine_halt function which writes that to PC. Remove code that
	follows that function call as it is unreachable.
2016-07-19 09:47:23 +03:00
Nick Clifton 7df94786e4 Small improvements to the ARM simulator to cope with illegal binaries.
* armemu.c (Multiply64): Only issue error messages about invalid
	arguments if debugging is enabled.
	* armos.c (ARMul_OSHandleSWI): Ignore invalid flags.
2016-07-14 10:38:07 +01:00
Jim Wilson c7be441465 Add support for simulating big-endian AArch64 binaries.
* cpustate.h: Include config.h.
	(union GRegisterValue): Add WORDS_BIGENDIAN check.  For big endian code
	use anonymous structs to align members.
	* simulator.c (aarch64_step): Use sim_core_read_buffer and
	endian_le2h_4 to read instruction from pc.
2016-06-30 09:10:41 +01:00
Nick Clifton fd7ed446fb Add support for FMLA (by element) to AArch64 sim.
* simulator.c (do_FMLA_by_element): New function.
	(do_vec_op2): Call it.
2016-05-06 10:35:33 +01:00
Nick Clifton 7881f69ee9 Fix a typo in the check for SNANs in the RX simulator.
PR target/20000
	* fpu.c (check_exceptions): Fix typo checking for signalling
	NANs.
2016-04-27 12:37:11 +01:00