* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
Use "source" rather than "destination" for microMIPS "G".
gas/
* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
* elfxx-mips.h (_bfd_mips_elf_get_synthetic_symtab): New
prototype.
* elf32-mips.c (elf_backend_plt_sym_val): Remove macro.
(bfd_elf32_get_synthetic_symtab): New macro.
* elfxx-mips.c (plt_entry): New structure.
(mips_elf_link_hash_entry): Add use_plt_entry member.
(mips_elf_link_hash_table): Rename plt_entry_size member to
plt_mips_entry_size. Add plt_comp_entry_size, plt_mips_offset,
plt_comp_offset, plt_got_index entries and plt_header_is_comp
members.
(STUB_LW_MICROMIPS, STUB_MOVE_MICROMIPS): New macros.
(STUB_LUI_MICROMIPS, STUB_JALR_MICROMIPS): Likewise.
(STUB_ORI_MICROMIPS, STUB_LI16U_MICROMIPS): Likewise.
(STUB_LI16S_MICROMIPS): Likewise.
(MICROMIPS_FUNCTION_STUB_NORMAL_SIZE): Likewise.
(MICROMIPS_FUNCTION_STUB_BIG_SIZE): Likewise.
(micromips_o32_exec_plt0_entry): New variable.
(mips16_o32_exec_plt_entry): Likewise.
(micromips_o32_exec_plt_entry): Likewise.
(mips_elf_link_hash_newfunc): Initialize use_plt_entry.
(mips_elf_output_extsym): Update to use gotplt_union's plist
member rather than offset.
(mips_elf_gotplt_index): Likewise. Remove the VxWorks
restriction. Use MIPS_ELF_GOT_SIZE to calculate GOT address.
(mips_elf_count_got_symbols): Update to use gotplt_union's plist
member rather than offset.
(mips_elf_calculate_relocation): Handle MIPS16/microMIPS PLT
entries.
(_bfd_mips_elf_create_dynamic_sections): Don't set PLT sizes
here.
(mips_elf_make_plt_record): New function.
(_bfd_mips_elf_check_relocs): Update comment. Record occurences
of JAL relocations that might need a PLT entry.
(_bfd_mips_elf_adjust_dynamic_symbol): Update to use
gotplt_union's plist member rather than offset. Set individual
PLT entry sizes here. Handle MIPS16/microMIPS PLT entries.
Don't set the symbol's value in the symbol table for PLT
references here. Don't set the PLT or PLT GOT section sizes
here.
(mips_elf_estimate_stub_size): Handle microMIPS stubs.
(mips_elf_allocate_lazy_stub): Likewise.
(mips_elf_lay_out_lazy_stubs): Likewise. Define a _MIPS_STUBS_
magic symbol.
(mips_elf_set_plt_sym_value): New function.
(_bfd_mips_elf_size_dynamic_sections): Set PLT header size and
PLT and PLT GOT section sizes here. Set the symbol values in
the symbol table for PLT references here. Handle microMIPS
annotation of the _PROCEDURE_LINKAGE_TABLE_ magic symbol.
(_bfd_mips_elf_finish_dynamic_symbol): Update to use
gotplt_union's plist member rather than offset. Handle
MIPS16/microMIPS PLT entries. Handle microMIPS stubs.
(_bfd_mips_vxworks_finish_dynamic_symbol): Update to use
gotplt_union's plist member rather than offset. Use
MIPS_ELF_GOT_SIZE to calculate GOT address.
(mips_finish_exec_plt): Handle microMIPS PLT. Return status.
(_bfd_mips_elf_finish_dynamic_sections): Handle result from
mips_finish_exec_plt.
(_bfd_mips_elf_link_hash_table_create): Update to use
gotplt_union's plist member rather than offset.
(_bfd_mips_elf_get_synthetic_symtab): New function.
include/elf/
* mips.h (ELF_ST_IS_MIPS_PLT): Respect STO_MIPS16 setting.
(ELF_ST_SET_MIPS_PLT): Likewise.
gdb/
* mips-tdep.c (mips_elf_make_msymbol_special): Handle MIPS16 and
microMIPS synthetic symbols.
ld/
* emulparams/elf32btsmip.sh: Arrange for .got.plt to be placed
as close to .plt as possible.
* scripttempl/elf.sc: Handle $INITIAL_READWRITE_SECTIONS and
$PLT_NEXT_DATA variables.
ld/testsuite/
* ld-mips-elf/jalx-2.dd: Update for microMIPS PLT support.
* ld-mips-elf/pic-and-nonpic-3a.dd: Update for the _MIPS_STUBS_
magic symbol.
* ld-mips-elf/pic-and-nonpic-3b.dd: Likewise.
* ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise.
* ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise.
* ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise.
* ld-mips-elf/stub-dynsym-1-10000.d: Likewise.
* ld-mips-elf/stub-dynsym-1-2fe80.d: Likewise.
* ld-mips-elf/stub-dynsym-1-7fff.d: Likewise.
* ld-mips-elf/stub-dynsym-1-8000.d: Likewise.
* ld-mips-elf/stub-dynsym-1-fff0.d: Likewise.
* ld-mips-elf/tlslib-o32.d: Likewise.
opcodes/
* mips-dis.c (is_mips16_plt_tail): New function.
(print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
word.
(is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
2013-06-08 Catherine Moore <clm@codesourcery.com>
* config/tc-mips.c (is_opcode_valid): Build ASE mask.
(is_opcode_valid_16): Pass ase value to opcode_is_member.
(append_insn): Change INSN_xxxx to ASE_xxxx.
include/
2013-06-08 Catherine Moore <clm@codesourcery.com>
* opcode/mips.h (mips_opcode): Add ase field.
(INSN_ASE_MASK): Delete.
(INSN_DSP): Rename to ASE_DSP. Provide new value.
(INSN_DSPR2): Rename to ASE_DSPR2. Provide new value.
(INSN_MCU): Rename to ASE_MCU. Provide new value.
(INSN_MDMX): Rename to ASE_MDMX. Provide new value.
(INSN_MIPS3d): Rename to ASE_MIPS3D. Provide new value.
(INSN_MT): Rename to ASE_MT. Provide new value.
(INSN_SMARTMIPS): Rename to ASE_SMARTMIPS. Provide new value.
(INSN_VIRT): Rename to ASE_VIRT. Provide new value.
(INSN_VIRT64): Rename to ASE_VIRT64. Provide new value.
(opcode_is_member): Add ase argument. Check ase.
opcodes/
2013-06-08 Catherine Moore <clm@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>
* micromips-opc.c (D32, D33, MC): Update definitions.
(micromips_opcodes): Initialize ase field.
* mips-dis.c (mips_arch_choice): Add ase field.
(mips_arch_choices): Initialize ase field.
(set_default_mips_dis_options): Declare and setup mips_ase.
* mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
MT32, MC): Update definitions.
(mips_builtin_opcodes): Initialize ase field.
* doc/binutils.texi: Document -Mvirt disassembler option.
gas/ChangeLog:
* config/tc-mips.c (struct mips_set_options): New ase_virt field.
(mips_opts): Update for the new field.
(file_ase_virt): New variable.
(ISA_SUPPORTS_VIRT_ASE): New macro.
(ISA_SUPPORTS_VIRT64_ASE): New macro.
(MIPS_CPU_ASE_VIRT): New define.
(is_opcode_valid): Handle ase_virt.
(macro_build): Handle "+J".
(validate_mips_insn): Likewise.
(mips_ip): Likewise.
(enum options): Add OPTION_VIRT and OPTION_NO_VIRT.
(md_longopts): Add mvirt and mnovirt
(md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT.
(mips_after_parse_args): Handle ase_virt field.
(s_mipsset): Handle "virt" and "novirt".
(mips_elf_final_processing): Add a comment about virt ASE might need a new flag.
(md_show_usage): Print out the usage of -mvirt and mno-virt options.
* doc/c-mips.texi: Document -mvirt and -mno-virt.
Document ".set virt" and ".set novirt".
gas/testsuite/ChangeLog:
* gas/mips/mips.exp: Run virt and virt64 testcases.
* gas/mips/virt.d: New file.
* gas/mips/virt.s: New file.
* gas/mips/virt64.d: New file.
* gas/mips/virt64.s: New file.
include/opcode/ChangeLog:
* mips.h (OP_MASK_CODE10): Correct definition.
(OP_SH_CODE10): Likewise.
Add a comment that "+J" is used now for OP_*CODE10.
(INSN_ASE_MASK): Update.
(INSN_VIRT): New macro.
(INSN_VIRT64): New macro
opcodes/ChangeLog:
* mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2 .
Add INSN_VIRT and INSN_VIRT64 to mips64r2.
(parse_mips_dis_option): Handle the virt option.
(print_insn_args): Handle "+J".
(print_mips_disassembler_options): Print out message about virt64.
* mips-opc.c (IVIRT): New define.
(IVIRT64): New define.
(mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
Move rfe to the bottom as it conflicts with tlbgp.
* config.bfd (msp430): Define targ_selvecs.
* configure.in: Add bfd_elf32_msp430_ti_vec.
* cpu-msp430.c: Add some more MSP430 machine numbers.
* elf32-msp430.c Add support for MSP430X relocations.
Add support for TI compiler generated relocations.
Add support for sym_diff relocations.
Add support for relaxing out of range short branches into long
branches.
Add support for MSP430 attribute section.
* reloc.c: Add MSP430X relocations.
* targets.c: Add bfd_elf32_msp430_ti_vec.
* bfd-in2.h: Regenerate.
* configure: Regenerate.
* libbfd.h: Regenerate.
* readelf.c: Add support for MSP430X architecture.
* readelf.exp: Expect -wi test to fail for the MSP430.
* config/tc-msp430.c: Add support for the MSP430X architecture.
Add code to insert a NOP instruction after any instruction that
might change the interrupt state.
Add support for the LARGE memory model.
Add code to initialise the .MSP430.attributes section.
* config/tc-msp430.h: Add support for the MSP430X architecture.
* doc/c-msp430.texi: Document the new -mL and -mN command line
options.
* NEWS: Mention support for the MSP430X architecture.
* gas/all/gas.exp: Skip the DIFF1 test for the MSP430.
Expect the FORWARD test to pass for the MSP430.
Skip the REDEF tests for the MSP430.
Expect the 930509A test to fail for the MSP430.
* gas/all/sleb128-4.d: Skip for the MSP430.
* gas/elf/elf.exp: Set target_machine to msp430 for the MSP430.
Skip the EHOPT0 test for the MSP430.
Skip the REDEF and EQU-RELOC tests for the MSP430.
* gas/elf/section2.e-msp430: New file.
* gas/lns/lns-big-delta.d: Remove expectation of 20-bit
addresses.
* gas/lns/lns.exp: Use alternate LNS COMMON test for the MSP430.
* gas/msp430/msp430x.s: New test.
* gas/msp430/msp430x.d: Expected disassembly.
* gas/msp430/msp430.exp: Run new test.
* gas/msp430/opcode.d: Update expected disassembly.
* msp430.h: Add MSP430X relocs.
Add some more MSP430 machine numbers.
Add values used by .MSP430.attributes section.
* msp430.h: Add patterns for MSP430X instructions.
* Makefile.am: Add emsp430X.c
* Makefine.in: Regenerate.
* configure.tgt (msp430): Add msp430X emulation.
* ldmain.c (multiple_definition): Only disable relaxation if it
was enabled by the user.
* ldmain.h (RELAXATION_ENABLED_BY_USER): New macro.
* emulparams/msp430all.sh: Add support for MSP430X.
* emultempl/generic.em: (before_parse): Enable relaxation for the
MSP430.
* scripttempl/msp430.sc: Reorganize sections. Add .rodata
section.
* scripttempl/msp430_3.sc: Likewise.
* NEWS: Mention support for MSP430X.
* ld-elf/flags1.d: Expect this test to pass on the MSP430.
* ld-elf/init-fini-arrays.d: Expect this test to fail on the
MSP430.
* ld-elf/merge.d: Expect this test to pass on the MSP430.
* ld-elf/sec64k.exp: Skip these tests for the MSP430.
* ld-gc/pr13683.d: Expect this test to fail on the MSP430.
* ld-srec/srec.exp: Expect these tests to fail on the MSP430.
* ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to
fail on the MSP430.
* msp430-dis.c: Add support for MSP430X instructions.
Make current with UA2011 specification.
Add an F_PREFERRED opcode flag that indicates a preferred alias
when multiple aliases for the same opcode exists.
For 'lzd':
Add 'lzcnt' as primary instruction, and make 'lzd' an alias.
Add 'ldtw', 'ldtwa', 'sttw', 'sttwa':
The modern opcode for for 'ldd', 'ldda', 'std', and 'stda' on
integer registers. Mark the latter now as aliases.
For 'flush':
Support "[address]" syntax as well as plain "address".
Rework 'mov' aliases for 'wr':
Eliminate bogus three operand moves, and encode the
instructions properly for the "mov REG, %ASR" cases,
specifically we should encode the register in rs2 not rs1 as
per The SPARC V8 Architecture Manual.
Add missing cbcond aliases:
c{w,x}bz, c{w,x}blu, c{w,x}bnz, c{w,x}bgeu
Add 'd' suffix VIS logical ops:
The primary opcode for 'fzero' is now 'fzerod' (compare with
'fzeros'), for example. And thus 'fzero' is now an alias.
Add modern opcodes for condition code setting edge instructions:
They are now edgeN{,l}cc instead of plain edgeN{,l}.
Add modern opcodes for VIS comparisons:
All VIS comparisons now start with prefix "fp", retain the
older variants as aliases.
The signed variants for equal and not-equal have "u" aliases
to show that these comparisons are equally suited for unsigned
compares.
Update existing test cases as needed, and add several new ones.
include/opcode/
* sparc.h (F_PREFERRED): Define.
(F_PREF_ALIAS): Define.
opcodes/
* sparc-dis.c (compare_opcodes): When encountering multiple aliases
of an opcode, prefer the one with F_PREFERRED set.
* sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
ops. Make 64-bit VIS logical ops have "d" suffix in their names,
mark existing mnenomics as aliases. Add "cc" suffix to edge
instructions generating condition codes, mark existing mnenomics
as aliases. Add "fp" prefix to VIS compare instructions, mark
existing mnenomics as aliases.
gas/testsuite/
* gas/sparc/cbcond.s: Add tests for new opcode aliases.
* gas/sparc/cbcond.d: Updated.
* gas/sparc/hpcvis3.s: Add tests for new opcode aliases.
* gas/sparc/hpcvis3.d: Updated.
* gas/sparc/v8-movwr-imm.d: Fix expected disassembly.
* gas/sparc/edge.s: New test.
* gas/sparc/edge.d: Expected disassembly.
* gas/sparc/flush.s: New test.
* gas/sparc/flush.d: Expected disassembly.
* gas/sparc/ldd_std.s: New test.
* gas/sparc/ldd_std.d: Expected disassembly.
* gas/sparc/ldtw_sttw.s: New test.
* gas/sparc/ldtw_sttw.d: Expected disassembly.
* gas/sparc/sparc.exp: Run new tests.
(bfd_elf32_bfd_is_target_special_symbol): Define.
* v850.h (V850_INVERSE_PCREL): Define.
* v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
destination address by subtracting the operand from the current
address.
* v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
a positive value in the insn.
(extract_u16_loop): Do not negate the returned value.
(D16_LOOP): Add V850_INVERSE_PCREL flag.
(ceilf.sw): Remove duplicate entry.
(cvtf.hs): New entry.
(cvtf.sh): Likewise.
(fmaf.s): Likewise.
(fmsf.s): Likewise.
(fnmaf.s): Likewise.
(fnmsf.s): Likewise.
(maddf.s): Restrict to E3V5 architectures.
(msubf.s): Likewise.
(nmaddf.s): Likewise.
(nmsubf.s): Likewise.
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
and xor.
* gas/tic6x/insns16-lsd-unit.d: Update expected output.
* tic6x-opcode-table.h: Rename mpydp's specific operand type macro
from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
tic6x_operand_xregpair operand coding type.
Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
opcode field, usu ORXREGD1324 for the src2 operand and remove the
TIC6X_FLAG_NO_CROSS.
* gas/tic6x/insns-bad-1.s: Remove test-case for mpydp with
cross-path.
* gas/tic6x/insns-bad-1.l: Update expected output.
* gas/tic6x/insns-c674x.s: Add a test-case for mpydp with
cross-path.
* gas/tic6x/insns-c674x.d: Update expected output.
order to encode separately the msb and lsb of a register pair ; this will be
needed to encode the opcodes the same
way as Ti assembler does.
* gas/config/tc-tic6x.c: handle tic6x_coding_dreg_(msb|lsb) field coding types
and use it to encode register pair numbers when required.
* opcodes/tic6x-dis.c: decodes opcodes that have individual msb and lsb halves
in src1 & src2 fields ; discard the src1 (lsb) value and only use src2 (msb),
discarding bit 0, to follow what Ti SDK does in that case as any value in the
src1 field yields the same output with SDK disassembler.
* include/opcode/tic6x-opcode-table.h: modify absdp, dpint, dpsp, dptrunc,
rcpdp and rsqrdp opcodes to use the new field coding types.
* gas/testsuite/gas/tic6x/insns-c674x.d, gas/testsuite/gas/tic6x/insns-c674x.s
: add test case for the newly generated opcode but keep the old ones as they
seem legit as per Ti disassembler output.
* elf.c (elfcore_write_s390_tdb): New function.
(elfcore_write_register_note): Call it.
(elfcore_grok_s390_tdb): New function.
(elfcore_grok_note): Call it.
* readelf.c (get_note_type): Add NT_S390_TDB.
to the plugin API. This patch helps preventing problems while
cherry-picking plugin-api.h changes from trunk gold to local branches.
For instance, a linker plugin compiled with a cherry-picked
plugin-api.h header with some enum values missing will behave
strangely when used with a linker built with the up to date header.
* plugin-api.h (enum ld_plugin_level): Assign integers
explicitly for all values.
* tic6x-opcode-table.h: Fix encoding of BNOP instruction.
* gas/tic6x/insns-c674x-pcrel.s: Add test of BNOP instruction
within header based fetch packet.
* gas/tic6x/insns-c674x-pcrel.d: Update expected disassembly.
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
opcodes/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
* aarch64-opc.c (operand_general_constraint_met_p): For
AARCH64_MOD_LSL, move the range check on the shift amount before the
alignment check; change to call set_sft_amount_out_of_range_error
instead of set_imm_out_of_range_error.
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
SIMD_IMM_SFT.
gas/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* config/tc-aarch64.c (output_operand_error_record): Change to output
the out-of-range error message as value-expected message if there is
only one single value in the expected range.
(programmer_friendly_fixup): Remove the handling of 8-bit MOVI with
LSL #0 as a programmer-friendly feature.
gas/testsuite/
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/movi.s: Add tests.
* gas/aarch64/movi.d: Update.
* gas/aarch64/programmer-friendly.s: Add comment.
