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26 Commits

Author SHA1 Message Date
Alan Modra
b3adc24a07 Update year range in copyright notice of binutils files 2020-01-01 18:42:54 +10:30
Alan Modra
827041555a Update year range in copyright notice of binutils files 2019-01-01 22:06:53 +10:30
Alan Modra
030157d8a6 Make _bfd_error_handler available outside libbfd 
Needed when building libopcodes.so.

bfd/
	* bfd.c (_bfd_error_handler): Arrange for this function to be
	declared in bfd-in2.h.
	* libbfd-in.h (_bfd_error_handler): Don't declare.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
opcodes/
	* sysdep.h (_bfd_error_handler): Don't declare.
	* msp430-decode.opc: Include bfd.h.  Don't include ansidecl.h here.
	* rl78-decode.opc: Likewise.
	* msp430-decode.c: Regenerate.
	* rl78-decode.c: Regenerate.
 2018-06-01 13:10:33 +09:30
Alan Modra
a6743a5420 opcodes error messages 
Another patch aimed at making binutils comply with the GNU coding
standard.  The generated files require
https://sourceware.org/ml/cgen/2018-q1/msg00004.html

cpu/
	* frv.opc: Include opintl.h.
	(add_next_to_vliw): Use opcodes_error_handler to print error.
	Standardize error message.
	(fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise.
opcodes/
	* sysdep.h (opcodes_error_handler): Define.
	(_bfd_error_handler): Declare.
	* Makefile.am: Remove stray #.
	* opc2c.c (main): Remove bogus -l arg handling.  Print "DO NOT
	EDIT" comment.
	* aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
	* d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
	* riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
	opcodes_error_handler to print errors.  Standardize error messages.
	* msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
	and include opintl.h.
	* nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
	* i386-gen.c: Standardize error messages.
	* msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
	* Makefile.in: Regenerate.
	* epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
	* epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
	* fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
	* frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
	* iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
	* lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
	* m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
	* m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
	* mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
	* mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
	* or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
	* xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
	* xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
 2018-03-03 11:34:26 +10:30
Alan Modra
219d1afa89 Update year range in copyright notice of binutils files 2018-01-03 17:49:56 +10:30
Nick Clifton
63323b5b23 Fix address violation when disassembling a corrupt RL78 binary. 
PR binutils/21588
	* rl78-decode.opc (OP_BUF_LEN): Define.
	(GETBYTE): Check for the index exceeding OP_BUF_LEN.
	(rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
	array.
	* rl78-decode.c: Regenerate.
 2017-06-15 12:37:01 +01:00
Alan Modra
2571583aed Update year range in copyright notice of all files. 2017-01-02 14:08:56 +10:30
Nick Clifton
4d82fe66e8 Fix display of RL78 MOVW instructions that use the stack pointer. 
* rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
	instructions that can support stack pointer operations.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c: Fix display of stack pointer in MOVW based
	instructions.

	* testsuite/gas/rl78/sp-relative-movw.s: New test.
	* testsuite/gas/rl78/sp-relative-movw.d: Expected disassembly.
	* testsuite/gas/rl78/rl78.exp: Run the new test.
 2016-01-14 16:23:35 +00:00
Alan Modra
6f2750feaf Copyright update for binutils 2016-01-01 23:00:01 +10:30
DJ Delorie
1eac08cc37 rl78: Enable MULU for all ISAs. 
Unlike other mul/div opcodes, MULU is available on all variants
of the RL78.

* rl78-decode.opc: Enable MULU for all ISAs.
* rl78-decode.c: Regenerate.
 2015-12-08 00:16:13 -05:00
Vinay Kumar
c2f2875869 Fix RL78 disassembly of DE+offset addressing to always show the offset, even when zero. 
PR binutils/19159
opcodes	* rl78-decode.opc (MOV): Added offset to DE register in index
	addressing mode.
	* rl78-decode.c: Regenerate.

test	* gas/rl78/pr19159.s: New test source file.
	* gas/rl78/pr19159.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
 2015-10-27 15:24:40 +00:00
Vinay Kumar
4666280441 Display system registers by their names when disassembling RL78 instructions. 
PR binutils/19158
opcodes	* rl78-decode.opc: Add 's' print operator to instructions that
	access system registers.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78_common): Decode all system
	registers.

tests	* gas/rl78/pr19158.s: New test source file.
	* gas/rl78/pr19158.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
 2015-10-27 14:49:02 +00:00
Vinay Kumar
02f12cd466 Fix RL78 disassembly so that SP+OFFSET addressing always shows the offset, even when zero. 
PR binutils/19157
opcodes	* rl78-decode.opc: Add 'a' print operator to mov instructions
	using stack pointer plus index addressing.
	* rl78-decode.c: Regenerate.

tests	* gas/rl78: New directory.
	* gas/rl78/rl78.exp: New test driver.
	* gas/rl78/pr19157.s: New test source file.
	* gas/rl78/pr19157.d: New test case.
 2015-10-27 14:00:40 +00:00
H.J. Lu
43e65147c0 Remove trailing spaces in opcodes 2015-08-12 04:45:07 -07:00
DJ Delorie
0952813b0b Make RL78 disassembler and simulator respect ISA for mul/div 
[gas]
	* config/rl78-defs.h (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.
	* config/rl78-parse.y (ISA_G10): New.
	(ISA_G13): New.
	(ISA_G14): New.
	(MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
	* config/tc-rl78.c (rl78_isa_g10): New.
	(rl78_isa_g13): New.
	(rl78_isa_g14): New.

[gdb]
	* rl78-tdep.c (rl78_analyze_prologue): Pass RL78_ISA_DEFAULT to
	rl78_decode_opcode

[include]
	* dis-asm.h (print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.
	* opcode/rl78.h (RL78_Dis_Isa): New.
	(rl78_decode_opcode): Add ISA parameter.

[opcodes]
	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

[sim]
	* rl78/cpu.c (g14_multiply): New.
	* rl78/cpu.h (g14_multiply): New.
	* rl78/load.c (rl78_load): Decode ISA completely.
	* rl78/main.c (main): Expand -M to include other ISAs.
	* rl78/rl78.c (decode_opcode): Decode based on ISA.
	* rl78/trace.c (rl78_disasm_fn): New.
	(sim_disasm_init): Reset it.
	(sim_disasm_one): Get correct disassembler for ISA.
 2015-04-30 15:25:49 -04:00
Vinay
fd63f640f6 Adds a space between the operands of the RL78's MOV instruction for consistency with the disassembling of other instructions. 
* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.
 2015-02-23 17:16:30 +00:00
Nick Clifton
90092e7305 Fixes a problem with the RL78 disassembler which would incorrectly disassemble [HL+0] as [HL]. 
* rl78-decode.opc: Add 'a' attribute to instructions that support
	[HL+0] addressing.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Display the offset in [HL+0]
	addresses.
 2015-02-11 14:36:39 +00:00
Alan Modra
b90efa5b79 ChangeLog rotatation and copyright year update 2015-01-02 00:53:45 +10:30
Alan Modra
4b95cf5c0c Update copyright years 2014-03-05 22:16:15 +10:30
Alan Modra
c7570fcd46 * rl78-decode.opc (rl78_decode_opcode): Fix typo. 
* rl78-decode.c: Regenerate.
 2013-02-27 03:00:44 +00:00
Nick Clifton
151fa98f80 * rl78-decode.opc: Fix encoding of DIVWU insn. 
* rl78-decode.c: Regenerate.

	* config/rl78-parse.y: Fix encoding of DIVWU insn.
 2013-02-25 18:41:06 +00:00
Nick Clifton
5bf135a788 Add copyright notices 2012-12-17 16:56:12 +00:00
DJ Delorie
3d557b4cce * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01] 
operands, so that data addresses can be corrected when not
ES-overridden.
* rl78-decode.c: Regenerate.
* rl78-dis.c (print_insn_rl78): Make order of modifiers
irrelevent.  When the 'e' specifier is used on an operand and no
ES prefix is provided, adjust address to make it absolute.
 2012-08-15 22:37:56 +00:00
Nick Clifton
df7b86aa4c PR 14072 
* configure.in: Add check that sysdep.h has been included before
	any system header files.
	* configure: Regenerate.
	* config.in: Regenerate.
	* sysdep.h: Generate an error if included before config.h.
	* alpha-opc.c: Include sysdep.h before any other header file.
	* alpha-dis.c: Likewise.
	* avr-dis.c: Likewise.
	* cgen-opc.c: Likewise.
	* cr16-dis.c: Likewise.
	* cris-dis.c: Likewise.
	* crx-dis.c: Likewise.
	* d10v-dis.c: Likewise.
	* d10v-opc.c: Likewise.
	* d30v-dis.c: Likewise.
	* d30v-opc.c: Likewise.
	* h8500-dis.c: Likewise.
	* i370-dis.c: Likewise.
	* i370-opc.c: Likewise.
	* m10200-dis.c: Likewise.
	* m10300-dis.c: Likewise.
	* micromips-opc.c: Likewise.
	* mips-opc.c: Likewise.
	* mips61-opc.c: Likewise.
	* moxie-dis.c: Likewise.
	* or32-opc.c: Likewise.
	* pj-dis.c: Likewise.
	* ppc-dis.c: Likewise.
	* ppc-opc.c: Likewise.
	* s390-dis.c: Likewise.
	* sh-dis.c: Likewise.
	* sh64-dis.c: Likewise.
	* sparc-dis.c: Likewise.
	* sparc-opc.c: Likewise.
	* spu-dis.c: Likewise.
	* tic30-dis.c: Likewise.
	* tic54x-dis.c: Likewise.
	* tic80-dis.c: Likewise.
	* tic80-opc.c: Likewise.
	* tilegx-dis.c: Likewise.
	* tilepro-dis.c: Likewise.
	* v850-dis.c: Likewise.
	* v850-opc.c: Likewise.
	* vax-dis.c: Likewise.
	* w65-dis.c: Likewise.
	* xgate-dis.c: Likewise.
	* xtensa-dis.c: Likewise.
	* rl78-decode.opc: Likewise.
	* rl78-decode.c: Regenerate.
	* rx-decode.opc: Likewise.
	* rx-decode.c: Regenerate.

	* configure.in: Add check that sysdep.h has been included before
	any system header files.
	* configure: Regenerate.
	* config.in: Regenerate.
	* sysdep.h: Generate an error if included before config.h.

	* configure.in: Add check that sysdep.h has been included before
	any system header files.
	* configure: Regenerate.
	* config.in: Regenerate.
	* aclocal.m4: Regenerate.
	* bfd-in.h: Generate an error if included before config.h.
	* sysdep.h: Likewise.
	* bfd-in2.h: Regenerate.
	* compress.c: Remove #include "config.h".
	* plugin.c: Likewise.
	* elf32-m68hc1x.c: Include sysdep.h before alloca-conf.h.
	* elf64-hppa.c: Likewise.
	* som.c: Likewise.
	* xsymc.c: Likewise.

	* configure.in: Add check that sysdep.h has been included before
	any system header files.
	* configure: Regenerate.
	* config.in: Regenerate.

	* configure.in: Add check that sysdep.h has been included before
	any system header files.
	* configure: Regenerate.
	* config.in: Regenerate.
	* aclocal.m4: Regenerate.
	* Makefile.am: Use wrappers around C files generated by flex.
	* Makefile.in: Regenerate.
	* doc/Makefile.in: Regenerate.
	* itbl-lex-wrapper.c: New file.
	* config/bfin-lex-wrapper.c: New file.
	* cgen.c: Include as.h before setjmp.h.
	* config/tc-dlx.c: Include as.h before any other header.
	* config/tc-h8300.c: Likewise.
	* config/tc-lm32.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mmix.c: Likewise.
	* config/tc-msp430.c: Likewise.
	* config/tc-or32.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic54x.c: Likewise.
	* config/tc-xtensa.c: Likewise.

	* configure.in: Add check that sysdep.h has been included before
	any system header files.
	* configure: Regenerate.
	* config.in: Regenerate.
	* unwind-ia64.h: Include config.h.
 2012-05-17 15:13:28 +00:00
DJ Delorie
21abe33a9b * rl78-decode.opc (rl78_decode_opcode): Add NOT1. 
* rl78-decode.c: Regenerate.

* config/rl78-parse.y (NOT1): Add.
 2012-01-25 01:40:11 +00:00
DJ Delorie
99c513f6ac [.] 
* configure.ac (rl78-*-*) New case.
	* configure: Regenerate.

[bfd]
	* Makefile.am (ALL_MACHINES): Add cpu-rl78.lo.
	(ALL_MACHINES_CFILES): Add cpu-rl78.c.
	(BFD32_BACKENDS): Add elf32-rl78.lo.
	(BFD32_BACKENDS_CFILES): Add elf32-rl78.c.
	(Makefile.in): Regenerate.
	* archures.c (bfd_architecture): Define bfd_arch_rl78.
	(bfd_archures_list): Add bfd_rl78_arch.
	* config.bfd: Add rl78-*-elf.
	* configure.in: Add bfd_elf32_rl78_vec.
	* reloc.c (bfd_reloc_code_type): Add BFD_RELOC_RL78_* relocations.
	* targets.c (bfd_target_vector): Add bfd_elf32_rl78_vec.
	* Makefile.in: Regenerate.
	* bfd-in2.h: Regenerate.
	* configure: Regenerate.
	* libbfd.h: Regenerate.
	* cpu-rl78.c: New file.
	* elf32-rl78.c: New file.

[binutils]
	* readelf.c: Include elf/rl78.h
	(guess_is_rela): Handle EM_RL78.
	(dump_relocations): Likewise.
	(get_machine_name): Likewise.
	(is_32bit_abs_reloc): Likewise.
	* NEWS: Mention addition of RL78 support.
	* MAINTAINERS: Add myself as RL78 port maintainer.

[gas]
	* Makefile.am (TARGET_CPU_CFILES): Add tc-rl78.c.
	(TARGET_CPU_HFILES): Add rc-rl78.h.
	(EXTRA_DIST): Add rl78-parse.c and rl78-parse.y.
	(rl78-parse.c, rl78-parse.h, rl78-parse.o, rl78-defs.h): New rules.
	* Makefile.in: Regenerate.
	* configure.in: Add rl78 case.
	* configure: Regenerate.
	* configure.tgt: Add rl78 case.
	* config/rl78-defs.h: New file.
	* config/rl78-parse.y: New file.
	* config/tc-rl78.c: New file.
	* config/tc-rl78.h: New file.
	* NEWS: Add Renesas RL78.

	* doc/Makefile.am (c-rl78.texi): New.
	* doc/Makefile.in: Likewise.
	* doc/all.texi: Enable it.
	* doc/as.texi: Add it.

[include]
	* dis-asm.h (print_insn_rl78): Declare.

[include/elf]
	* common.h (EM_RL78, EM_78K0R): New.
	* rl78.h: New.

[include/opcode]
	* rl78.h: New file.

[ld]
	* Makefile.am (ALL_EMULATION_SOURCES): Add eelf32rl78.c.
	(+eelf32rl78.c): New rule.
	* Makefile.in: Regenerate.
	* configure.tgt: Add rl78-*-* case.
	* emulparams/elf32rl78.sh: New file.
	* NEWS: Mention addition of Renesas RL78 support.

[opcodes]
	* Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
	rl78-dis.c.
	(MAINTAINERCLEANFILES): Add rl78-decode.c.
	(rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
	* Makefile.in: Regenerate.
	* configure.in: Add bfd_rl78_arch case.
	* configure: Regenerate.
	* disassemble.c: Define ARCH_rl78.
	(disassembler): Add ARCH_rl78 case.
	* rl78-decode.c: New file.
	* rl78-decode.opc: New file.
	* rl78-dis.c: New file.
 2011-11-02 03:09:11 +00:00