00716ab174
* config.in: Disable sanity check for kfreebsd.
2012-09-10 22:30:57 +00:00
6d2920c847
Regenerate binutils configure
...
bfd/
2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
binutils/
2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
etc/
2010-11-20 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
* Makefile.in (install-strip): New target.
gas/
2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
gold/
2012-09-09 Alan Modra <amodra@gmail.com>
* target.h (Target::gc_mark_symbol, do_gc_mark_symbol): New functions.
gprof/
2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
intl/
2010-06-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
PR bootstrap/44621
ld/
2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
libiberty/
2011-08-28 H.J. Lu <hongjiu.lu@intel.com>
* argv.c (dupargv): Replace malloc with xmalloc. Don't check
opcodes/
2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
* configure: Regenerated.
2012-09-10 17:00:44 +00:00
b3e14edafc
Add Intel Itanium Series 9500 support
...
bfd/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* cpu-ia64-opc.c (ins_cnt6a): New function.
(ext_cnt6a): Ditto.
(ins_strd5b): Ditto.
(ext_strd5b): Ditto.
(elf64_ia64_operands): Add new operand types.
gas/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* config/tc-ia64.c (reg_symbol): Add a new register.
(indirect_reg): Ditto.
(pseudo_func): Add new symbolic constants.
(operand_match): Add new operand types recognition.
(operand_insn): Add new register recognition.
(md_begin): Add new register definition.
(specify_resource): Add new register recognition.
gas/testsuite/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* gas/testsuite/gas/ia64/psn.d: New file.
* gas/testsuite/gas/ia64/psn.s: New file.
* gas/testsuite/gas/ia64/ia64.exp: Add new testcase.
* gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests.
* gas/testsuite/gas/ia64/opc-m.d: Ditto.
include/opcode/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64.h (ia64_opnd): Add new operand types.
opcodes/
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
* ia64-gen.c: Promote completer index type to longlong.
(irf_operand): Add new register recognition.
(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
(lookup_specifier): Add new resource recognition.
(insert_bit_table_ent): Relax abort condition according to the
changed completer index type.
(print_dis_table): Fix printf format for completer index.
* ia64-ic.tbl: Add a new instruction class.
* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
* ia64-opc.h: Define short names for new operand types.
* ia64-raw.tbl: Add new RAW resource for DAHR register.
* ia64-waw.tbl: Add new WAW resource for DAHR register.
* ia64-asmtab.c: Regenerate.
2012-09-04 13:52:06 +00:00
382c72e904
* ppc-opc.c (VXASHB_MASK): New define.
...
(powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
2012-08-29 22:34:04 +00:00
fb048c26f1
* ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
...
VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
(powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
vupklsh>: Use VXVA_MASK.
<vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
<mfvscr>: Use VXVAVB_MASK.
<mtvscr>: Use VXVDVA_MASK.
<vspltb>: Use VXUIMM4_MASK.
<vsplth>: Use VXUIMM3_MASK.
<vspltw>: Use VXUIMM2_MASK.
2012-08-28 16:41:07 +00:00
3c9017d250
* gas/config/tc-arm.c (ARM_ENC_TAB): Add sha1h and sha2op entries.
...
(do_sha1h): New function.
(do_sha1su1): Likewise.
(do_sha256su0): Likewise.
(insns): Add 2 operand SHA instructions.
* gas/testsuite/gas/arm/armv8-a+crypto.s: Update testcase.
* gas/testsuite/gas/arm/armv8-a+crypto.d: Likewise.
* opcodes/arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
2012-08-24 08:14:40 +00:00
48adcd8ed5
* gas/config/tc-arm.c (NEON_ENC_TAB): Add sha3op entry.
...
(do_crypto_3op_1): New function.
(do_sha1c): Likewise.
(do_sha1p): Likewise.
(do_sha1m): Likewise.
(do_sha1su0): Likewise.
(do_sha256h): Likewise.
(do_sha256h2): Likewise.
(do_sha256su1): Likewise.
(insns): Add SHA 3 operand instructions.
* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
* opcodes/arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
2012-08-24 08:14:04 +00:00
4f51b4bdbb
* gas/config/tc-arm.c (neon_type_mask): Add P64 type.
...
(type_chk_of_el_type): Handle P64 type.
(el_type_of_type_chk): Likewise.
(do_neon_vmull): Handle VMULL.P64.
* gas/testsuite/gas/arm/armv8-a+crypto.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
* opcodes/arm-dis.c (neon_opcodes): Handle VMULL.P64.
2012-08-24 08:13:24 +00:00
91ff78946d
* gas/config/tc-arm.c (NEON_ENC_TAB): Add aes entry.
...
(neon_type_mask): Add N_UNT.
(neon_check_type): Don't always decay typed to untyped sizes.
(do_crypto_2op_1): New function.
(do_aese): Likewise.
(do_aesd): Likewise.
(do_aesmc.8): Likewise.
(do_aesimc.8): Likewise.
(insns): Add AES instructions.
* gas/testsuite/gas/arm/armv8-a+crypto.d: New testcase.
* gas/testsuite/gas/arm/armv8-a+crypto.s: Likewise.
* opcodes/arm-dis.c (neon_opcodes): Add support for AES instructions.
2012-08-24 08:12:45 +00:00
c70a898785
* gas/config/tc-arm.c (el_type_type_check): Add handling for 16-bit
...
floating point types.
(do_neon_cvttb_2): New function.
(do_neon_cvttb_1): Likewise.
(do_neon_cvtb): Refactor to use do_neon_cvttb_1.
(do_neon_cvtt): Likewise.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
* gas/testsuite/gas/arm/half-prec-vfpv3.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add support for HP/DP
conversions.
2012-08-24 08:11:44 +00:00
30bdf75259
* gas/config/tc-arm.c (NEON_ENC_TAB): Add vrint entries.
...
(neon_cvt_mode): Add neon_cvt_mode_r.
(do_vrint_1): New function.
(do_vrint_x): Likewise.
(do_vrint_z): Likewise.
(do_vrint_r): Likewise.
(do_vrint_a): Likewise.
(do_vrint_n): Likewise.
(do_vrint_p): Likewise.
(do_vrint_m): Likewise.
(insns): Add VRINT instructions.
* gas/testsuite/gas/arm/armv8-a+fpv5.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+fpv5.s: Likewise.
* gas/testsuite/gas/arm/armv8-a+simdv3.d: Likewise.
* gas/testsuite/gas/arm/armv8-a+simdv3.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add VRINT.
(neon_opcodes): Likewise.
2012-08-24 08:11:13 +00:00
7e8e678496
* gas/config/tc-arm.c (NEON_ENC_TAB): Add vcvta entry.
...
(neon_cvt_mode): New enumeration.
(do_vfp_nsyn_cvt_fpv8): New function.
(do_neon_cvt_1): Add support for new conversions.
(do_neon_cvtr): Use neon_cvt_mode enumerator.
(do_neon_cvt): Likewise.
(do_neon_cvta): New function.
(do_neon_cvtn): Likewise.
(do_neon_cvtp): Likewise.
(do_neon_cvtm): Likewise.
(insns): Add new VCVT instructions.
* gas/testsuite/gas/arm/armv8-a+fp.d: Update testcase.
* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
* gas/testsuite/gas/arm/armv8-a+simd.d: Likewise.
* gas/testsuite/gas/arm/armv8-a+simd.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add support for new VCVT
variants.
(neon_opcodes): Likewise.
2012-08-24 08:09:50 +00:00
73924fbcf8
* gas/config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
...
(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
(vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
(do_maxnm): New function.
(insns): Add vmaxnm, vminnm entries.
* gas/testsuite/gas/testsuite/gas/armv8-a+fp.d: Update testcase.
* gas/testsuite/gas/testsuite/gas/armv8-a+fp.s: Likewise.
* gas/testsuite/gas/testsuite/gas/armv8-a+simd.d: New testcase.
* gas/testsuite/gas/testsuite/gas/armv8-a+simd.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
(neon_opcodes): Likewise.
2012-08-24 08:07:36 +00:00
33399f071c
* gas/config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
...
(NEON_ENC_FPV8_): New define.
(do_vfp_nsyn_fpv8): New function.
(do_vsel): Likewise.
(insns): Add VSEL instructions.
* gas/testsuite/gas/arm/armv8-a+fp.d: New testcase.
* gas/testsuite/gas/arm/armv8-a+fp.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add VSEL.
(print_insn_coprocessor): Add new %<>c bitfield format
specifier.
2012-08-24 08:06:36 +00:00
9eb6c0f132
* gas/config/tc-arm.c (do_rm_rn): New function.
...
(do_strlex): Likewise.
(do_t_strlex): Likewise.
(insns): Add support for LDRA/STRL instructions.
* gas/testsuite/gas/arm/armv8-a-bad.l: Update testcase.
* gas/testsuite/gas/arm/armv8-a-bad.s: Likewise.
* gas/testsuite/gas/arm/armv8-a.d: Likewise.
* gas/testsuite/gas/arm/armv8-a.s: Likewise.
* opcodes/arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
(thumb32_opcodes): Likewise.
(print_arm_insn): Add support for %<>T formatter.
2012-08-24 08:03:39 +00:00
8884b7208b
* gas/config/tc-arm.c (do_t_bkpt_hlt1): New function.
...
(do_t_hlt): New function.
(do_t_bkpt): Use do_t_bkpt_hlt1.
(insns): Add HLT.
* gas/testsuite/gas/arm/armv8-a-bad.l: Update for HLT.
* gas/testsuite/gas/arm/armv8-a-bad.s: Likewise.
* gas/testsuite/gas/arm/armv8-a.d: Likewise.
* gas/testsuite/gas/arm/armv8-a.s: Likewise.
* opcodes/arm-dis.c (arm_opcodes): Add HLT.
(thumb_opcodes): Likewise.
2012-08-24 08:02:51 +00:00
b79f7053dd
* gas/config/tc-arm.c (insns): Add DCPS instruction.
...
* gas/testsuite/gas/arm/armv8-a.d: Update.
* gas/testsuite/gas/arm/armv8-a.s: Likewise.
* opcodes/arm-dis.c (thumb32_opcodes): Add DCPS instruction.
2012-08-24 08:02:09 +00:00
53c4b28b4f
* gas/config/tc-arm.c (T16_32_TAB): Add _sevl.
...
(insns): Add SEVL.
* gas/testsuite/gas/arm/armv8-a.s: New testcase.
* gas/testsuite/gas/arm/armv8-a.d: Likewise.
* opcodes/arm-dis.c (arm_opcodes): Add SEVL.
(thumb_opcodes): Likewise.
(thumb32_opcodes): Likewise.
2012-08-24 08:01:18 +00:00
e797f7e0b2
* gas/config/tc-arm.c (asm_barrier_opt): Add arch field.
...
(mark_feature_used): New function.
(parse_barrier): Check specified option is valid for the
specified architecture.
(UL_BARRIER): New macro.
(barrier_opt_names): Update for new barrier options.
* gas/testsuite/gas/arm/armv8-a-barrier.s: New testcase.
* gas/testsuite/gas/arm/armv8-a-barrier-arm.d: Likewise.
* gas/testsuite/gas/arm/armv8-a-barrier-thumb.d: Likewise.
* opcodes/arm-dis.c (data_barrier_option): New function.
(print_insn_arm): Use data_barrier_option.
(print_insn_thumb32): Use data_barrier_option.
2012-08-24 08:00:20 +00:00
e2efe87d8a
* opcodes/arm-dis.c (COND_UNCOND): New constant.
...
(print_insn_coprocessor): Add support for %u format specifier.
(print_insn_neon): Likewise.
2012-08-24 07:59:05 +00:00
2c63854f55
Fix sparc opcode encoding for 4-arg crypto instructions.
...
include/opcode
* sparc.h (F3F4): New macro.
opcodes
* sparc-opc.c (4-argument crypto instructions): Fix encoding using
F3F4 macro.
gas/testsuite
* gas/sparc/crypto.d: Fix opcodes for 4-arg crypto instructions.
2012-08-21 23:00:36 +00:00
e67ed0e885
opcodes/ChangeLog
...
* ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
vabsduh, vabsduw, mviwsplt.
gas/testsuite/ChangeLog
* gas/ppc/e6500.d: Changed opcode for vabsdub, vabsduh, vabsduw,
mviwsplt.
2012-08-20 03:20:24 +00:00
7b458c12dc
Add AMD btver1 and btver2 support
...
gas/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* config/tc-i386.c (cpu_arch): Add CPU_BTVER1_FLAGS and
CPU_BTVER2_FLAGS.
(i386_align_code): Add case for PROCESSOR_BT.
* config/tc-i386.h (enum processor_type): Add PROCESSOR_BT.
* doc/c-i386.texi: Add -march={btver1, btver2} options.
gas/testsuite/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* gas/i386/i386.exp: Run btver1 and btver2 test cases.
* gas/i386/nops-1-btver1.d: New.
* gas/i386/nops-1-btver2.d: New.
* gas/i386/arch-10-btver1.d: New.
* gas/i386/arch-10-btver2.d: New.
* gas/i386/x86-64-nops-1-btver1.d: New.
* gas/i386/x86-64-nops-1-btver2.d: New.
* gas/i386/x86-64-arch-2-btver1.d: New.
* gas/i386/x86-64-arch-2-btver2.d: New.
opcodes/
2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
* i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
CPU_BTVER2_FLAGS.
* i386-opc.h: Update CpuPRFCHW comment.
* i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2012-08-17 17:12:36 +00:00
eb80cb8751
* po/vi.po: Updated Vietnamese translation.
...
* po/uk.po: New Ukranian translation.
* configure.in (ALL_LINGUAS): Add uk.
* configure: Regenerate.
2012-08-17 14:33:27 +00:00
8baf7b78b5
* ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
...
RBX for the third operand.
<"lswi">: Use RAX for second and NBI for the third operand.
2012-08-16 18:12:38 +00:00
3d557b4cce
* rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
...
operands, so that data addresses can be corrected when not
ES-overridden.
* rl78-decode.c: Regenerate.
* rl78-dis.c (print_insn_rl78): Make order of modifiers
irrelevent. When the 'e' specifier is used on an operand and no
ES prefix is provided, adjust address to make it absolute.
2012-08-15 22:37:56 +00:00
588925d065
opcodes/
...
* ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
gas/testsuite/
* gas/ppc/power4.s <lq, stq>: Add more tests.
* gas/ppc/power4.d: Likewise.
2012-08-15 21:25:21 +00:00
9f6a6cc022
opcodes/
...
* ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
gas/testsuite/
* gas/ppc/common.d ("nop", "xnop"): Add tests.
* gas/ppc/common.s: Likewise.
* gas/ppc/power7.d ("yield", "mdoio", "mdoom"): Add tests.
* gas/ppc/power7.s: Likewise.
2012-08-15 15:33:25 +00:00
fc8c4fd1b2
* mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
...
macros, use local variables for info struct member accesses,
update the type of the variable used to hold the instruction
word.
(print_insn_mips, print_mips16_insn_arg): Likewise.
(print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
local variables for info struct member accesses.
(print_insn_micromips): Add GET_OP_S local macro.
(_print_insn_mips): Update the type of the variable used to hold
the instruction word.
2012-08-14 22:00:05 +00:00
a06ea96464
Add support for 64-bit ARM architecture: AArch64
2012-08-13 14:52:54 +00:00
35d0a16941
include/opcode/
...
* mips.h (mips_opcode): Add the exclusions field.
(OPCODE_IS_MEMBER): Remove macro.
(cpu_is_member): New inline function.
(opcode_is_member): Likewise.
opcodes/
* micromips-opc.c (micromips_opcodes): Update comment.
* mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
instructions for IOCT as appropriate.
* mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
opcode_is_member.
* configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
the result of a check for the -Wno-missing-field-initializers
GCC option.
* Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
(mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
compilation.
(mips16-opc.lo): Likewise.
(micromips-opc.lo): Likewise.
* aclocal.m4: Regenerate.
* configure: Regenerate.
* Makefile.in: Regenerate.
gas/
* config/tc-mips.c (NO_ISA_COP, COP_INSN): Remove macros.
(is_opcode_valid): Remove coprocessor instruction exclusions.
Replace OPCODE_IS_MEMBER with opcode_is_member.
(is_opcode_valid_16): Replace OPCODE_IS_MEMBER with
opcode_is_member.
(macro): Remove coprocessor instruction exclusions.
2012-08-13 14:26:14 +00:00
5c5acbbddf
Enable FMA instructions for bdver2
...
gas/testsuite/
PR gas/14423
* gas/i386/arch-10-bdver2.d: New file.
* gas/i386/x86-64-arch-2-bdver2.d: Likewise.
* gas/i386/i386.exp: Run new test
opcodes/
2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
PR gas/14423
* i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
* i386-init.h: Regenerated.
2012-08-10 21:19:40 +00:00
3c892704a9
Updated Vietnamese translation.
2012-08-09 14:46:44 +00:00
d7189fa58e
gas/testsuite/
...
* gas/i386/prefetch.s: New file.
* gas/i386/prefetch.d: New file.
* gas/i386/prefetch-intel.d: New file.
* gas/i386/x86-64-prefetch.d: New file.
* gas/i386/x86-64-prefetch-intel.d: New file.
* gas/i386/i386.exp: Run them.
opcodes/
* i386-dis.c (reg_table): Fill out REG_0F0D table with
AMD-reserved cases as "prefetch".
(MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
(MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
(reg_table): Use those under REG_0F18.
(mod_table): Add those cases as "nop/reserved".
2012-08-07 18:22:04 +00:00
4c692bc7aa
There were several cases where the registers in the REX encoded range
...
got treated identically to the ones in the base range, due to not
paying attention to the fact that reg_entry's reg_num field doesn't
fully specify the register number (reg_flags also needs to be checked
for RegRex). This patch introduces and uses a new (inline) function to
obtain the full register number, and uses it to fix all those cases.
It additionally adds the missing operand checks for SVME instructions
(which match the monitor/mwait ones).
gas/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* config/tc-i386.c (register_number): New function.
(build_vex_prefix, process_immext, process_operands,
build_modrm_byte, i386_index_check): Use it.
gas/testsuite/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* gas/i386/x86-64-specific-reg.{s,l}: New.
* gas/i386/i386.exp: Run new test.
opcodes/
2012-08-07 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
2012-08-07 16:51:34 +00:00
de88229846
gas/testsuite/
...
* gas/i386/x86-64-stack.s: Add cases for push segment register.
* gas/i386/x86-64-stack.d: Updated.
* gas/i386/x86-64-stack-suffix.d: Updated.
* gas/i386/x86-64-stack-intel.d: Updated.
* gas/i386/ilp32/x86-64-stack.d: Updated.
* gas/i386/ilp32/x86-64-stack-suffix.d: Updated.
* gas/i386/ilp32/x86-64-stack-intel.d: Updated.
opcodes/
* i386-dis.c (print_insn): Print spaces between multiple excess
prefixes. Return actual number of excess prefixes consumed,
not always one.
* i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
2012-08-06 22:08:25 +00:00
7bb15c6f21
gas/testsuite/
...
* gas/i386/x86-64-stack.s: Add cases for push immediate.
* gas/testsuite/gas/i386/ilp32/x86-64-stack-intel.d: Updated.
* gas/testsuite/gas/i386/ilp32/x86-64-stack-suffix.d: Updated.
* gas/testsuite/gas/i386/ilp32/x86-64-stack.d: Updated.
* gas/testsuite/gas/i386/x86-64-stack-intel.d: Updated.
* gas/testsuite/gas/i386/x86-64-stack-suffix.d: Updated.
* gas/testsuite/gas/i386/x86-64-stack.d: Updated.
opcodes/
* i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
(putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
(intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
(OP_E_register): Likewise.
(OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
2012-08-06 20:19:34 +00:00
3843081d42
* configure.in: Formatting.
...
* configure: Regenerate.
2012-08-02 08:13:48 +00:00
488916061e
* h8300-dis.c: Fix printf arg warnings.
...
* i960-dis.c: Likewise.
* mips-dis.c: Likewise.
* pdp11-dis.c: Likewise.
* sh-dis.c: Likewise.
* v850-dis.c: Likewise.
* configure.in: Formatting.
* configure: Regenerate.
* rl78-decode.c: Regenerate.
* po/POTFILES.in: Regenerate.
2012-08-01 00:41:35 +00:00
03f66e8a8f
include/opcode/
...
* mips.h: Document microMIPS DSP ASE usage.
(MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
microMIPS DSP ASE support.
(MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
(MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
(MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
(MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
(MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
(MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
(MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
gas/
* config/tc-mips.c (macro_build) <'2'>: Handle microMIPS.
(macro) <M_BALIGN>: Update error handling.
(validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases.
<'7', '8', '0', '@', '^'>: Likewise.
(mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS.
<'9'>: Fix formatting.
<'0', '@'>: Handle microMIPS.
<'^'>: New case.
gas/testsuite/
* gas/mips/micromips@mips32-dsp.d: New.
* gas/mips/micromips@mips32-dspr2.d: New.
* gas/mips/mips32-dsp.d: Remove -mips32r2.
* gas/mips/mips32-dspr2.d: Likewise.
* gas/mips/mips.exp: (mips_create_arch): Use -mips64r2
for micromips. Use run_dump_test_arches to run dsp tests.
opcodes/
* micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
(DSP_VOLA): Likewise.
(D32, D33): Likewise.
(micromips_opcodes): Add DSP ASE instructions.
* micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
<'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
2012-07-31 21:38:54 +00:00
94948e646e
VMOVNTDQA was both misplaced and improperly tagged as being an AVX
...
instruction (instead of AVX2).
2012-07-31 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
instruction group. Mark as requiring AVX2.
* i386-tbl.h: Re-generate.
2012-07-31 07:38:42 +00:00
416cf80afb
2012-07-05 Sean Keys <skeys@ipdatasys.com>
...
* xgate-dis.c: Removed an IF statement that will
always be false due to overlapping operand masks.
* xgate-opc.c: Corrected 'com' opcode entry and
fixed spacing.
2012-07-30 21:49:06 +00:00
a6dc81d2ab
Updated translations
2012-07-30 08:43:46 +00:00
c4dd807e7b
bfd: update to AC_INIT
...
Move the package name/version from AM_INIT_AUTOMAKE to AC_INIT per recent
autotools guidelines. We use recent versions of both, so it shouldn't be
a problem.
This sets PACKAGE_xxx variables correctly, and makes the output of:
./configure --version
actually useful:
bfd configure 2.22.52
Changing the other dirs to use AC_INIT would require a bit of m4 trickery
that I don't feel like getting into, and they all use BFD_VERSION anyways,
so there isn't much point.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2012-07-27 16:30:57 +00:00
63d08c6844
Fix attributation of PR 13135 patch.
2012-07-26 14:05:38 +00:00
03edbe3bfb
2012-07-25 James Lemke <jwlemke@codesourcery.com>
...
* ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
2012-07-25 13:08:55 +00:00
d908c8af5a
PR binutils/13135
...
* arm-dis.c: Add necessary casts for printing integer values.
Use %s when printing string values.
* hppa-dis.c: Likewise.
* m68k-dis.c: Likewise.
* microblaze-dis.c: Likewise.
* mips-dis.c: Likewise.
* ppc-dis.c: Likewise.
* sparc-dis.c: Likewise.
* dis-asm.h (fprintf_ftype): Add ATTRIBUTE_FPTR_PRINTF_2.
2012-07-24 12:56:47 +00:00
ff688e1f8e
Use vex_len_table in xop_table
...
PR binutils/14355
* i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
(VEX_LEN_0FXOP_08_CD): Likewise.
(VEX_LEN_0FXOP_08_CE): Likewise.
(VEX_LEN_0FXOP_08_CF): Likewise.
(VEX_LEN_0FXOP_08_EC): Likewise.
(VEX_LEN_0FXOP_08_ED): Likewise.
(VEX_LEN_0FXOP_08_EE): Likewise.
(VEX_LEN_0FXOP_08_EF): Likewise.
(xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
vpcomub, vpcomuw, vpcomud, vpcomuq.
(vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
VEX_LEN_0FXOP_08_EF.
2012-07-19 13:41:03 +00:00
e2e1fcde62
Implement RDRSEED, ADX and PRFCHW instructions
...
gas/
* config/tc-i386.c: Add ADX, RDSEED and PRFCHW asm directives.
* doc/c-i386.texi: Document the new directives.
gas/testsuite/
* gas/i386/i386.exp: Run adx, rdseed and prefetchw tests.
* gas/i386/x86-64-arch-2.s: Use prefetchw as 3dnow and Prfchw tests.
* gas/i386/arch-10.s: Likewise.
* gas/i386/arch-10-1.l: Changed correspondingly.
* gas/i386/arch-10-2.l: Likewise.
* gas/i386/arch-10-3.l: Likewise.
* gas/i386/arch-10-4.l: Likewise.
* gas/i386/arch-10.d: Likewise.
* gas/i386/arch-10-lzcnt.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-arch-2-lzcnt.d: Likewise.
* gas/i386/ilp32/x86-64-arch-2.d: Likewise.
* gas/i386/arch-10-prefetchw.d: New file.
* gas/i386/x86-64-arch-2-prefetchw.d: Likewise.
* gas/i386/rdseed.s: Likewise.
* gas/i386/rdseed.d: Likewise.
* gas/i386/rdseed-intel.d: Likewise.
* gas/i386/adx.s: Likewise.
* gas/i386/adx.d: Likewise.
* gas/i386/adx-intel.d: Likewise.
* gas/i386/x86-64-rdseed.s: Likewise.
* gas/i386/x86-64-rdseed.d: Likewise.
* gas/i386/x86-64-rdseed-intel.d: Likewise.
* gas/i386/x86-64-adx.s: Likewise.
* gas/i386/x86-64-adx.d: Likewise.
* gas/i386/x86-64-adx-intel.d: Likewise.
opcodes/
* i386-dis.c (PREFIX_0F38F6): New.
(prefix_table): Add adcx, adox instructions.
(three_byte_table): Use PREFIX_0F38F6.
(mod_table): Add rdseed instruction.
* i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
(cpu_flags): Likewise.
* i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
(i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
* i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
prefetchw.
* i386-tbl.h: Regenerate.
* i386-init.h: Likewise.
2012-07-16 12:58:29 +00:00
f4263ca2cd
Typo fix.
2012-07-05 08:28:22 +00:00
Alan Modra