Commit Graph

539 Commits

Author SHA1 Message Date
Aldy Hernandez ced05688d4 2002-11-07 Aldy Hernandez <aldyh@redhat.com>
* ppc-opc.c (EVUIMM_4): Change bit size to 32.
	(EVUIMM_2): Same.
	(EVUIMM_8): Same.
2002-11-08 00:46:21 +00:00
Aldy Hernandez 95e172a508 2002-11-07 Aldy Hernandez <aldyh@redhat.com>
* ppc-opc.c (EVUIMM_4): Change bit size to 32.
	(EVUIMM_2): Same.
2002-11-07 23:43:50 +00:00
Nick Clifton bde78a07b9 Convert ia64-gen to use getopt(). Add standard GNU options plus --srcdir.
Convert Makefile.am to pass --srcdir to ia64-gen.  Fix compile time warnings.
2002-11-07 14:33:48 +00:00
Aldy Hernandez fe58797755 2002-11-06 Aldy Hernandez <aldyh@redhat.com>
* opcodes/ppc-opc.c: Change RD to RS for evmerge*.
2002-11-07 00:54:09 +00:00
Nick Clifton d3c866d1d8 Add conditional/unconditional branch classification. 2002-10-23 15:45:49 +00:00
Stephane Carrez ac8c616a59 * m68hc11-dis.c (print_insn): Treat bitmask and branch operands
at the end.
2002-10-13 09:01:54 +00:00
Richard Sandiford 9752cf1b67 [include/opcode/]
* mips.h: Update comment for new opcodes.
	(OP_MASK_VECBYTE, OP_SH_VECBYTE): New.
	(OP_MASK_VECALIGN, OP_SH_VECALIGN): New.
	(INSN_4111, INSN_4120, INSN_5400, INSN_5500): New.
	(CPU_VR4120, CPU_VR5400, CPU_VR5500): New.
	(OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags.
	Don't match CPU_R4111 with INSN_4100.

[opcodes/]
	* mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'.
	(mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400
	and bfd_mach_mips5500.
	* mips-opc.c (V1): Include INSN_4111 and INSN_4120.
	(N411, N412, N5, N54, N55): New convenience defines.
	(mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes.
	Change dmadd16 and madd16 from V1 to N411.
2002-09-30 11:58:10 +00:00
Thiemo Seufer 3396de367a /gas/ChangeLog
* config/tc-mips.c (CPU_HAS_MIPS16): Add mips-lsi-elf as MIPS16
	capable configuration.
	(macro_build): Check for MIPS16 capability, not for actual MIPS16 code
	generation.
	(mips_ip): Likewise.

	/gas/testsuite/ChangeLog
	* gas/mips/mips-jalx.d: New file, check jalx assembly.
	* gas/mips/mips-jalx.s: Likewise.
	* gas/mips/mips-no-jalx.l: Likewise.
	* gas/mips/mips-no-jalx.s: Likewise.
	* gas/mips/mips16-jalx.d: Likewise.
	* gas/mips/mips16-jalx.s: Likewise.
	* gas/mips/mips.exp: Add new tests.

	/opcodes/ChangeLog:
	* mips-dis.c (print_insn_mips): Always allow disassembly of
	32-bit jalx opcode.
2002-09-26 09:56:35 +00:00
Nick Clifton 1a40396432 Updated German translation. 2002-09-24 13:00:33 +00:00
Alan Modra 2d2550d688 * Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
2002-09-21 10:49:05 +00:00
Nick Clifton 0ec499f72c Allow CRFS and CRFD operands to accept CR register names 2002-09-20 15:44:23 +00:00
Alan Modra 4415b5c296 * tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED.
Convert functions to K&R format.
2002-09-17 08:34:17 +00:00
Nick Clifton dde1b13223 Fix Book-E opcodes 2002-09-13 09:07:49 +00:00
Alan Modra 9ec878e367 * ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC. 2002-09-12 03:58:37 +00:00
Nick Clifton e09f439535 Update translations 2002-09-11 13:52:17 +00:00
Nick Clifton 341026c1c1 Do not insert non-BookE32 instructions into the hash table if the target cpu
is the BookE32. (case 107575)
2002-09-04 12:37:30 +00:00
Nick Clifton 07dd56a969 Have objdump's --help switch document PPC -M options. 2002-09-04 10:08:08 +00:00
Nick Clifton 2e32aab953 The BookE implementations of the TLBWE and TLBRE instructions do not take any
arguments.
2002-09-04 09:59:48 +00:00
Nick Clifton bf5be08227 Remove redundant references to V850EA architecture. 2002-09-02 11:44:39 +00:00
Alan Modra d943fe33c6 * arc-opc.c: Include bfd.h.
(arc_get_opcode_mach): Subtract off base bfd_mach value.
2002-09-02 06:00:05 +00:00
Alan Modra 53f32ea5c6 * v850-dis.c (disassemble): Remove bfd_mach_v850ea case.
* mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants.
2002-08-30 08:28:08 +00:00
Nick Clifton 026df7c5e6 Add TMS320C4x support 2002-08-28 10:38:51 +00:00
Nick Clifton 1489984027 opcodes: Fix definition of "in rd,imm16" opcode.
gas: Adjust ptr variable also in "case 0" case.
2002-08-22 19:22:35 +00:00
Elena Zannoni 2397604975 2002-08-19 Elena Zannoni <ezannoni@redhat.com>
From  matthew green  <mrg@redhat.com>

        * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and
        `-mefs'. Turn off AltiVec for E500 and efs.
        (print_insn_powerpc): Don't print an AltiVec instruction if the
        dialect is not efs.

        * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2,
        insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions
        for extracting pmrn/evld/evstd/etc operands.
        (CRB, CRFD, CRFS, DC, RD): New instruction fields.
        (CT): Make this equal to RD + 1.
        (PMRN): New operand.
        (RA): Update.
        (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands.
        (WS): Update.
        (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL.
        (ISEL, ISEL_MASK): New instruction form and mask for ISEL.
        (XISEL, XISEL_MASK): New instruction form and mask for ISEL.
        (CTX, CTX_MASK): New instruction form and mask for context cache
        instructions.
        (UCTX, UCTX_MASK): New instruction form and mask for user context
        cache instructions.
        (XC, XC_MASK, XUC, XUC_MASK): New instruction forms.
        (CLASSIC): New define.
        (PPCESPE): New define.
        (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New
        defines for integer select, cache control, branch
        locking, power management, cache locking and machine check
        APU instructions, respectively.
        (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul,
        efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt,
        efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf,
        efsctui, efsctsi, efsctsiz, efsctuf, efsctsf,
        evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb,
        evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor,
        evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi,
        evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi,
        evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts,
        evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh,
        evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx,
        evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat,
        evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx,
        evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe,
        evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox,
        evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv,
        evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq,
        evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui,
        evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg,
        evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq,
        evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf,
        evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf,
        evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi,
        evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi,
        evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw,
        evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw,
        evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw,
        evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw,
        evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw,
        evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa,
        evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian,
        evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf,
        evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa,
        evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan,
        evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa,
        evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian,
        evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi,
        evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi,
        evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw,
        evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw,
        evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa,
        evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia,
        evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan,
        evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw,
        evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw,
        evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex
        instructions.
        (rfmci): New machine check APU instruction.
        (isel): New integer select APU instructino.
        (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls,
        dcbtstlse, dcblc, dcblce): New cache control APU instructions.
        (mtspefscr, mfspefscr): New instructions.
        (mfpmr, mtpmr): New performance monitor APU instructions.
        (savecontext): New context cache APU instructions.
        (bblels, bbelr): New branch locking APU instructions.
        (bblels, bbelr): New instructions.
        (mftbl, mftbu, mftb): Set as CLASSIC instructions.  Add BOOKE alias.
2002-08-19 20:59:10 +00:00
Stephane Carrez 7eccd7f6f1 * m68hc11-opc.c: Update call operand to accept the page definition.
Identify instructions that are branches and calls to generate a
	RL_JUMP relocation.
2002-08-13 19:09:01 +00:00
Stephane Carrez f07534f64e * m68hc11-dis.c (print_insn): Take into account 68HC12 memory
banks and fix disassembling of call instruction.
	(print_indexed_operand): New param to tell whether
	it was an indirect addressing operand (for disassembling call).
2002-08-13 19:01:25 +00:00
Nick Clifton 2b692c5912 Updated Swedish translation 2002-08-09 15:07:57 +00:00
Maciej W. Rozycki 0c11417f42 * config/tc-mips.c (macro): Handle a register plus a 16-bit
immediate offset in "dla" and "la" expansions.
* gas/mips/empic.d: Treat "addiu" and "daddiu" as equivalent when
$0 is source.
* mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as
aliases to "daddiu" and "addiu".
2002-08-09 11:07:24 +00:00
Nick Clifton 83e1617e06 Updated Translations 2002-07-30 15:53:18 +00:00
Nick Clifton 219576a4db New translations 2002-07-25 10:31:28 +00:00
Nick Clifton ff3063f557 Update Spanish and Swedish translations 2002-07-24 09:34:08 +00:00
Alan Modra 8c3bb577a6 * Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
2002-07-23 12:42:32 +00:00
Nick Clifton 2c71db8993 oops - omitted from previous delta 2002-07-23 09:59:47 +00:00
Nick Clifton 0461a601af update translations. 2002-07-23 09:58:05 +00:00
Nick Clifton a40cbfa3c9 Add IP2k GAS and OPCODES support. 2002-07-19 07:52:40 +00:00
H.J. Lu ae66e5d720 2002-07-17 David Mosberger <davidm@hpl.hp.com>
* ia64-opc-b.c (bWhc): New macro.
	(mWhc): Ditto.
	(OpPaWhcD): Ditto.
	(ia64_opcodes_b): Correct patterns for indirect call
	instructions to use 3-bit "wh" field.
	* ia64-asmtab.c: Regnerate.
2002-07-17 07:27:40 +00:00
Thiemo Seufer aec421e08b * config/tc-mips.c (macro_build): Handle MIPS16 insns.
(mips_ip): Likewise.
	* mips.h (INSN_MIPS16): New define.
	* mips-dis.c (mips_isa_type): Add MIPS16 insn handling.
	* mips-opc.c (I16): New define.
	(mips_builtin_opcodes): Make jalx an I16 insn.
2002-07-09 14:21:40 +00:00
Dave Brolley fd3c93d5a7 2002-06-18 Dave Brolley <brolley@redhat.com>
* po/POTFILES.in: Add frv-*.[ch].
	* disassemble.c (ARCH_frv): New macro.
	(disassembler): Handle bfd_arch_frv.
	* configure.in: Support frv_bfd_arch.
	* Makefile.am (HFILES): Add frv-*.h.
	(CFILES): Add frv-*.c
	(ALL_MACHINES): Add frv-*.lo.
	(CLEANFILES): Add stamp-frv.
	(FRV_DEPS): New variable.
	(stamp-frv): New target.
	(frv-asm.lo): New target.
	(frv-desc.lo): New target.
	(frv-dis.lo): New target.
	(frv-ibld.lo): New target.
	(frv-opc.lo): New target.
	(frv-*.[ch]): New files.
2002-06-18 21:21:05 +00:00
Ben Elliston bc98a6310f * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen.
* Makefile.in: Regenerate.
2002-06-18 17:43:07 +00:00
Alan Modra 56da5fedc7 * a29k-dis.c: Replace CONST with const.
* h8300-dis.c: Likewise.
	* m68k-dis.c: Likewise.
	* or32-dis.c: Likewise.
	* sparc-dis.c: Likewise.
2002-06-08 07:29:27 +00:00
Jason Thorpe 5b0e55b627 bfd:
* Makefile.am (BFD32_BACKENDS): Add elf32-sh64-nbsd.lo.
(BFD32_BACKENDS_CFILES): Add elf32-sh64-nbsd.c.
(BFD64_BACKENDS): Add elf64-sh64-nbsd.lo.
(BFD64_BACKENDS_CFILES): Add elf64-sh64-nbsd.c.
(elf32-sh64-nbsd.lo, elf64-sh64-nbsd.lo): New rules.
* Makefile.in: Regenerate.
* config.bfd (sh5le-*-netbsd*, sh5-*-netbsd*, sh64le-*-netbsd*)
(sh64-*-netbsd*): New targets.
* configure.in: Add bfd_elf32_sh64nbsd_vec, bfd_elf32_sh64lnbsd_vec,
bfd_elf64_sh64nbsd_vec, and bfd_elf64_sh64lnbsd_vec.
* configure: Regenerate.
* elf32-sh64-nbsd.c: New file.
* elf64-sh64-nbsd.c: New file.
* targets.c: Add extern decls for bfd_elf32_sh64nbsd_vec,
bfd_elf32_sh64lnbsd_vec, bfd_elf64_sh64nbsd_vec, and
bfd_elf64_sh64lnbsd_vec.

gas:
* configure.in (sh5*): Set cpu_type to sh64 and endian to big.
(sh5le*, sh64le*): Set cpu_type to sh64 and endian to little.
(sh5*-*-netbsd*, sh64*-*-netbsd*): New targets.
* configure: Regenerate.
* config/tc-sh64.c (sh64_target_format): Add support for NetBSD
environment.

ld:
* Makefile.am (ALL_EMULATIONS): Add eshelf32_nbsd.o,
eshlelf32_nbsd.o, eshelf64_nbsd.o, and eshlelf64_nbsd.o.
(eshelf32_nbsd.c, eshelf64_nbsd.c, eshlelf32_nbsd.c)
(eshlelf64_nbsd.c): New rules.
* Makefile.in: Regenerate.
* configure.tgt (sh5le-*-netbsd*, sh5-*-netbsd*, sh64le-*-netbsd*)
(sh64-*-netbsd*): New targets.
* emulparams/shelf32_nbsd.sh: New file.
* emulparams/shelf64_nbsd.sh: New file.
* emulparams/shlelf32_nbsd.sh: New file.
* emulparams/shlelf64_nbsd.sh: New file.

opcodes:
* configure.in: Add "sh5*-*" to list of targets which include
sh64 support.
* configure: Regenerate.
2002-06-04 02:57:44 +00:00
Chris Demetriou 154bce22d5 2002-05-31 Chris G. Demetriou <cgd@broadcom.com>
* mips-opc.c: Clean up a few whitespace issues, and sort a
        few entries understanding that 'x' follows 'w' in the alphabet.
2002-05-31 20:46:07 +00:00
Chris Demetriou 107c6e1ad8 [ opcodes/ChangeLog ]
2002-05-31  Chris G. Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

        * mips-opc.c: Add support for SB-1 MDMX subset and extensions.

[ gas/testsuite/ChangeLog ]
2002-05-31  Chris G. Demetriou  <cgd@broadcom.com>

        * gas/mips/sb1-ext-mdmx.s: New file.
        * gas/mips/sb1-ext-mdmx.d: Likewise.
        * gas/mips/mips.exp: Run new "sb1-ext-mdmx" test.
2002-05-31 18:27:03 +00:00
Alan Modra 194b521088 * Makefile.am: Run "make dep-am".
* Makefile.in: Regenerate.
	* po/POTFILES.in: Regenerate.
2002-05-31 04:27:37 +00:00
Chris Demetriou deec17343c [ gas/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* config/tc-mips.c (mips_set_options): New "ase_mdmx" member.
	(mips_opts): Initialize "ase_mdmx" member.
	(file_ase_mdmx): New variable.
	(CPU_HAS_MDMX): New macro.
	(md_begin): Initialize mips_opts.ase_mdmx and file_ase_mdmx
	based on command line options and configuration defaults.
	(macro_build): Note in comment that use of MDMX in macros is
	not currently allowed.
	(validate_mips_insn): Add support for the "O", "Q", "X", "Y", and
	"Z" MDMX operand types.
	(mips_ip): Accept MDMX instructions if mips_opts.ase_mdmx is set,
	and add support for the "O", "Q", "X", "Y", and "Z" MDMX operand
	types.
	(OPTION_MDMX, OPTION_NO_MDMX, md_longopts, md_parse_option):
	Add support for "-mdmx" and "-no-mdmx" options.
	(OPTION_ELF_BASE): Move to accomodate new options.
	(s_mipsset): Support ".set mdmx" and ".set nomdmx".
	(mips_elf_final_processing): Set MDMX ASE ELF header flag if
	file_ase_mdmx was set.
	* doc/as.texinfo: Document -mdmx and -no-mdmx options.
	* doc/c-mips.texi: Likewise, and document ".set mdmx" and ".set
	nomdmx" directives.

[ gas/testsuite/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>

	* gas/mips/mips64-mdmx.s: New file.
	* gas/mips/mips64-mdmx.d: Likewise.
	* gas/mips/mips.exp: Run new "mips64-mdmx" test.

[ include/opcode/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>

	* mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL)
	(MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH)
	(MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC)
	(INSN_MDMX): New constants, for MDMX support.
	(opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX.

[ opcodes/ChangeLog ]
2002-05-30  Chris G. Demetriou  <cgd@broadcom.com>
            Ed Satterthwaite  <ehs@broadcom.com>

	* mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y',
	and 'Z' formats, for MDMX.
        (mips_isa_type): Add MDMX instructions to the ISA
	bit mask for bfd_mach_mipsisa64.
	* mips-opc.c: Add support for MDMX instructions.
	(MX): New definition.

	* mips-dis.c: Update copyright years to include 2002.
2002-05-31 01:17:18 +00:00
Tom Rix c20129930b Fix for invalid conflict warning. 2002-05-30 15:25:37 +00:00
Nick Clifton d172d4ba03 Add DLX target 2002-05-28 14:08:47 +00:00
Alan Modra 19f33eeef5 * Makefile.am (sh-dis.lo): Don't put make commands in deps.
* Makefile.in: Regenerate.
	* arc-dis.c: Use #include "" instead of <> for local header files.
	* m68k-dis.c: Likewise.
2002-05-25 12:55:19 +00:00
Nick Clifton baf0cc5e96 Fix handling of BLX instruction to conform to Operations definition in the
ARM ARM.
2002-05-23 12:48:23 +00:00
Joern Rennecke 9ccc8931b8 * Makefile.am (sh-dis.lo): Compile with @archdefs@.
* Makefile.in: regenerate.
2002-05-22 19:18:16 +00:00