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87192c630a
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1054 Commits

Author SHA1 Message Date
Andrew Cagney
87192c630a * simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. Sign 
extend bit 44 all constants.
(OP_4201): Replace GCC specific 0x..LL with SIGNED64 macro.
 1997-11-10 22:40:14 +00:00
Andrew Cagney
51624b4bf6 Test rachi instruction. 1997-11-10 08:27:15 +00:00
Andrew Cagney
8cb060b6b0 * callback.c (os_poll_quit): Replace _WIN32 with _MSC_VER. 1997-11-10 02:08:50 +00:00
Andrew Cagney
95469cebdd Replace global IPC with function argument cia or current instruction 
address.
Pass cia into calls to sim_engine_stop so that breakpoints et.al. work.
 1997-11-06 14:24:57 +00:00
Andrew Cagney
549bf95051 Fix computation of sim_events_time when sim_events_slip is loosing it. 1997-11-06 14:14:33 +00:00
Andrew Cagney
7ce8b9178c IGEN likes to cache the current instruction address (CIA). Change the 
MIPS simulator so that correctly writes the value of CIA back int PC
(the global previously used) when the simulation halts.
Fix implementation of DELAY_SLOT and NULLIFY_NEXT_INSTRUCTION macros.
 1997-11-06 09:16:16 +00:00
Andrew Cagney
864519b9fd Allow separate single character and long options. 
Avoid overflow of options buffer.
Provide examples of sim-options use.
 1997-11-06 05:00:09 +00:00
Andrew Cagney
44b8585a3d Add option --enable-sim-igen to mips configuration. Allows user to 
attempt a build of an older MIPS simulator using igen.
 1997-11-05 09:43:34 +00:00
Andrew Cagney
63be8febf7 Rewrite the MIPS simulator's memory model so that it uses the generic 
common/sim-core.

Add support for 3, 5, 6, 7 byte transfers to sim core.
 1997-11-05 08:17:26 +00:00
Andrew Cagney
22de994d0e Delete -l and -n options, didn't do anything. 
Rename option trace to dinero-trace & dinero-file - -t clashed with
common options.
Enable common trace options.
 1997-11-05 01:08:12 +00:00
Andrew Cagney
525d929e49 Rewrite sim_monitor (implements read, write, open, et.al. system 
calls) and sim_open so that they uses the virtual memory data transfer
functions sim_read & sim_write.  This eliminates all code (other than
in load_memory & store_memory) that makes assumptions about the
implementation of the underlying memory model.
 1997-11-05 00:08:14 +00:00
Andrew Cagney
a26ecda4ec * sim-endian.h (U16_8): Implement 
* sim-endian.c (sim_endian_split_16, sim_endian_join_16): New functions
* sim-endian.h (VL8_16, VH8_16): Implement.
* sim-memopt.c (memory_option_handler): Typecast 64bit value to long in printf.
  (memory_option_handler): Only zalloc modulo bytes when non-zero.
  (memory_option_handler): Skip comma in alias address list
 1997-11-04 23:59:41 +00:00
Brendan Kehoe
3b5bd034f5 * gen-idecode.c (print_jump_until_stop_body): Use `#if 0' instead of 
`#ifdef 0' around this.
 1997-11-04 17:36:37 +00:00
Michael Meissner
5aa52e3d26 do not assume NULL is an integer constant 1997-11-04 13:19:49 +00:00
Gavin Romig-Koch
0425cfb3af Correct r5900 sanitization. 1997-11-04 05:50:22 +00:00
Andrew Cagney
fcc86d82f7 Make memory regions layered (just like existing device regions) so 
that overlapping regions can be defined.
Allow the layer (level) of a memory region to be specified as part of
an address parameter to memory options.
Update simulators.
 1997-10-31 08:49:10 +00:00
Nick Clifton
d3e9ca1a88 Patches to support generating an executing environment. 
Patches from Tony Thompson at ARM:  athompso@arm.com
 1997-10-30 21:52:16 +00:00
Doug Evans
d048b52dbb * sim-core.h (sim_core_write_8): Define. 1997-10-30 21:45:12 +00:00
Gavin Romig-Koch
6205f37913 * gencode.c: Add tx49 configury and insns. 
* configure.in: Add tx49 configury.
	* configure: Update.
 1997-10-29 19:42:49 +00:00
Andrew Cagney
01b9cd49ca common/sim-bits.h: Document ROTn macro. 
igen/{igen.c,ld-insns.h}: Document mnemonic string formats.
mips/Makefile.in: Add dependencies for files included by mips.igen
mips/vr5400.igen: checkpoint vr5400 instructions.
 1997-10-29 04:02:30 +00:00
Andrew Cagney
89d0973831 Add support for 16 byte quantities to sim-endian macro H2T. 
Add model-filter field to option, include, model anf function igen records
 1997-10-28 07:10:36 +00:00
Andrew Cagney
a86809d323 Implement sim_core_{read,write}_word using sim_core_{read,write}_<N>. 1997-10-28 02:13:09 +00:00
Doug Evans
084219a513 * sem-ops.h (U{DIV,MOD}[BHSD]I): Use unsigned division. 1997-10-27 20:45:56 +00:00
Doug Evans
c3e3e4ad2f * sim-endian.h: Disable 16 byte support. 
So things will build.
 1997-10-27 19:47:24 +00:00
Doug Evans
374b95c1b0 * sim-n-endian.h: Add TAGS entrys for 16 byte versions. 1997-10-27 19:25:59 +00:00
Doug Evans
2fc2f8d8a4 Fix typo. 1997-10-27 19:25:05 +00:00
Andrew Cagney
16bd5d6e52 Separate r5900 specifoc and mips16 instructions. 
Add support for this to configure (vr5400 target only)
 1997-10-27 07:55:24 +00:00
Andrew Cagney
90ad43b2de Add mips64vr5400 to configuration list 
Mark mipsIV instructions as being implemented by the vr5400.
Sanitize.
 1997-10-27 06:42:13 +00:00
Andrew Cagney
e2880fadf3 Add include-file support to igen. 1997-10-27 06:30:35 +00:00
Andrew Cagney
f45dd42b32 Add 128 bit transfers to sim core. 1997-10-27 03:00:12 +00:00
Gavin Romig-Koch
635ae9cb7c * sim/mips/gencode.c (build_instruction): Follow sim_write's lead in using 
BigEndianMem instead of !ByteSwapMem.
 1997-10-25 20:53:46 +00:00
Andrew Cagney
b5da31ac7c Correct name of file given in ChangeLog for change: Pass lma_p and 
sim_write args to sim_load_file.
 1997-10-25 05:04:25 +00:00
Andrew Cagney
122edc03de Add basic igen configuration to autoconf. Disable. 1997-10-24 07:54:21 +00:00
Andrew Cagney
dad6f1f326 Add function to fetch 32bit instructions 
When address translation of insn fetch fails raise exception immediatly.
Use address_word as type of all address variables (instead of unsigned64),
the former is configured as either 32 or 64 bit type.
Always compile fpu code (no #if has fpu)
 1997-10-24 06:43:51 +00:00
Andrew Cagney
49a7683337 Checkpoint IGEN version of mips sim 1997-10-24 06:38:44 +00:00
Andrew Cagney
4a203fbae2 Add function sim_events_slip() 
Clear work_pending flag as part of processing any pending work.
 1997-10-24 05:53:01 +00:00
Andrew Cagney
1315b4cb60 Address MSC compiler issues in d10v_sim.h 1997-10-24 00:52:23 +00:00
Andrew Cagney
9e03a68f13 Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file(). 
Update all simulators.
Clarify behavour of sim_load in remote-sim.h
 1997-10-22 05:26:27 +00:00
Doug Evans
2328ef1c98 * nrun.c (main): Exit if bfd_openr fails. 
Call bfd_check_format after bfd_openr.
 1997-10-22 02:12:41 +00:00
Doug Evans
897a1d7863 * nrun.c (main): Remove useless test of name != NULL. 1997-10-22 01:38:49 +00:00
Jeff Law
f4ab2b2fdc * simops.c: Correctly handle register restores for "ret" and "retf" 
instructions.
pr13306 related stuff.
 1997-10-21 16:07:53 +00:00
Andrew Cagney
92ad193bb0 Use SIM*_OVERFLOW_RESULT defined in sim-alu.h 1997-10-21 07:57:33 +00:00
Andrew Cagney
b7432f0f27 Pacify GCC -Wall 1997-10-21 07:41:46 +00:00
Andrew Cagney
aa324b9b1e Output pc profile statistics once gathered. 1997-10-21 07:40:00 +00:00
Andrew Cagney
e2f8ffb736 Delete profile support from MIPS simulator, use sim/common/sim-profile 
module instead.
Generate a "gmon.out" (gprof) when profiling the target PC.
Add target PC profiling option --profile-pc-granularity (bucket size)
 1997-10-21 03:41:21 +00:00
Andrew Cagney
293a0876f8 Have single bit macros return an unsigned result. Avoids risk (and 
need) of sign extending results.
 1997-10-20 07:27:55 +00:00
Andrew Cagney
fb5a2a3e39 Make mips registers of type unsigned_word. 
Ensure all references to MIPS registers use same type.
 1997-10-20 06:28:53 +00:00
Andrew Cagney
0a0ecb2120 Add 8 bit arithmetic to sim-alu. 
Fix flags (Carry, oVerflow) for negate and subtract.
Add ALU*_RESULT macros for accessing final result of ALU op.
 1997-10-20 02:03:06 +00:00
Andrew Cagney
afb1dbe851 Preliminary tests for sim-alu module. 1997-10-17 03:57:53 +00:00
Andrew Cagney
ea985d2472 Move register definitions and macros out of interp.c and into sim-main.h 1997-10-16 03:50:48 +00:00