OpenE2K/binutils-gdb
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471 Commits

Author SHA1 Message Date
Jeff Law
374cb3020b * mn10300-opc.c (mn10300_opcodes): Add "break" instruction. 
For gdb.
 1996-12-16 22:28:24 +00:00
Jeff Law
d21f1eae7d * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)". 1996-12-16 20:05:07 +00:00
Ian Lance Taylor
39e5bea281 * mips-dis.c (print_mips16_insn_arg): The base address of a PC 
relative load or add now depends upon whether the instruction is
	in a delay slot.
 1996-12-15 03:37:08 +00:00
Jeff Law
c6b62ad1d7 * mn10200-dis.c: Finish writing disassembler. 
* mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
        Fix mask for "jmp (an)".
mn10200 disassembler works!
 1996-12-12 08:09:27 +00:00
Jeff Law
77955104ba * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently 
handle endianness issues for mn10300.
 1996-12-11 17:34:15 +00:00
Jeff Law
532700fc31 * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)". 
Yoshihiro Adachi sez the manual was wrong for this insn.
 1996-12-11 16:29:02 +00:00
Jeff Law
7bfc95d917 * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2 
instruction.  Fix opcode field for "movb (imm24),dn".
Stuff found by the testsuite.
 1996-12-10 20:34:14 +00:00
Jeff Law
0888b4a38a * mn10200-opc.c (mn10200_operands): Fix insertion position 
for DI operand.
Found by gas testsuite.
 1996-12-10 19:13:07 +00:00
Jeff Law
781766e7e1 * mn10200-opc.c: Create mn10200 opcode table. 
* mn10200-dis.c: Flesh out mn10200 disassembler.  Not ready,
        but moving along nicely.
Checkpointing today's mn10200 work.
 1996-12-09 23:48:15 +00:00
Peter Schauer
b65415a446 * Makefile.in (ALL_MACHINES): Add mips16-opc.o. 1996-12-08 12:35:28 +00:00
J.T. Conklin
6827a1c758 * m68k-opc.c (m68k_opcodes): Revert change to use < and > 
specifiers for fmovem* instructions.
 1996-12-07 00:54:51 +00:00
Jeff Law
4db788a664 * mn10300-dis.c (disassemble): Remove '$' register prefixing. 1996-12-06 22:40:31 +00:00
Ian Lance Taylor
34212ec3f6 * mips16-opc.c: Change opcode for entry/exit to avoid conflicting 
with dsrl.
 1996-12-06 22:35:01 +00:00
Jeff Law
8329699005 * mn10300-opc.c: Add some comments explaining the various 
operands and such.

        * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
 1996-12-06 22:04:12 +00:00
J.T. Conklin
e72d5a50f9 * m68k-dis.c (print_insn_arg): Handle new < and > operand 
specifiers.
* m68k-opc.c (m68k_opcodes): Simplify table by using < and >
operand specifiers in fmovm* instructions.
 1996-12-05 20:12:47 +00:00
Ian Lance Taylor
70eb6bdd65 * ppc-opc.c (insert_li): Give an error if the offset has the two 
least significant bits set.
PR 11201.
 1996-12-04 19:53:09 +00:00
Jeff Law
069279b34a * mn10300-dis.c (disasemble): Finish conversion to '$' as 
register prefix.
Fixes improper disassembly of movm instructions.
 1996-11-26 23:04:02 +00:00
Ian Lance Taylor
0e809bba05 * configure: Rebuild with autoconf 2.12. 1996-11-26 21:59:23 +00:00
Jeff Law
23b01150f5 * mn10300-opc.c (mn10300_opcodes): Fix mask field for 
mov am,(imm32,sp).
Found during initial simulator work.
 1996-11-26 20:28:34 +00:00
Ian Lance Taylor
8d67dc3077 Add support for mips16 (16 bit MIPS implementation): 
* mips16-opc.c: New file.
	* mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
	(mips16_reg_names): New static array.
	(print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
	after seeing a 16 bit symbol.
	(print_insn_little_mips): Likewise.
	(print_insn_mips16): New static function.
	(print_mips16_insn_arg): New static function.
	* mips-opc.c: Add jalx instruction.
	* Makefile.in (mips16-opc.o): New target.
	* configure.in: Use mips16-opc.o for bfd_mips_arch.
	* configure: Rebuild.
 1996-11-26 15:59:18 +00:00
J.T. Conklin
520e44a15a * m68k-opc.c (m68k_opcodes): Simplify table by using < and > 
operand specifiers in *save, *restore and movem* instructions.
 1996-11-26 03:24:55 +00:00
J.T. Conklin
da34628ad8 * m68k-opc.c (m68k-opcodes): Fix move and movem instructions for 
the coldfire.
 1996-11-26 01:54:16 +00:00
J.T. Conklin
0dd19a8f36 * m68k-opc.c (m68k-opcodes): Fix many forms of the move 
instruction for the coldfire.
 1996-11-26 00:17:17 +00:00
J.T. Conklin
09d205d155 * m68k-opc.c (m68k-opcodes): The coldfire (mcf5200) can only use 
register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
 1996-11-25 22:33:46 +00:00
J.T. Conklin
1852237cf4 * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage 
specifier of the effective-address operand in immediate forms of
arithmetic instructions.  The specifier for the immediate operand
notes how and where the constant will be stored.
 1996-11-25 21:39:55 +00:00
Jeff Law
731c7b4bb8 * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" 
opcode.
 1996-11-25 19:46:21 +00:00
Jeff Law
76783aa31c * mn10300-dis.c (disassemble): Use '$' instead of '%' for 
register prefix.
It's easier for the assembler...
 1996-11-25 18:46:06 +00:00
Jeff Law
11cd057a41 * mn10300-dis.c (disassemble): Prefix registers with '%'. 1996-11-25 18:21:08 +00:00
Jeff Law
f0e98103c5 * mn10300-dis.c (disassemble): Handle register lists. 
More disassembler stuff.
 1996-11-20 18:39:48 +00:00
Jeff Law
f039819018 * mn10300-opc.c: Fix handling of register list operand for 
"call", "ret", and "rets" instructions.
Stuff noticed while working on disasembler.
 1996-11-20 18:32:44 +00:00
Jeff Law
aa9c04cd55 * mn10300-dis.c (disassemble): Print PC-relative and memory 
addresses symbolically if possible.
        * mn10300-opc.c: Distinguish between absolute memory addresses,
        pc-relative offsets & random immediates.
More disassembler work.
 1996-11-20 18:02:31 +00:00
Jeff Law
f497f3ae7c * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte 
in 7 byte insns.
        (disassemble): Handle SPLIT and EXTENDED operands.
 1996-11-20 17:36:31 +00:00
Jeff Law
d91028d2c7 * mn10300-dis.c: Rough cut at printing some operands. 1996-11-20 00:55:22 +00:00
Jeff Law
4aa92185f8 * mn10300-dis.c: Start working on disassembler support. 
* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
Selects opcodes & consumes bytes.  Breaks badly if given data instead of
code.  No operands yet.
 1996-11-19 23:59:27 +00:00
Jeff Law
99246e03f9 * mn10300-opc.c (mn10300_operands): Add "REGS" for a register 
list.
        (mn10300_opcodes): Use REGS for register list in "movm" instructions.
 1996-11-19 20:32:31 +00:00
Michael Meissner
b337f8691f Add3 sets the carry 1996-11-18 20:21:55 +00:00
Jeff Law
54dfaf0a65 * mn10300-opc.c (mn10300_opcodes): Demand parens around 
register argument is calls and jmp instructions.
Found trying to build libgcc2 for the mn10300 :-)
 1996-11-15 20:43:44 +00:00
Jeff Law
f2ab9a7505 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and 
getx operand.  Fix opcode for mulqu imm,dn.
Fix bugs exposed by gas testsuite (extended instructions).
 1996-11-07 07:26:25 +00:00
Jeff Law
26433754cc * mn10300-opc.c (mn10300_operands): Hijack "bits" field 
in MN10300_OPERAND_SPLIT operands for how many bits
        appear in the basic insn word.  Add IMM32_HIGH24,
        IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
        (mn10300_opcodes): Use new operands as needed.
Support for everything in the basic instruction manual (yippie!)
 1996-11-06 21:58:21 +00:00
Jeff Law
64ce06688d * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 
for bset, bclr, btst instructions.
        (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
For btst, bclr & bset.
 1996-11-06 21:18:27 +00:00
Jeff Law
fdef41f30b * mn10300-opc.c (mn10300_operands): Remove many redundant 
operands.  Update opcode table as appropriate.
        (IMM32): Add MN10300_OPERAND_SPLIT flag.
        (mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.
 1996-11-06 20:44:58 +00:00
Jeff Law
bb5e141ab4 * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 
operands (for indexed load/stores).  Fix bitpos for DI
        operand.  Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
        few instructions that insert immediates/displacements in the
        middle of the instruction.  Add IMM8E for 8 bit immediate in
        the extended part of an instruction.
        (mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
 1996-11-05 20:29:31 +00:00
Martin Hunt
733861650a Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Declare the trap instruction
 	sequential so the assembler never parallelizes it with
	other instructions.
 1996-11-05 18:34:19 +00:00
Jeff Law
e85c140a27 * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for 
a data/address register that appears in register field 0
        and register field 1.
        (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN

Hacking Matsushita again.  Yippie!
 1996-11-04 19:51:31 +00:00
Ian Lance Taylor
03e9562378 Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu> 
* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
	standard disassembly.

	* alpha-opc.c (alpha_operands): Rearrange flags slot.
	(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
	Recategorize PALcode instructions.
 1996-11-01 18:30:43 +00:00
Jeff Law
7d2759fc5b * v850-opc.c (v850_opcodes): Add relaxing "jbr". 1996-10-30 23:52:31 +00:00
Ian Lance Taylor
b56c3d6cee * mips-dis.c (_print_insn_mips): Don't print a trailing tab if 
there are no operand types.
 1996-10-29 21:31:22 +00:00
Jeff Law
244558e354 * v850-opc.c (D9_RELAX): Renamed from D9, all references 
changed.
        (v850_operands): Make sure D22 immediately follows D9_RELAX.
 1996-10-29 19:25:35 +00:00
Jeff Law
0f02ae6e5a * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for 
"bCC"instructions).
Because quantum's code uses jnz, jcc, etc etc etc.
 1996-10-24 23:55:11 +00:00
Ian Lance Taylor
4f6d7c2c30 * mips-dis.c (_print_insn_mips): Use a tab between the instruction 
and the arguments.
 1996-10-24 21:21:37 +00:00