Commit Graph

3174 Commits

Author SHA1 Message Date
Joel Brobecker
91c6776727 Spelling fixe in sim/ppc/vm.c
From Stephen Kitt  <steve@sk2.org>
        * vm.c (vm_synchronize_context): Spelling fix in function
        documentation.
2011-06-03 23:47:04 +00:00
Joel Brobecker
d009417cdb Minor spelling fix in ChangeLog. 2011-06-03 23:46:46 +00:00
Mike Frysinger
36f3e98103 sim: bfin: dma: fix indentation 2011-06-03 05:03:31 +00:00
Joel Brobecker
248d2a8fdc Add `sim_complete_command' definition to erc32 sim
This patch fixes a build failure at link time due to
sim_complete_command being undefined.  There was a recent change
that added this function to all the ports that do not use the
common/ subdir.  But somehow, the erc32 port got missed.

sim/erc32/ChangeLog:

        * interf.c (sim_complete_command): New stub function.
2011-06-01 17:35:02 +00:00
Mike Frysinger
440db57552 sim: fix minor --sysroot mem leak
The current --sysroot parsing attempts to keep from leaking memory by
treating the empty string specially (sine this is the initial value),
but it ends up leaking memory when the arg is an empty string.  So if
someone uses --sysroot "", the old value is leaked, as is the new one.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-27 18:05:16 +00:00
Mike Frysinger
3ddcae71bb sim: common: add back Blackfin syscalls
A semi-recent change which regenerated nltvals.def somehow missed all of
the Blackfin syscalls.  So regenerate against the latest tree to get them
back.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-26 18:20:13 +00:00
Mike Frysinger
ea1f7d4c8e sim: bfin: switch to new syscall trace level
Now that the common code supports the syscall trace level, change the
Blackfin code from using the event level to the syscall level.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-26 00:14:43 +00:00
Mike Frysinger
3a49ea9fac sim: add syscall tracing level
It's useful to be able to trace just the system calls the simulated
program is calling, so add a new --trace-syscall option for ports to
leverage if they choose.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-26 00:09:59 +00:00
Mike Frysinger
f2db709f4f sim: bfin: move model data into machs.h
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header.  The models themselves don't care about
where they're mapped, only the mach code does.  This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding.  Such as when a newer device model is
created, but with incompatible register names/layouts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:54:19 +00:00
Mike Frysinger
c43aadcaa6 sim: bfin: add a performance monitor stub
No counters get updated, but there is enough here for software to
poke things and work.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:41:29 +00:00
Mike Frysinger
dfb61fb66f sim: bfin: add bf526-0.2/bf54x-0.4 rom regions
Add regions for the on-chip roms on some newer Blackfin parts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-25 12:35:05 +00:00
Mike Frysinger
dd931b2ff2 sim: glue: allow bitwise devices to only glue ints
Some Blackfin parts tie a bunch of interrupt lines into a single OR
gate before feeding the result into the SIC.  The glue-or device in
the sim provides a nice way of modeling this exact behavior.  At the
moment though, it requires the device to be mapped into the address
space so that things could write to it directly.  This is not needed
for the Blackfin usage, so make it optional.  Now the glue devices
can be used to simply tie interrupt lines together.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-23 23:00:35 +00:00
Mike Frysinger
0e31da218e sim: glue: implement or/xor funcs
The glue device has a bunch of "todos" for the misc bitwise devices.
So implement two for fun -- the glue-or and glue-xor.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-23 22:59:54 +00:00
Mike Frysinger
0641104b2e sim: tests: support .S/.c files
Rather than requiring all sim tests to be preprocessed .s files, add
support for .S and .c files so we can easily write code using a higher
level language like C.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-16 18:48:31 +00:00
Mike Frysinger
efac2223c4 sim: bfin: allow pushing of SP
The hardware respects this insn, and some code (like the on-chip bootrom)
uses it, so allow it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 16:00:37 +00:00
Mike Frysinger
28fe96b798 sim: bfin: implement loop back support in the UARTs
The UART has a LOOP_ENA bit in its MCR register where writes to the THR
go to the RBR.  Implement support for this mode.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-14 15:59:09 +00:00
Mike Frysinger
34b47c3828 sim: fix func call style (space before paren)
Committed this as obvious:
	-foo(...);
	+foo (...);

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-11 20:02:42 +00:00
Hans-Peter Nilsson
3fc8ee5409 PR sim/12737
* sim/arm/iwmmxt/wcmpgt.cgs, sim/arm/iwmmxt/wmac.cgs,
	sim/arm/iwmmxt/wsra.cgs, sim/arm/xscale/blx.cgs: Kfail.
2011-05-11 04:59:28 +00:00
Mike Frysinger
b44f3f638e sim: bfin: fix UART LSR read-only bit saturation
A few bits in the newer UART LSR register are not sticky, so make sure
we clear them when returning updated status rather than leaving them
always set.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-05-09 18:14:01 +00:00
Joseph Myers
4d393d60c4 gdb:
* configure.host (xscale*): Don't handle target.
	* configure.tgt (thumb*-*-* | strongarm*-*-* | xscale-*-*): Don't
	handle targets.

gdb/gdbserver:
	* README: Don't mention xscale*-*-linux*.
	* configure.srv (xscale*-*-linux*): Don't handle target.

gdb/testsuite:
	* gdb.base/a2-run.exp (strongarm-*-coff): Don't handle target.
	* gdb.base/float.exp (xscale*-*-*, strongarm*-*-*): Don't handle
	targets.
	* gdb.base/long_long.exp (xscale*-*-*, strongarm*-*-*): Don't
	handle targets.

sim:
	* configure.tgt (thumb*-*-* | strongarm*-*-* | xscale-*-*): Don't
	handle targets.
	* configure: Regenerate.

sim/testsuite:
	* configure: Regenerate.
	* sim/arm/allinsn.exp (xscale*-*-*): Don't handle target.
	* sim/arm/misc.exp (thumb*-*-*, xscale*-*-*): Don't handle
	targets.
	* sim/arm/iwmmxt/iwmmxt.exp: Test for arm*-*-* instead of
	xscale*-*-*.
	* sim/arm/thumb/allthumb.exp (thumb*-*-*): Don't handle target.
	* sim/arm/xscale/xscale.exp: Test for arm*-*-* instead of
	xscale*-*-*.
2011-05-04 19:28:16 +00:00
Mike Frysinger
2613074f8f sim: bfin: constify dmac pmap arrays
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-27 21:29:03 +00:00
Mike Frysinger
054c055baf sim: gpio: add output support
Make all of the pins bidirectional, and support sending signals when
software drives the pins as outputs.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 05:47:14 +00:00
Mike Frysinger
5e0ba1a39e sim: gpio: update mask a/b signals better
When the mask a/b MMRs are written, the output signal might change levels
(as pins are [un]masked), so make sure we update the output level.

Further, make sure we handle edge ints correctly by first sending a high
signal followed by a low signal.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-26 05:46:02 +00:00
Mike Frysinger
af9f7da78b sim: add sim_complete_command stubs for non-common-using ports
For the ports that don't use the common/ subdir, we need to add stub funcs
to them to avoid build failures with gdb and command completion.  These do
not implement the actual completion functionality ... any port that wants
that can either convert to the common/ subdir, or fill out the function on
their own time.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16 18:16:36 +00:00
Mike Frysinger
0427acfba0 sim: bfin: use store buffer with more 32bit insns
A bunch of 32bit insns were not using the store buffer, so when they were
used in parallel insns, they would incorrectly clobber a register early.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-16 17:37:55 +00:00
Mike Frysinger
5592f70ec8 gdb: sim: add style fixes lost between git->cvs 2011-04-15 16:23:19 +00:00
Mike Frysinger
56a9aa1d10 gdb: sim: add command line completion
For now, only the sub-command name is completed.  No support yet for
completing options to that command.  But even this is a huge step as
currently, nothing is completed, and the basic "help sim" is fairly
obtuse as to what exactly the "sim" command accepts.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15 03:43:46 +00:00
Mike Frysinger
d2cfa400a1 sim: bfin: handle implicit DISALGNEXCPT with video insns
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.

Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-15 01:21:21 +00:00
Mike Frysinger
e10d6db33d sim: bfin: respect the port level on signals to the SIC
The SIC latches ints from peripherals to the CEC, but the peripherals
need to be able to tell the SIC when to stop.  So use the incoming level
to figure out when to set the int bits and when to clear it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 05:23:26 +00:00
Mike Frysinger
8aacdaf48d sim: bfin: add missing GPIO pin 15
Each GPIO block has 16 pins, and I only added 15 in the original
port list.  So add the missing 16th.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-11 05:22:23 +00:00
Mike Frysinger
d45bea91ec sim: dv-glue: fix up style a bit
This touches up the code a bit to match GNU style.  No functional changes.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-02 06:02:51 +00:00
Mike Frysinger
12c4cbd553 sim: fix up style a bit
This touches up the code a bit to match GNU style.  No functional changes.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-02 05:30:16 +00:00
Mike Frysinger
2b12772f43 sim: bfin: add OTP output port
This doesn't currently generate any interrupts (as there doesn't appear
to be any documentation to *when* it would even do so), but since the
HRM does say an interrupt line exists between the OTP and the SIC, add
one for completeness sake.  This will make a follow up patch easier.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-04-01 22:32:04 +00:00
Mike Frysinger
6294f8ea1e sim: bfin: regen configure to include new cfi device 2011-03-29 18:39:51 +00:00
Mike Frysinger
66ee273116 sim: cfi: new flash device simulation
This simulates a CFI flash.  Its pretty configurable via the device
tree.  For now, only basic read/write/erase operations are supported
for the Intel command set, but it's easy enough to extend support.
It's certainly enough to trick Das U-Boot into using it for probing,
reading, writing, and erasing.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29 17:57:21 +00:00
Mike Frysinger
1a3af0bfc3 sim: bfin: fix sign extension with 16bit acc add insns
The current implementation attempts to handle the 16bit sign extension
itself.  Unfortunately, it gets it right in some cases.  So rather than
fix that logic, just drop it in favor of using 16bit signed casts.  Now
gcc will take care of getting the logic right.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-29 01:41:49 +00:00
Mike Frysinger
36aef94270 sim: bfin: handle saturation with RND12 sub insns
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved.  So add handling for this edge
case to match the hardware.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-27 04:03:05 +00:00
Mike Frysinger
fcd1ee07d3 sim: bfin: add missing VS set with add/sub insns
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-26 06:02:41 +00:00
Mike Frysinger
a31d4fd99d sim: bfin: add hw tracing to gpio/sic port events
Makes it a lot easier to find out what's going on with interrupt lines
if the ports have tracing output.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:13:57 +00:00
Mike Frysinger
b72cc8e145 sim: bfin: fix GPIO logic bugs when processing events
We need the DIR bit cleared, not set, in order for the pin to be treated
as an input.

When looking up the data value, we need to shift the "level" value over by
"my_port" rather than "bit" as the latter has already been shifted over.
We also should normalize the "level" coming in from the outside worlds to
the set of {0,1} since those are the only values that matter to GPIOs.

We need the BOTH bit set, not cleared, in order for the pin to trigger
on both edges.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:13:23 +00:00
Mike Frysinger
eaf863cd1e sim: bfin: fix clear/set/toggle GPIO handling
The clear/set/toggle MMRs aren't backed by "real" data; they implicitly
perform bit operations on the associated data register.  So when we go
to process writes to them, we need to adjust the pointer accordingly so
that the actual backing data is modified.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-25 00:12:47 +00:00
Mike Frysinger
b16a1f4c4f sim: bfin: document SIC limitation
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:18:17 +00:00
Mike Frysinger
9922f80319 sim: bfin: fix inverted W1C logic
When I originally wrote the w1c helper funcs, I used it in a few places.
Then I forgot how it worked and when I later documented it, I described
the 3rd arg in the exact opposite way it is actually used.  This error
propagated to a bunch of devices registers that were not explicitly
tested (a bunch of the devices are stubs which merely exist to say "no
device is connected" to make device drivers happy).

So once the documentation is unscrewed, fix all of the broken call sites.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:17:14 +00:00
Mike Frysinger
2d2bab5b21 sim: bfin: define more UART LSR bits
We'll need these bits in an upcoming patch, so map out the whole
LSR MMR now.

Fix up indentation style while we're here.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:16:50 +00:00
Mike Frysinger
972dbc8ade sim: bfin: fix typo in TWI stat reg
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:16:22 +00:00
Mike Frysinger
8e670c0a3f sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are set
The Blackfin PRM says that the top 8 bits of the accumulator must be
cleared when using the VIT_MAX insn, so the sim has followed this spec.
Matching the hardware behavior though when the high bits are not cleared
is easy to do and doesn't break existing behavior, so go for it.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:14:20 +00:00
Mike Frysinger
de0addfbef sim: bfin: always do 16bit sign extension with the SEARCH insn
The Blackfin PRM does not cover this case, but the hardware is clear: even
if the search criteria is not met (and thus a new 16bit value is loaded up
into the accumulator), the accumulator undergoes 16bit sign extension.  So
simply reload the low signed 16bits in that case.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:13:32 +00:00
Mike Frysinger
beb378a5f2 sim: bfin: update AV and AC ASTAT bits with acc negation
The Acc=-Acc insn can overflow or carry with edge values, so make sure
we update the ASTAT bits accordingly to match the hardware.  Also fix
a thinko where we always updated AC0 even when working with A1 regs.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:12:16 +00:00
Mike Frysinger
e4a861d14b sim: bfin: fix thinko in SIC pin encoding
When encoding the SIC/pin info into unique input port ids, I used bases
of 100 when I meant to use 0x100.  Rather than simply fix the decoding
math in the different functions, create a few helper macros to simplify
the SIC/pin encoding and decoding steps.  This makes the resulting tables
nice & clear.

And now that pins are clear, the 533 and 537 port_event handlers may
easily be merged into one.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:11:08 +00:00
Mike Frysinger
8d8a97461a sim: bfin: allow byteop[123]p src regs to be the same
The hardware allows the byteop[123]p insns to use the same src reg pair,
so remove the combination check in the sim.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-03-24 03:08:15 +00:00