Running an address signed binary through GDB on a non pauth system
gives the following error:
Call Frame Instruction op 45 in vendor extension space is not handled on this architecture.
Instead GDB should ignore the op, treating it as a nop.
Add test case for pauth binaries, regardless of whether the target
supports it.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_execute_dwarf_cfa_vendor_op): Treat
DW_CFA_AARCH64_negate_ra_state as nop on non pauth targets.
gdb/testsuite/ChangeLog:
* gdb.arch/aarch64-pauth.c: New test.
* gdb.arch/aarch64-pauth.exp: New file.
This removes a VEC from aarch64-tdep.c, replacing it with a
std::vector.
gdb/ChangeLog
2019-05-04 Tom Tromey <tom@tromey.com>
* aarch64-tdep.c (stack_item_t): Remove typedef and DEF_VEC.
(struct aarch64_call_info): Add initializers.
<si>: Now a std::vector.
(pass_on_stack, aarch64_push_dummy_call): Update.
While trying to build GDB on i686, I found the following error:
In file included from ../../gdb/common/common-defs.h:105,
from ../../gdb/defs.h:28,
from ../../gdb/aarch64-tdep.c:21:
../../gdb/aarch64-tdep.c: In function 'gdbarch* aarch64_gdbarch_init(gdbarch_info, gdbarch_list*)':
../../gdb/aarch64-tdep.c:3176:43: error: format '%ld' expects argument of type 'long int', but argument 4 has type 'uint64_t' {aka 'long long unsigned int'} [-Werror=format=]
3176 | internal_error (__FILE__, __LINE__, _("VQ out of bounds: %ld (max %d)"),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../gdb/common/gdb_locale.h:28:29: note: in definition of macro '_'
28 | # define _(String) gettext (String)
| ^~~~~~
../../gdb/aarch64-tdep.c:3176:64: note: format string is defined here
3176 | internal_error (__FILE__, __LINE__, _("VQ out of bounds: %ld (max %d)"),
| ~~^
| |
| long int
| %lld
This happens because aarch64-tdep.c:aarch64_gdbarch_init prints a
"uint64_t" variable using "%ld". This patch fixes the build by using
"pulongest" instead. As explained in a similar fix (commit
495143533ad95369811391c6e3c6dadd69d7dd67), this should be safe because
if aarch64-tdep.c is included in the build, then ULONGEST must be a
64-bit type.
gdb/ChangeLog:
2019-04-24 Sergio Durigan Junior <sergiodj@redhat.com>
* aarch64-tdep.c (aarch64_gdbarch_init): Use "pulongest" to print
"vq".
Replaces use of aarch64_type_align with common type_align function.
Doing this fixes a bug in aarch64_type_align where static fields are
considered as part of the alignment calculation of a struct, which
results in arguments passed on the stack being misaligned. This bug
is exposed in the new test gdb.cp/many-args.exp.
Part of the old aarch64_type_align is retained and used as the gdbarch
type align callback in order to correctly align vectors.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_type_align): Only handle vector override
case.
(pass_on_stack): Use type_align.
(aarch64_gdbarch_init): Register aarch64_type_align gdbarch
function.
gdb/testsuite/ChangeLog:
* gdb.cp/many-args.cc: New file.
* gdb.cp/many-args.exp: New file.
Override the thread_architecture method, similar to SPU. If the vector
length has changed, then find the arch using info, making sure the vector
length is passed down to the init routine.
In the init routine, ensure the arch has the correct vector length.
Example output. Program is stopped in thread 2, just before it calls prctl
to change the vector length
(gdb) info threads
Id Target Id Frame
1 Thread 0xffffbf6f4000 (LWP 3188) "sve_change" 0x0000ffffbf6ae130 in pthread_join ()
* 2 Thread 0xffffbf55e200 (LWP 3189) "sve_change" thread1 (arg=0xfeedface) at sve_change_size.c:28
(gdb) print $vg
$1 = 8
(gdb) print $z0.s.u
$2 = {623191333, 623191333, 623191333, 623191333, 0 <repeats 12 times>}
(gdb) n
29 int ret = prctl(PR_SVE_SET_VL, vl/2);
(gdb) n
30 printf ("Changed: ret\n", ret);
(gdb) print $vg
$4 = 4
(gdb) print $z0.s.u
$5 = {623191333, 623191333, 623191333, 623191333, 0, 0, 0, 0}
(gdb) thr 1
[Switching to thread 1 (Thread 0xffffbf6f4000 (LWP 3181))]
(gdb) print $vg
$6 = 8
(gdb) print $z0.s.u
$7 = {623191333, 623191333, 623191333, 623191333, 0 <repeats 12 times>}
gdb/ChangeLog:
* aarch64-linux-nat.c
(aarch64_linux_nat_target::thread_architecture): Add override.
* aarch64-tdep.c (aarch64_gdbarch_init): Ensure different tdesc for
each VQ.
Move the lookup_by_info to the top of the function to avoid unnecessarily
creating a new feature when the gdbarch already exists.
Add some additional cleanups that have no functional effect.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_gdbarch_init): Move gdbarch lookup.
A recent change made the AArch64 self tests resuse the saved regs
cache, rather than creating a new one. Ensure it is reset to default
values between tests.
Do this by splitting the reset functionality from trad_frame_alloc_saved_regs
into a new function.
Fixes selftest on AArch64.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_analyze_prologue_test): Reset saved regs.
* trad-frame.c (trad_frame_reset_saved_regs): New function.
(trad_frame_alloc_saved_regs): Call trad_frame_reset_saved_regs.
* trad-frame.h (trad_frame_reset_saved_regs): New declaration.
This rewrites gdb's TRY/CATCH to plain C++ try/catch. The patch was
largely written by script, though one change (to a comment in
common-exceptions.h) was reverted by hand.
gdb/ChangeLog
2019-04-08 Tom Tromey <tom@tromey.com>
* xml-support.c: Use C++ exception handling.
* x86-linux-nat.c: Use C++ exception handling.
* windows-nat.c: Use C++ exception handling.
* varobj.c: Use C++ exception handling.
* value.c: Use C++ exception handling.
* valprint.c: Use C++ exception handling.
* valops.c: Use C++ exception handling.
* unittests/parse-connection-spec-selftests.c: Use C++ exception
handling.
* unittests/cli-utils-selftests.c: Use C++ exception handling.
* typeprint.c: Use C++ exception handling.
* tui/tui.c: Use C++ exception handling.
* tracefile-tfile.c: Use C++ exception handling.
* top.c: Use C++ exception handling.
* thread.c: Use C++ exception handling.
* target.c: Use C++ exception handling.
* symmisc.c: Use C++ exception handling.
* symfile-mem.c: Use C++ exception handling.
* stack.c: Use C++ exception handling.
* sparc64-linux-tdep.c: Use C++ exception handling.
* solib.c: Use C++ exception handling.
* solib-svr4.c: Use C++ exception handling.
* solib-spu.c: Use C++ exception handling.
* solib-frv.c: Use C++ exception handling.
* solib-dsbt.c: Use C++ exception handling.
* selftest-arch.c: Use C++ exception handling.
* s390-tdep.c: Use C++ exception handling.
* rust-lang.c: Use C++ exception handling.
* rust-exp.y: Use C++ exception handling.
* rs6000-tdep.c: Use C++ exception handling.
* rs6000-aix-tdep.c: Use C++ exception handling.
* riscv-tdep.c: Use C++ exception handling.
* remote.c: Use C++ exception handling.
* remote-fileio.c: Use C++ exception handling.
* record-full.c: Use C++ exception handling.
* record-btrace.c: Use C++ exception handling.
* python/python.c: Use C++ exception handling.
* python/py-value.c: Use C++ exception handling.
* python/py-utils.c: Use C++ exception handling.
* python/py-unwind.c: Use C++ exception handling.
* python/py-type.c: Use C++ exception handling.
* python/py-symbol.c: Use C++ exception handling.
* python/py-record.c: Use C++ exception handling.
* python/py-record-btrace.c: Use C++ exception handling.
* python/py-progspace.c: Use C++ exception handling.
* python/py-prettyprint.c: Use C++ exception handling.
* python/py-param.c: Use C++ exception handling.
* python/py-objfile.c: Use C++ exception handling.
* python/py-linetable.c: Use C++ exception handling.
* python/py-lazy-string.c: Use C++ exception handling.
* python/py-infthread.c: Use C++ exception handling.
* python/py-inferior.c: Use C++ exception handling.
* python/py-gdb-readline.c: Use C++ exception handling.
* python/py-framefilter.c: Use C++ exception handling.
* python/py-frame.c: Use C++ exception handling.
* python/py-finishbreakpoint.c: Use C++ exception handling.
* python/py-cmd.c: Use C++ exception handling.
* python/py-breakpoint.c: Use C++ exception handling.
* python/py-arch.c: Use C++ exception handling.
* printcmd.c: Use C++ exception handling.
* ppc-linux-tdep.c: Use C++ exception handling.
* parse.c: Use C++ exception handling.
* p-valprint.c: Use C++ exception handling.
* objc-lang.c: Use C++ exception handling.
* mi/mi-main.c: Use C++ exception handling.
* mi/mi-interp.c: Use C++ exception handling.
* mi/mi-cmd-stack.c: Use C++ exception handling.
* mi/mi-cmd-break.c: Use C++ exception handling.
* main.c: Use C++ exception handling.
* linux-thread-db.c: Use C++ exception handling.
* linux-tdep.c: Use C++ exception handling.
* linux-nat.c: Use C++ exception handling.
* linux-fork.c: Use C++ exception handling.
* linespec.c: Use C++ exception handling.
* language.c: Use C++ exception handling.
* jit.c: Use C++ exception handling.
* infrun.c: Use C++ exception handling.
* infcmd.c: Use C++ exception handling.
* infcall.c: Use C++ exception handling.
* inf-loop.c: Use C++ exception handling.
* i386-tdep.c: Use C++ exception handling.
* i386-linux-tdep.c: Use C++ exception handling.
* guile/scm-value.c: Use C++ exception handling.
* guile/scm-type.c: Use C++ exception handling.
* guile/scm-symtab.c: Use C++ exception handling.
* guile/scm-symbol.c: Use C++ exception handling.
* guile/scm-pretty-print.c: Use C++ exception handling.
* guile/scm-ports.c: Use C++ exception handling.
* guile/scm-param.c: Use C++ exception handling.
* guile/scm-math.c: Use C++ exception handling.
* guile/scm-lazy-string.c: Use C++ exception handling.
* guile/scm-frame.c: Use C++ exception handling.
* guile/scm-disasm.c: Use C++ exception handling.
* guile/scm-cmd.c: Use C++ exception handling.
* guile/scm-breakpoint.c: Use C++ exception handling.
* guile/scm-block.c: Use C++ exception handling.
* guile/guile-internal.h: Use C++ exception handling.
* gnu-v3-abi.c: Use C++ exception handling.
* gdbtypes.c: Use C++ exception handling.
* frame.c: Use C++ exception handling.
* frame-unwind.c: Use C++ exception handling.
* fbsd-tdep.c: Use C++ exception handling.
* f-valprint.c: Use C++ exception handling.
* exec.c: Use C++ exception handling.
* event-top.c: Use C++ exception handling.
* event-loop.c: Use C++ exception handling.
* eval.c: Use C++ exception handling.
* dwarf2read.c: Use C++ exception handling.
* dwarf2loc.c: Use C++ exception handling.
* dwarf2-frame.c: Use C++ exception handling.
* dwarf2-frame-tailcall.c: Use C++ exception handling.
* dwarf-index-write.c: Use C++ exception handling.
* dwarf-index-cache.c: Use C++ exception handling.
* dtrace-probe.c: Use C++ exception handling.
* disasm-selftests.c: Use C++ exception handling.
* darwin-nat.c: Use C++ exception handling.
* cp-valprint.c: Use C++ exception handling.
* cp-support.c: Use C++ exception handling.
* cp-abi.c: Use C++ exception handling.
* corelow.c: Use C++ exception handling.
* completer.c: Use C++ exception handling.
* compile/compile-object-run.c: Use C++ exception handling.
* compile/compile-object-load.c: Use C++ exception handling.
* compile/compile-cplus-symbols.c: Use C++ exception handling.
* compile/compile-c-symbols.c: Use C++ exception handling.
* common/selftest.c: Use C++ exception handling.
* common/new-op.c: Use C++ exception handling.
* cli/cli-script.c: Use C++ exception handling.
* cli/cli-interp.c: Use C++ exception handling.
* cli/cli-cmds.c: Use C++ exception handling.
* c-varobj.c: Use C++ exception handling.
* btrace.c: Use C++ exception handling.
* breakpoint.c: Use C++ exception handling.
* break-catch-throw.c: Use C++ exception handling.
* arch-utils.c: Use C++ exception handling.
* amd64-tdep.c: Use C++ exception handling.
* ada-valprint.c: Use C++ exception handling.
* ada-typeprint.c: Use C++ exception handling.
* ada-lang.c: Use C++ exception handling.
* aarch64-tdep.c: Use C++ exception handling.
gdb/gdbserver/ChangeLog
2019-04-08 Tom Tromey <tom@tromey.com>
* server.c: Use C++ exception handling.
* linux-low.c: Use C++ exception handling.
* gdbreplay.c: Use C++ exception handling.
When SVE is enabled, the V registers become pseudo registers based
on the Z registers. They should look the same as they do when
there is no SVE.
The existing code viewed them as single value registers. Switch
this to a vector.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_vnv_type): Use vector types.
Pauth address signing is enabled at binary compile time. When enabled the
return addresses for functions may be mangled. This patch adds functionality
to restore the original address for use in the prologue scan unwinder.
In the prologue analyzer, check for PACIASP/PACIBSP (enable address mangling)
and AUTIASP/AUTIBSP (disable address mangling).
When unwinding the PC from the prologue, unmask the register if required.
Add a test case to the prologue tests.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_analyze_prologue): Check for pauth
instructions.
(aarch64_analyze_prologue_test): Add PACIASP test.
(aarch64_prologue_prev_register): Unmask PC value.
Pauth address signing is enabled at binary compile time. When enabled the
return addresses for functions may be mangled. This patch adds functionality
to restore the original address for use in the DWARF unwinder.
DW_CFA_AARCH64_negate_ra_state in a binary indicates the toggling of address
signing between enabled and disabled. Ensure the state is stored in the DWARF
register ra_state.
Ensure the pauth DWARF registers are initialised.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_frame_unmask_address): New function.
(aarch64_dwarf2_prev_register): Unmask PC value.
(aarch64_dwarf2_frame_init_reg): Init pauth registers.
(aarch64_execute_dwarf_cfa_vendor_op): Check for
DW_CFA_AARCH64_negate_ra_state.
(aarch64_gdbarch_init): Add aarch64_execute_dwarf_cfa_vendor_op.
Map the pauth registers to DWARF.
Add a new pseudo register ra_state and also map this to DWARF. This register
is hidden from the user - prevent it from being read or written to. It will
be used for the unmangling of addresses.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_dwarf_reg_to_regnum): Check for pauth
registers.
(aarch64_pseudo_register_name): Likewise.
(aarch64_pseudo_register_type): Likewise.
(aarch64_pseudo_register_reggroup_p): Likewise.
(aarch64_gdbarch_init): Add pauth registers.
* aarch64-tdep.h (AARCH64_DWARF_PAUTH_RA_STATE): New define.
(AARCH64_DWARF_PAUTH_DMASK): Likewise.
(AARCH64_DWARF_PAUTH_CMASK): Likewise.
(struct gdbarch_tdep): Add regnum for ra_state.
Initialise the pauth registers when creating a target description, and store
the regnum of the first pauth register.
Use ptrace to read the registers in the pauth feature.
Do not allow the registers to be written.
gdb/ChangeLog:
* aarch64-linux-nat.c (fetch_pauth_masks_from_thread): New
function.
(aarch64_linux_nat_target::fetch_registers): Read pauth registers.
* aarch64-tdep.c (aarch64_cannot_store_register): New function.
(aarch64_gdbarch_init): Add puth registers.
* aarch64-tdep.h (struct gdbarch_tdep): Add pauth features.
* arch/aarch64.h (AARCH64_PAUTH_DMASK_REGNUM): New define.
(AARCH64_PAUTH_CMASK_REGNUM): Likewise.
Pointer Authentication is a new feature in AArch64 v8.3-a. When enabled in
the compiler, function return addresses will be mangled by the kernel.
Add register description xml and wire up to aarch64_linux_read_description.
This description includes the two pauth user registers.
Nothing yet uses the feature - that is added in later patches.
gdb/ChangeLog:
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Add pauth param.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (struct target_desc): Add in pauth.
(aarch64_read_description): Add pauth param.
(aarch64_gdbarch_init): Likewise.
* aarch64-tdep.h (aarch64_read_description): Likewise.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/aarch64.h (aarch64_create_target_description): Likewise.
* features/Makefile: Add new files.
* features/aarch64-pauth.c: New file.
* features/aarch64-pauth.xml: New file.
gdb/doc/ChangeLog:
* gdb.texinfo: Describe pauth feature.
gdb/gdbserver/ChangeLog:
* linux-aarch64-ipa.c (get_ipa_tdesc): Add pauth param.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.c (aarch64_arch_setup): Likewise.
* linux-aarch64-tdesc-selftest.c (aarch64_tdesc_test): Likewise.
* linux-aarch64-tdesc.c (struct target_desc): Likewise.
(aarch64_linux_read_description): Likewise.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Likewise.
Make use of the default gdbarch methods for gdbarch_dummy_id,
gdbarch_unwind_pc, and gdbarch_unwind_sp where possible.
I have not tested this change but, by inspecting the code, I believe
the default methods are equivalent to the code being deleted.
gdb/ChangeLog:
* gdb/aarch64-tdep.c (aarch64_dummy_id): Delete.
(aarch64_unwind_pc): Delete.
(aarch64_unwind_sp): Delete.
(aarch64_gdbarch_init): Don't register deleted functions with
gdbarch.
AArch64 does not define any reggroups. This causes "maintenance print
reggroups" to dump the default set (which is ok).
However, if a new group is added via an xml file, then this now becomes
the only group.
Fixes gdb.xml/tdesc-regs.exp on AArch64.
gdb/ChangeLog:
* aarch64-tdep.c (aarch64_add_reggroups): New function
(aarch64_gdbarch_init): Call aarch64_add_reggroups.
Static members in C++ structs are global data and therefore not part of the
list of struct members considered for passing in registers.
Note the corresponding code in GCC (from which the GDB AAPCS code is based)
does not have any static member checks due to the static members not being
part of the struct type at that point.
Extend gdb.base/infcall-nested-structs.exp to test structs with static
members when compiled for C++. XFAIL more cases for x86_64 (see gdb/24104).
For completeness, ensure some test cases have both empty structures and
static members.
Also fixes gdb.dwarf2/dw2-cp-infcall-ref-static.exp.
gdb/ChangeLog:
* aarch64-tdep.c (aapcs_is_vfp_call_or_return_candidate_1): Check
for static members.
(pass_in_v_vfp_candidate): Likewise.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.c (struct struct_static_02_01):
New structure.
(struct struct_static_02_02): Likewise.
(struct struct_static_02_03): Likewise.
(struct struct_static_02_04): Likewise.
(struct struct_static_04_01): Likewise.
(struct struct_static_04_02): Likewise.
(struct struct_static_04_03): Likewise.
(struct struct_static_04_04): Likewise.
(struct struct_static_06_01): Likewise.
(struct struct_static_06_02): Likewise.
(struct struct_static_06_03): Likewise.
(struct struct_static_06_04): Likewise.
(cmp_struct_static_02_01): Likewise.
(cmp_struct_static_02_02): Likewise.
(cmp_struct_static_02_03): Likewise.
(cmp_struct_static_02_04): Likewise.
(cmp_struct_static_04_01): Likewise.
(cmp_struct_static_04_02): Likewise.
(cmp_struct_static_04_03): Likewise.
(cmp_struct_static_04_04): Likewise.
(cmp_struct_static_06_01): Likewise.
(cmp_struct_static_06_02): Likewise.
(cmp_struct_static_06_03): Likewise.
(cmp_struct_static_06_04): Likewise.
(call_all): Test new structs.
* gdb.base/infcall-nested-structs.exp: Likewise.
When gdb.base/infcall-nested-structs.c is complied as C++, the compiler
will not pass structs containing empty structs via float arguments.
This is because structs in C++ have a minimum size of 1, causing padding
in the struct once compiled. The AAPCS does not allow structs with
padding to be passed in float arguments.
Add padding checks to AArch64 and add C++ compile variant to the test.
Some of the tests fail on X86_64. This has been raised as bug gdb/24104.
gdb/ChangeLog:
* aarch64-tdep.c (aapcs_is_vfp_call_or_return_candidate_1): Check
for padding.
gdb/testsuite/ChangeLog:
* gdb.base/infcall-nested-structs.exp: Test C++ in addition to C.
This replaces "the the" with "the" in various comments.
Tested by rebuilding. This didn't test the solib-dsbt.c change, but
it looks harmless.
gdb/ChangeLog
2019-01-17 Tom Tromey <tromey@bapiya>
* valprint.c: Replace "the the" with "the".
* symtab.c: Replace "the the" with "the".
* solib.c: Replace "the the" with "the".
* solib-dsbt.c: Replace "the the" with "the".
* linespec.c: Replace "the the" with "the".
* dwarf2loc.h: Replace "the the" with "the".
* amd64-windows-tdep.c: Replace "the the" with "the".
* aarch64-tdep.c: Replace "the the" with "the".
This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
The following will segfault on aarch64 if foo is in another object,
was compiled as c++ and has no debug symbols:
(gdb) p (int)foo()
This is because aarch64_push_dummy_call determines the return type
of the function and then does not check for null pointer.
A null pointer for the return type means the call has no debug
information. For the code to get here, then the call must have
been cast, otherwise we'd error out sooner. In the case of a
no-debug-info call cast, the return type is the type the user
had cast the call to, but we do not have that information
available here.
However, aarch64_push_dummy_call only requires the return type in
order to calculate lang_struct_return. This information is available
in the return_method enum. The fix is to simply use this instead.
Adds testcase to check calls across objects, with all combinations
of c, c++, debug and no debug.
gdb/ChangeLog:
PR gdb/22736:
* aarch64-tdep.c (aarch64_push_dummy_call): Remove
lang_struct_return code.
gdb/testsuite/ChangeLog:
PR gdb/22736:
* gdb.cp/infcall-nodebug-lib.c: New test.
* gdb.cp/infcall-nodebug-main.c: New test.
* gdb.cp/infcall-nodebug.exp: New file.
Consider the gdb.ada/array_return.exp testcase, and in particular,
consider the following code...
type Small_Float_Vector is array (1 .. 2) of Float;
function Create_Small_Float_Vector return Small_Float_Vector is
begin
return (others => 4.25);
end Create_Small_Float_Vector;
... which declares a type which is an array with 2 floats in it
(floats are 4 bytes on AArch64), trying to get GDB to print
the return value from that function does not work:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 0.0)
^^^
|||
We expected the value shown to be:
(gdb) fin
Run till exit from #0 pck.create_small_float_vector () at /[...]/pck.adb:15
0x000000000000062c in p () at /[...]/p.adb:11
11 Vector := Create_Small_Float_Vector;
Value returned is $1 = (4.25, 4.25)
Because the return type is an HFA, it is returned via the first two
SIMD registers. However, what happens is that the current implementation
fails to realize that this is an HFA, and therefore fetches the return
value from the wrong location. And the reason why it fails to realize
this is because it thinks that our array has 8 elements (HFAs have
a maximum of 4). Looking at aapcs_is_vfp_call_or_return_candidate_1,
where this is determined, we can easily see why (looks like a thinko):
| case TYPE_CODE_ARRAY:
| [...]
| struct type *target_type = TYPE_TARGET_TYPE (type);
| int count = aapcs_is_vfp_call_or_return_candidate_1
| (target_type, fundamental_type);
|
| if (count == -1)
| return count;
|
!! -> | count *= TYPE_LENGTH (type);
| return count;
Here, we first determine the count for one element of our array,
and so we should then be multiplying that count by the number
of elements in our array (2 in our case). But instead, we multiply it
by the total size (8). As a result, we do not classify the return
type as an HFA, and thus pick the wrong location for fetching
the return value.
gdb/ChangeLog:
* aarch64-tdep.c (aapcs_is_vfp_call_or_return_candidate_1):
return the correct count for potential HFAs.
Tested on aarch64-linux, fixes:
array_return.exp: value printed by finish of Create_Small_Float_Vector
This patch adds support for debugging Ravenscar tasks, similar to what
is done for ppc and sparc.
gdb/ChangeLog:
* aarch64-ravenscar-thread.h, aarch64-ravenscar-thread.c:
New files.
* aarch64-tdep.c: #include "aarch64-ravenscar-thread.h".
(aarch64_gdbarch_init): Add call to register_aarch64_ravenscar_ops.
* Makefile.in (ALL_64_TARGET_OBS): Add aarch64-ravenscar-thread.o.
(HFILES_NO_SRCDIR): Add aarch64-ravenscar-thread.h.
(ALLDEPFILES): Add aarch64-ravenscar-thread.c.
* configure.tgt (cpu_obs) [aarch64*-*-*]: Add ravenscar-thread.o
and aarch64-ravenscar-thread.o.
* NEWS: Add entry documenting Ravenscar tasking support
on AArch64 ELF.
Using "call" on a function that passes arguments via float registers can cause
gdb to overflow buffers.
Ensure enough memory is reserved to hold a full FP register.
This fixes gdb.base/callfuncs.exp for Aarch64 SVE.
2018-09-18 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (pass_in_v): Use register size.
(aarch64_extract_return_value): Likewise.
(aarch64_store_return_value): Likewise.
Use aapcs_is_vfp_call_or_return_candidate to detect float register
args, then pass in registers if there is room.
gdb/
* aarch64-tdep.c
(aapcs_is_vfp_call_or_return_candidate): Make static
(pass_in_v_or_stack): Remove function.
(pass_in_v_vfp_candidate): New function.
(aarch64_push_dummy_call): Check for float register candidates.
aapcs_is_vfp_call_or_return_candidate is as an eventual replacement
for is_hfa_or_hva.
This function is based on the GCC code
gcc/config/aarch64/aarch64.c:aarch64_vfp_is_call_or_return_candidate ()
gdb/
* aarch64-tdep.c (HA_MAX_NUM_FLDS): New macro.
(aapcs_is_vfp_call_or_return_candidate_1): New function.
(aapcs_is_vfp_call_or_return_candidate): Likewise.
Code like this:
CORE_ADDR breaks[2] = {-1, -1};
... gives a warning with -Wnarrowing. This patch changes all
instances of this to use CORE_ADDR_MAX instead.
gdb/ChangeLog
2018-08-27 Tom Tromey <tom@tromey.com>
* rs6000-tdep.c (ppc_deal_with_atomic_sequence): Use
CORE_ADDR_MAX.
* mips-tdep.c (mips_deal_with_atomic_sequence)
(micromips_deal_with_atomic_sequence): Use CORE_ADDR_MAX.
* arch/arm-get-next-pcs.c (thumb_deal_with_atomic_sequence_raw)
(arm_deal_with_atomic_sequence_raw): Use CORE_ADDR_MAX.
* alpha-tdep.c (alpha_deal_with_atomic_sequence): Use
CORE_ADDR_MAX.
* aarch64-tdep.c (aarch64_software_single_step): Use
CORE_ADDR_MAX.
tdesc_register_size returns number of bits, not bytes.
Rename to make it clearer.
Also, fixed bug in aarch64_get_tdesc_vq which assumed bytes.
gdb/
* target-descriptions.c (tdesc_register_bitsize): Rename.
* target-descriptions.h (tdesc_register_bitsize): Likewise.
* rs6000-tdep.c (rs6000_gdbarch_init): Use new name.
* aarch64-tdep.c (aarch64_get_tdesc_vq): Convert size.
This is as per the spec:
https://developer.arm.com/products/architecture/a-profile/docs/100985/0000
gdb/
* aarch64-tdep.c (aarch64_dwarf_reg_to_regnum): Add mappings.
* aarch64-tdep.h (AARCH64_DWARF_SVE_VG): Add define.
(AARCH64_DWARF_SVE_FFR): Likewise.
(AARCH64_DWARF_SVE_P0): Likewise.
(AARCH64_DWARF_SVE_Z0): Likewise.
Add the functionality for reading/writing pseudo registers.
On SVE the V registers are pseudo registers. This is supported
by adding AARCH64_SVE_V0_REGNUM.
* aarch64-tdep.c (AARCH64_SVE_V0_REGNUM): Add define.
(aarch64_vnv_type): Add function.
(aarch64_pseudo_register_name): Add V regs for SVE.
(aarch64_pseudo_register_type): Likewise.
(aarch64_pseudo_register_reggroup_p): Likewise.
(aarch64_pseudo_read_value_2): Use V0 offset for SVE
(aarch64_pseudo_read_value): Add V regs for SVE.
(aarch64_pseudo_write_2): Use V0 offset for SVE
(aarch64_pseudo_write): Add V regs for SVE.
* aarch64-tdep.h (struct gdbarch_tdep): Add vnv_type.
Reduce code copy/paste by adding two helper functions for
aarch64_pseudo_read_value and aarch64_pseudo_write
Does not change any functionality.
gdb/
* aarch64-tdep.c (aarch64_pseudo_read_value_1): New helper func.
(aarch64_pseudo_write_1): Likewise.
(aarch64_pseudo_read_value): Use helper.
(aarch64_pseudo_write): Likewise.
Enable SVE support for GDB by reading the VQ when creating a
target description.
Also ensurse that SVE is taken into account when creating
the tdep structure, and store the current VQ value directly in tdep.
gdb/
* aarch64-linux-nat.c (aarch64_linux_read_description): Support SVE.
* aarch64-tdep.c (aarch64_get_tdesc_vq): New function.
(aarch64_gdbarch_init): Check for SVE.
* aarch64-tdep.h (gdbarch_tdep::has_sve): New function.
Previously VQ was of type long. Using uint64_t ensures it always matches the
same type as the VG register.
Note that in the Linux kernel, VQ is 16bits. We cast it up to 64bits
immediately after reading to ensure we always use the same type throughout
the code.
gdb/
* aarch64-tdep.c (aarch64_read_description): Use uint64_t for VQ.
* aarch64-tdep.h (aarch64_read_description): Likewise.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/aarch64.h (aarch64_create_target_description): Likewise.
* features/aarch64-sve.c (create_feature_aarch64_sve): Likewise.
* nat/aarch64-sve-linux-ptrace.c(aarch64_sve_get_vq): Likewise.
* nat/aarch64-sve-linux-ptrace.h (aarch64_sve_get_vq): Likewise.
In order to prevent gaps in the register numbering, the Z registers
reuse the V register numbers (which become pseudos on SVE).
2018-06-01 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (aarch64_sve_register_names): New const
var.
* arch/aarch64.h (enum aarch64_regnum): Add SVE entries.
(AARCH64_SVE_Z_REGS_NUM): New define.
(AARCH64_SVE_P_REGS_NUM): Likewise.
(AARCH64_SVE_NUM_REGS): Likewise.
Remove regcache_raw_write, update all callers to use regcache::raw_write
instead.
gdb/ChangeLog:
* regcache.h (regcache_raw_write): Remove, update callers to use
regcache::raw_write instead.
* regcache.c (regcache_raw_write): Remove.
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.
These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.
This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.
The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.
gas/
PR binutils/21446
* config/tc-aarch64.c (parse_sys_reg): Return register flags.
(parse_operands): Fill in register flags.
gdb/
PR binutils/21446
* aarch64-tdep.c (aarch64_analyze_prologue,
aarch64_software_single_step, aarch64_displaced_step_copy_insn):
Indicate not interested in errors.
include/
PR binutils/21446
* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
(aarch64_decode_insn): Accept error struct.
opcodes/
PR binutils/21446
* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
and take error struct.
* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
aarch64_ins_reglist, aarch64_ins_ldst_reglist,
aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
aarch64_ext_reglist, aarch64_ext_ldst_reglist,
aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
(determine_disassembling_preference, aarch64_decode_insn,
print_insn_aarch64_word, print_insn_data): Take errors struct.
(print_insn_aarch64): Use errors.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-gen.c (print_operand_inserter): Use errors and change type to
boolean in aarch64_insert_operan.
(print_operand_extractor): Likewise.
* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
This patch fixes tagged pointer support for AArch64 GDB. Linux kernel
debugging failure was reported after tagged pointer support was committed.
After a discussion around best path forward to manage tagged pointers
on GDB side we are going to disable tagged pointers support for
aarch64-none-elf-gdb because for non-linux applications we cant be
sure if tagged pointers will be used by MMU or not.
Also for aarch64-linux-gdb we are going to sign extend user-space
address after clearing tag bits. This will help debug both kernel
and user-space addresses based on information from linux kernel
documentation given below:
According to AArch64 memory map:
https://www.kernel.org/doc/Documentation/arm64/memory.txt
"User addresses have bits 63:48 set to 0 while the kernel addresses have
the same bits set to 1."
According to AArch64 tagged pointers document:
https://www.kernel.org/doc/Documentation/arm64/tagged-pointers.txt
The kernel configures the translation tables so that translations made
via TTBR0 (i.e. userspace mappings) have the top byte (bits 63:56) of
the virtual address ignored by the translation hardware. This frees up
this byte for application use.
Running gdb testsuite after applying this patch introduces no regressions
and tagged pointer test cases still pass.
gdb/ChangeLog:
2018-05-10 Omair Javaid <omair.javaid@linaro.org>
PR gdb/23127
* aarch64-linux-tdep.c (aarch64_linux_init_abi): Add call to
set_gdbarch_significant_addr_bit.
* aarch64-tdep.c (aarch64_gdbarch_init): Remove call to
set_gdbarch_significant_addr_bit.
* utils.c (address_significant): Update to sign extend addr.
