* sparc-dis.c (sorted_opcodes): New static local.
(struct opcode_hash): `opcode' is pointer to const element.
(build_hash): First arg is now table of sorted pointers.
(print_insn_sparc): Sort opcodes by sorting table of pointers.
(compare_opcodes): Update.
(hash_keyword_name): New arg `case_sensitive_p'. Callers updated.
Handle case insensitive hashing.
(hash_keyword_value): Change type of `value' to unsigned int.
precision FP, mark it as such. Likewise for double precision
FP. Mark ISA1 insns. Consolidate duplicate opcodes where
possible.
(mips_builtin_opcodes): Remove non-existant r5900 instructions
toshiba_5900 stuff
* i386-dis.c (dis386[], dis386_twobyte[]): change pushl/popl
to pushS/popS for segment regs and byte constant so that
pushw/popw printed when in 16 bit data mode.
* i386-dis.c (dis386[]): change cwtl, cltd to cWtS, cStd to
print cbtw, cwtd in 16 bit data mode.
* i386-dis.c (putop): extra case W to support above.
* i386-dis.c (print_insn_x86): print addr32 prefix when given
address size prefix in 16 bit address mode.
* configure, config.in: Rebuild.
* sysdep.h: Include <stdlib.h> if it exists.
* sparc-dis.c: Include <stdio.h> and "sysdep.h". Don't include
<string.h>.
* Makefile.in: Rebuild dependencies.
(HFILES): New variable.
(CFILES): Add all C files.
(.dep, .dep1, dep.sed, dep, dep-in): New targets.
Delete old dependencies, and build new ones.
* dep-in.sed: New file.
* i386-dis.c (fetch_data): Add prototype.
* m68k-dis.c (fetch_data): Add prototype.
(dummy_print_address): Add prototype. Make static.
* ppc-opc.c (valid_bo): Add prototype.
* sparc-dis.c (build_hash_table): Add prototype.
(is_delayed_branch, compute_arch_mask): Add prototypes.
(print_insn_sparc): Make several local variables const.
(compare_opcodes): Change arguments to const PTR. Add prototype.
* sparc-opc.c (arg): Change name field to be const.
(lookup_name, lookup_value): Add prototypes. Change table and
name parameters to be const.
(sparc_encode_asi): Change name parameter to be const.
(sparc_encode_membar, sparc_encode_prefetch): Likewise.
(sparc_encode_sparclet_cpreg): Likewise.
(sparc_decode_asi): Change return type to be const.
(sparc_decode_membar, sparc_decode_prefetch): Likewise.
(sparc_decode_sparclet_cpreg): Likewise.
* m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use
floatformat_to_double to make portable.
(print_insn_arg): Use NEXTEXTEND macro when extracting extended
precision float.
(OFF_SL_BR_SCALED): ... to this, and added the flag
TIC80_OPERAND_BASEREL to the flags word.
(tic80_opcodes): Replace all occurances of LSI_SCALED with
OFF_SL_BR_SCALED.
Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
so that we can increase the size of the mips opcodes table
dynamically.
store BITNUM values in the table in one's complement form
to match behavior when assembler is given a raw numeric
value for a BITNUM operand.
* tic80-dis.c (print_operand_bitnum): Ditto.
(tic80_opcodes): Sort entries so that long immediate forms
come after short immediate forms, making it easier for
assembler to select the right one for a given operand.
and REG_DEST_E for register operands that have to be
an even numbered register. Add REG_FPA for operands that
are one of the floating point accumulator registers.
Add TIC80_OPERAND_MASK to flags for ENDMASK operand.
(tic80_opcodes): Change entries that need even numbered
register operands to use the new operand table entries.
Add "or" entries that are identical to "or.tt" entries.
disassembler.
* mips-dis.c (print_mips16_insn_arg): Display floating point
registers in operands of exit instruction. Print `$' before
register names in operands of entry and exit instructions.
pairs for all predefined symbols recognized by the assembler.
Also used by the disassembling routines.
(tic80_symbol_to_value): New function.
(tic80_value_to_symbol): New function.
* tic80-dis.c (print_operand_control_register,
print_operand_condition_code, print_operand_bitnum):
Remove private tables and use tic80_value_to_symbol function.
coldfire moveb instruction to not allow an address register as
destination. Although the documentation does not indicate that
this is invalid, experiments uncovered unexpected behavior.
Added a comment explaining the situation. Thanks to Andreas
Schwab for pointing this out to me.
entries are presorted so that entries with the same mnemonic are
adjacent to each other in the table. Sort the entries for each
instruction so that this is true.
function up into several smaller ones and arranged for
the instruction printing function to be callable recursively
to print vector instructions that have both a load and a
math instruction packed into a single opcode.
* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
to explain why it comes after the other vector opcodes.
* m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
move insns to handle immediate operands.
From Andreas Schwab:
* m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
New macros for building vector instruction opcodes.
(tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
FMT_LI, which were unused. The field is now a flags field.
Remove some opcodes that are possible, but illegal, such
as long immediate instructions with doubles for immediate
values. Add "vadd" and "vld" instructions.
the order more logical. Move the shift alias instructions ("rotl",
"shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
interspersed with the regular sr.x and sl.x instructions. Add
and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
"sub", "subu", "swcr", and "trap".
as floats.
* tic80-opc.c (SPFI): Add single precision floating point
immediate operand type.
(ROTATE): Add rotate operand type for shifts.
(ENDMASK): Add for shifts.
(n): Macro for the 'n' bit.
(i): Macro for the 'i' bit.
(PD): Macro for the 'PD' field.
(P2): Macro for the 'P2' field.
(P1): Macro for the 'P1' field.
(tic80_operands): Add entries for "exts", "extu", "fadd",
"fcmp", and "fdiv".
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
(SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
REG_BASE_M_SI, REG_BASE_M_LI respectively.
(REG_SCALED, LSI_SCALED): New operand types.
(E): New macro for 'E' bit at bit 27.
(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
opcodes, including the various size flavors (b,h,w,d) for
the direct load and store instructions.
in an instruction.
* tic80-dis.c (print_insn_tic80): Change comma and paren handling.
Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
* tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
(F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers.
(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
masks with "MASK_* & ~M_*" to get the M bit reset.
(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
David Edelsohn
Jeff Law
Felix Lee
Ian Lance Taylor
Gavin Romig-Koch
Martin Hunt
J.T. Conklin
Jim Wilson
Michael Meissner
Fred Fish
Dawn Perchik