0e35537d75
RISC-V: Add .insn support.
...
gas/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* config/tc-riscv.c (opcode_name_list): New.
(opcode_names_hash): Likewise.
(init_opcode_names_hash): Likewise.
(opcode_name_lookup): Likewise.
(validate_riscv_insn): New argument length, and add new format
which used in .insn directive.
(md_begin): Refine hash table initialization logic into
init_opcode_hash.
(init_opcode_hash): New.
(my_getOpcodeExpression): Parse opcode name for .insn.
(riscv_ip): New argument hash, able to handle .insn directive.
(s_riscv_insn): Handler for .insn directive.
(riscv_pseudo_table): New entry for .insn.
* doc/c-riscv.texi: Add documentation for .insn directive.
* testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
* testsuite/gas/riscv/insn.s: Likewise.
include/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* opcode/riscv.h (OP_MASK_FUNCT3): New.
(OP_SH_FUNCT3): Likewise.
(OP_MASK_FUNCT7): Likewise.
(OP_SH_FUNCT7): Likewise.
(OP_MASK_OP2): Likewise.
(OP_SH_OP2): Likewise.
(OP_MASK_CFUNCT4): Likewise.
(OP_SH_CFUNCT4): Likewise.
(OP_MASK_CFUNCT3): Likewise.
(OP_SH_CFUNCT3): Likewise.
(riscv_insn_types): Likewise.
opcodes/ChangeLog
2018-03-07 Kito Cheng <kito.cheng@gmail.com>
* riscv-opc.c (riscv_insn_types): New.
2018-03-14 16:04:03 -07:00
219d1afa89
Update year range in copyright notice of binutils files
2018-01-03 17:49:56 +10:30
3342be5dab
RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2
...
This matches the ISA specification. This also adds two tests: one to
make sure the assembler rejects invalid 'c.lui's, and one to make sure
we only relax valid 'c.lui's.
bfd/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* elfnn-riscv.c (_bfd_riscv_relax_lui): Don't relax to c.lui
when rd is x0.
include/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* opcode/riscv.h (VALID_RVC_LUI_IMM): c.lui can't load the
immediate 0.
gas/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* testsuite/gas/riscv/c-lui-fail.d: New testcase.
gas/testsuite/gas/riscv/c-lui-fail.l: Likewise.
gas/testsuite/gas/riscv/c-lui-fail.s: Likewise.
gas/testsuite/gas/riscv/riscv.exp: Likewise.
ld/ChangeLog
2017-10-24 Andrew Waterman <andrew@sifive.com>
* ld/testsuite/ld-riscv-elf/c-lui.d: New testcase.
ld/testsuite/ld-riscv-elf/c-lui.s: Likewise.
ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp: New test suite.
2017-10-24 08:02:46 -07:00
cc917fd93d
Add support for the Q extension to the RISCV ISA.
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gas * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
extension.
(riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
enabled and no other ABI is specified.
include * opcode/riscv-opc.h: Add support for the "q" ISA extension.
opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
extension.
* riscv-opcodes/all-opcodes: Likewise.
2017-01-03 17:42:01 +00:00
2571583aed
Update year range in copyright notice of all files.
2017-01-02 14:08:56 +10:30
e23eba971d
Add support for RISC-V architecture.
...
bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf.
* config.bdf: Likewise.
* configure.ac: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* archures.c: Add bfd_riscv_arch.
* reloc.c: Add riscv relocs.
* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
* elfnn-riscv.c: New file.
* elfxx-riscv.c: New file.
* elfxx-riscv.h: New file.
binutils* readelf.c (guess_is_rela): Add EM_RISCV.
(get_machine_name): Likewise.
(dump_relocations): Add support for riscv relocations.
(get_machine_flags): Add support for riscv flags.
(is_32bit_abs_reloc): Add R_RISCV_32.
(is_64bit_abs_reloc): Add R_RISCV_64.
(is_none_reloc): Add R_RISCV_NONE.
* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
Expect the debug_ranges test to fail.
gas * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this architecture.
* configure.in: Define a default architecture.
* configure: Regenerate.
* configure.tgt: Add entries for riscv.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
* config/tc-riscv.c: New file.
* config/tc-riscv.h: New file.
* doc/c-riscv.texi: New file.
* testsuite/gas/riscv: New directory.
* testsuite/gas/riscv/riscv.exp: New file.
* testsuite/gas/riscv/t_insns.d: New file.
* testsuite/gas/riscv/t_insns.s: New file.
ld * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this target.
* configure.tgt: Add riscv entries.
* emulparams/elf32lriscv-defs.sh: New file.
* emulparams/elf32lriscv.sh: New file.
* emulparams/elf64lriscv-defs.sh: New file.
* emulparams/elf64lriscv.sh: New file.
* emultempl/riscvelf.em: New file.
opcodes * configure.ac: Add entry for bfd_riscv_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Add support for riscv.
(disassembler_usage): Likewise.
* riscv-dis.c: New file.
* riscv-opc.c: New file.
include * dis-asm.h: Add prototypes for print_insn_riscv and
print_riscv_disassembler_options.
* elf/riscv.h: New file.
* opcode/riscv-opc.h: New file.
* opcode/riscv.h: New file.
2016-11-01 16:45:57 +00:00
Jim Wilson
Alan Modra
Andrew Waterman
Kito Cheng
Nick Clifton