This patch adds qualifiers to represent /z and /m suffixes on
predicate registers.
include/
* opcode/aarch64.h (AARCH64_OPND_QLF_P_Z): New aarch64_opnd_qualifier.
(AARCH64_OPND_QLF_P_M): Likewise.
opcodes/
* aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
AARCH64_OPND_QLF_P_[ZM].
(aarch64_print_operand): Print /z and /m where appropriate.
gas/
* config/tc-aarch64.c (vector_el_type): Add NT_zero and NT_merge.
(parse_vector_type_for_operand): Assert that the skipped character
is a '.'.
(parse_predication_for_operand): New function.
(parse_typed_reg): Parse /z and /m suffixes for predicate registers.
(vectype_to_qualifier): Handle NT_zero and NT_merge.
This patch adds the Zn and Pn registers, and associated fields and
operands.
include/
* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
aarch64_operand_class.
(AARCH64_OPND_CLASS_PRED_REG): Likewise.
(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
* aarch64-opc.c (fields): Add corresponding entries here.
(operand_general_constraint_met_p): Check that SVE register lists
have the correct length. Check the ranges of SVE index registers.
Check for cases where p8-p15 are used in 3-bit predicate fields.
(aarch64_print_operand): Handle the new SVE operands.
* aarch64-opc-2.c: Regenerate.
* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
* aarch64-asm.c (aarch64_ins_sve_index): New function.
(aarch64_ins_sve_reglist): Likewise.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
* aarch64-dis.c (aarch64_ext_sve_index): New function.
(aarch64_ext_sve_reglist): Likewise.
* aarch64-dis-2.c: Regenerate.
gas/
* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
(AARCH64_REG_TYPES): Add ZN and PN.
(get_reg_expected_msg): Handle them.
(parse_vector_type_for_operand): Add a reg_type parameter.
Skip the width for Zn and Pn registers.
(parse_typed_reg): Extend vector handling to Zn and Pn. Update the
call to parse_vector_type_for_operand. Set HASVARTYPE for Zn and Pn,
expecting the width to be 0.
(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
REG_TYPE_VN.
(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
(parse_operands): Handle the new Zn and Pn operands.
(REGSET16): New macro, split out from...
(REGSET31): ...here.
(reg_names): Add Zn and Pn entries.
SVE has some instructions in which the same register appears twice
in the assembly string, once as an input and once as an output.
This patch adds a general mechanism for that.
The patch needs to add new information to the instruction entries.
One option would have been to extend the flags field of the opcode
to 64 bits (since we already rely on 64-bit integers being available
on the host). However, the *_INSN macros mean that it's easy to add
new information as top-level fields without affecting the existing
table entries too much. Going for that option seemed to give slightly
neater code.
include/
* opcode/aarch64.h (aarch64_opcode): Add a tied_operand field.
(AARCH64_OPDE_UNTIED_OPERAND): New aarch64_operand_error_kind.
opcodes/
* aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
(_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
(V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
* aarch64-opc.c (aarch64_match_operands_constraint): Check for
tied operands.
gas/
* config/tc-aarch64.c (output_operand_error_record): Handle
AARCH64_OPDE_UNTIED_OPERAND.
SVE adds addresses in which the base or offset are vector registers.
The addresses otherwise have the same kind of form as normal AArch64
addresses, including things like SXTW with or without a shift, UXTW
with or without a shift, and LSL.
This patch therefore refactors the address-printing code so that it
can cope with both scalar and vector registers.
opcodes/
* aarch64-opc.c (get_offset_int_reg_name): New function.
(print_immediate_offset_address): Likewise.
(print_register_offset_address): Take the base and offset
registers as parameters.
(aarch64_print_operand): Update caller accordingly. Use
print_immediate_offset_address.
Use a macro to define 31 regular registers followed by a supplied
value for 0b11111. The SVE code will also use this for vector base
and offset registers.
opcodes/
* aarch64-opc.c (BANK): New macro.
(R32, R64): Take a register number as argument
(int_reg): Use BANK.
This patch generalises the interface to print_register_list so
that it can print register lists involving SVE z registers as
well as AdvSIMD v ones.
opcodes/
* aarch64-opc.c (print_register_list): Add a prefix parameter.
(aarch64_print_operand): Update accordingly.
FPIMM used the normal "imm" insert/extract methods, with a specific
test for FPIMM in the extract method. SVE needs to use the same
extractors, so rather than add extra checks for specific operand types,
it seemed cleaner to use a separate insert/extract method.
opcodes/
* aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
for FPIMM.
* aarch64-asm.h (ins_fpimm): New inserter.
* aarch64-asm.c (aarch64_ins_fpimm): New function.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_fpimm): New extractor.
* aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
(aarch64_ext_fpimm): New function.
* aarch64-dis-2.c: Regenerate.
Several of the SVE operands use the aarch64_operand fields array
to store the fields that make up the operand, rather than hard-coding
the names in the C code. This patch adds helpers for inserting and
extracting those fields.
opcodes/
* aarch64-asm.c: Include libiberty.h.
(insert_fields): New function.
(aarch64_ins_imm): Use it.
* aarch64-dis.c (extract_fields): New function.
(aarch64_ext_imm): Use it.
SVE supports logical immediate operations on 8-bit, 16-bit and 32-bit
elements, treating them as aliases of operations on 64-bit elements in
which the immediate is replicated. This patch therefore replaces the
"32-bit/64-bit" input to aarch64_logical_immediate_p with a more
general "number of bytes" input.
opcodes/
* aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
with an esize parameter.
(operand_general_constraint_met_p): Update accordingly.
Fix misindented code.
* aarch64-asm.c (aarch64_ins_limm): Update call to
aarch64_logical_immediate_p.
SVE predicate operands can appear in three forms:
1. unsuffixed: "Pn"
2. with a predication type: "Pn/[ZM]"
3. with a size suffix: "Pn.[BHSD]"
No variation is allowed: unsuffixed operands cannot have a (redundant)
suffix, and the suffixes can never be dropped. Unsuffixed Pn are used
in LDR and STR, but they are also used for Pg operands in cases where
the result is scalar and where there is therefore no choice to be made
between "merging" and "zeroing". This means that some Pg operands have
suffixes and others don't.
It would be possible to use context-sensitive parsing to handle
this difference. The tc-aarch64.c code would then raise an error
if the wrong kind of suffix is used for a particular instruction.
However, we get much more user-friendly error messages if we parse
all three forms for all SVE instructions and record the suffix as a
qualifier. The normal qualifier matching code can then report cases
where the wrong kind of suffix is used. This is a slight extension
of existing usage, which really only checks for the wrong choice of
suffix within a particular kind of suffix.
The only catch is a that a "NIL" entry in the qualifier list
specifically means "no suffix should be present" (case 1 above).
NIL isn't a wildcard here. It also means that an instruction that
requires all-NIL qualifiers can fail to match (because a suffix was
supplied when it shouldn't have been); this requires a slight change
to find_best_match.
This patch adds an F_STRICT flag to select this behaviour.
The flag will be set for all SVE instructions. The behaviour
for other instructions doesn't change.
include/
* opcode/aarch64.h (F_STRICT): New flag.
opcodes/
* aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
gas/
* config/tc-aarch64.c (find_best_match): Simplify, allowing an
instruction with all-NIL qualifiers to fail to match.
In the review of the original version of this series, Richard didn't
like the use of boolean parameters to parse_address_main. I think we
can just get rid of them and leave the callers to check the addressing
modes. As it happens, the handling of ADDR_SIMM9{,_2} already did this
for relocation operators (i.e. it used parse_address_reloc and then
rejected relocations).
The callers are already set up to reject invalid register post-indexed
addressing, so we can simply remove the accept_reg_post_index parameter
without adding any more checks. This again creates a corner case where:
.equ x2, 1
ldr w0, [x1], x2
was previously an acceptable way of writing "ldr w0, [x1], #1" but
is now rejected.
Removing the "reloc" parameter means that two cases need to check
explicitly for relocation operators.
ADDR_SIMM9_2 appers to be unused. I'll send a separate patch
to remove it.
This patch makes parse_address temporarily equivalent to
parse_address_main, but later patches in the series will need
to keep the distinction.
gas/
* config/tc-aarch64.c (parse_address_main): Remove reloc and
accept_reg_post_index parameters. Parse relocations and register
post indexes unconditionally.
(parse_address): Remove accept_reg_post_index parameter.
Update call to parse_address_main.
(parse_address_reloc): Delete.
(parse_operands): Call parse_address instead of parse_address_main.
Update existing callers of parse_address and make them check
inst.reloc.type where appropriate.
* testsuite/gas/aarch64/diagnostic.s: Add tests for relocations
in ADDR_SIMPLE, SIMD_ADDR_SIMPLE, ADDR_SIMM7 and ADDR_SIMM9 addresses.
Also test for invalid uses of post-index register addressing.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
aarch64_reg_parse_32_64 is currently used to parse address registers,
among other things. It returns two bits of information about the
register: whether it's W rather than X, and whether it's a zero register.
SVE adds addressing modes in which the base or offset can be a vector
register instead of a scalar, so a choice between W and X is no longer
enough. It's more convenient to pass the type of register around as
a qualifier instead.
As it happens, two callers of aarch64_reg_parse_32_64 already wanted
the information in the form of a qualifier, so the change feels pretty
natural even without SVE.
Also, the function took two parameters to control whether {W}SP
and (W|X)ZR should be accepted. We tend to get slightly better
error messages by accepting them regardless and getting the caller
to do the check, rather than potentially treating "xzr", "sp" etc.
as constants. This is easier to do if the function returns the
reg_entry rather than just the register number.
This does create a corner case where:
.equ sp, 1
ldr w0, [x0, sp]
was previously an acceptable way of writing "ldr w0, [x0, #1]",
but I don't think it's important to continue supporting that.
We already rejected things like:
.equ sp, 1
add x0, x1, sp
To ensure these new error messages "win" when matching against
several candidate instruction entries, we need to use the same
address-parsing code for all addresses, including ADDR_SIMPLE
and SIMD_ADDR_SIMPLE. The next patch also relies on this.
Finally, aarcch64_check_reg_type was written in a pretty
conservative way. It should always be equivalent to a single
bit test.
gas/
* config/tc-aarch64.c (REG_TYPE_R_Z, REG_TYPE_R_SP): New register
types.
(get_reg_expected_msg): Handle them and REG_TYPE_R64_SP.
(aarch64_check_reg_type): Simplify.
(aarch64_reg_parse_32_64): Return the reg_entry instead of the
register number. Return the type as a qualifier rather than an
"isreg32" boolean. Remove reject_sp, reject_rz and isregzero
parameters.
(parse_shifter_operand): Update call to aarch64_parse_32_64_reg.
Use get_reg_expected_msg.
(parse_address_main): Likewise. Use aarch64_check_reg_type.
(po_int_reg_or_fail): Replace reject_sp and reject_rz parameters
with a reg_type parameter. Update call to aarch64_parse_32_64_reg.
Use aarch64_check_reg_type to test the result.
(parse_operands): Update after the above changes. Parse ADDR_SIMPLE
addresses normally before enforcing the syntax restrictions.
* testsuite/gas/aarch64/diagnostic.s: Add tests for a post-index
zero register and for a stack pointer index.
* testsuite/gas/aarch64/diagnostic.l: Update accordingly.
Also update existing diagnostic messages after the above changes.
* testsuite/gas/aarch64/illegal-lse.l: Update the error message
for 32-bit register bases.
Since some SVE constants are no longer explicitly tied to the 8-bit
FP immediate format, it seems better to move the range checks out of
parse_aarch64_imm_float and into the callers.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Remove range check.
(parse_operands): Check the range of 8-bit FP immediates here instead.
Previously:
fmov d0, #2
would give an error:
Operand 2 should be an integer register
whereas the user probably just forgot to add the ".0" to make:
fmov d0, #2.0
This patch reports an invalid floating point constant unless the
operand is obviously a register.
The FPIMM8 handling is only relevant for SVE. Without it:
fmov z0, z1
would try to parse z1 as an integer immediate zero (the res2 path),
whereas it's more likely that the user forgot the predicate. This is
tested by the final patch.
gas/
* config/tc-aarch64.c (parse_aarch64_imm_float): Report a specific
low-severity error for registers.
(parse_operands): Report an invalid floating point constant for
if parsing an FPIMM8 fails, and if no better error has been
recorded.
* testsuite/gas/aarch64/diagnostic.s,
testsuite/gas/aarch64/diagnostic.l: Add tests for integer operands
to FMOV.
SVE has single-bit floating-point constants that don't really
have any relation to the AArch64 8-bit floating-point encoding.
(E.g. one of the constants selects between 0 and 1.) The easiest
way of representing them in the aarch64_opnd_info seemed to be
to use the IEEE float representation directly, rather than invent
some new scheme.
This patch paves the way for that by making the code that converts IEEE
doubles to IEEE floats accept any value in the range of an IEEE float,
not just zero and 8-bit floats. It leaves the range checking to the
caller (which already handles it).
gas/
* config/tc-aarch64.c (aarch64_double_precision_fmovable): Rename
to...
(can_convert_double_to_float): ...this. Accept any double-precision
value that converts to single precision without loss of precision.
(parse_aarch64_imm_float): Update accordingly.
To remove parsing ambiguities and to avoid register names being
accidentally added to the symbol table, the immediate parsing
routines reject things like:
.equ x0, 0
add v0.4s, v0.4s, x0
An explicit '#' must be used instead:
.equ x0, 0
add v0.4s, v0.4s, #x0
Of course, it wasn't possible to predict what other register
names might be added in future, so this behaviour was restricted
to the register names that were defined at the time. For backwards
compatibility, we should continue to allow things like:
.equ p0, 0
add v0.4s, v0.4s, p0
even though p0 is now an SVE register.
However, it seems reasonable to extend the x0 behaviour above to
SVE registers when parsing SVE instructions, especially since none
of the SVE immediate formats are relocatable. Doing so removes the
same parsing ambiguity for SVE instructions as the x0 behaviour removes
for base AArch64 instructions.
As a prerequisite, we then need to be able to tell the parsing routines
which registers to reject. This patch changes the interface to make
that possible, although the set of rejected registers doesn't change
at this stage.
gas/
* config/tc-aarch64.c (parse_immediate_expression): Add a
reg_type parameter.
(parse_constant_immediate): Likewise, and update calls.
(parse_aarch64_imm_float): Likewise.
(parse_big_immediate): Likewise.
(po_imm_nc_or_fail): Update accordingly, passing down a new
imm_reg_type variable.
(po_imm_of_fail): Likewise.
(parse_operands): Likewise.
Rename parse_neon_reg_list to parse_vector_reg_list and take
in the required register type as an argument. Later patches
will reuse the function for SVE registers.
gas/
* config/tc-aarch64.c (parse_neon_reg_list): Rename to...
(parse_vector_reg_list): ...this and take a register type
as input.
(parse_operands): Update accordingly.
Generalise the name of parse_neon_type_for_operand to
parse_vector_type_for_operand. Later patches will add SVEisms to it.
gas/
* config/tc-aarch64.c (parse_neon_type_for_operand): Rename to...
(parse_vector_type_for_operand): ...this.
(parse_typed_reg): Update accordingly.
Similar to the previous patch, but this time for the neon_type_el
structure.
gas/
* config/tc-aarch64.c (neon_type_el): Rename to...
(vector_type_el): ...this.
(parse_neon_type_for_operand): Update accordingly.
(parse_typed_reg): Likewise.
(aarch64_reg_parse): Likewise.
(vectype_to_qualifier): Likewise.
(parse_operands): Likewise.
(eq_neon_type_el): Likewise. Rename to...
(eq_vector_type_el): ...this.
(parse_neon_reg_list): Update accordingly.
Later patches will add SVEisms to neon_el_type, so this patch renames
it to something more generic.
gas/
* config/tc-aarch64.c (neon_el_type: Rename to...
(vector_el_type): ...this.
(neon_type_el): Update accordingly.
(parse_neon_type_for_operand): Likewise.
(vectype_to_qualifier): Likewise.
The maximum indentation needed by aarch64-gen.c grows as more
instructions are added to aarch64-tbl.h. Rather than having to
increase the indentation limit to a higher value, it seemed better
to replace it with "%*s".
opcodes/
* aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
A false return from parse_neon_operand_type had an overloaded
meaning: either the parsing failed, or there was nothing to parse
(which isn't necessarily an error). The only caller, parse_typed_reg,
would therefore not consume the suffix if it was invalid but instead
(successfully) parse the register without a suffix. It would still
leave inst.parsing_error with an error about the invalid suffix.
It seems wrong for a successful parse to leave an error message,
so this patch makes parse_typed_reg return PARSE_FAIL instead.
The patch doesn't seem to make much difference in practice.
Most possible follow-on errors use set_first_error and so the
error about the suffix tended to win despite the successful parse.
gas/
* config/tc-aarch64.c (parse_neon_operand_type): Delete.
(parse_typed_reg): Call parse_neon_type_for_operand directly.
Correct a commit 2151ccc56c ("Always organize test artifacts in a
directory hierarchy") regression causing:
Running .../gdb/testsuite/gdb.arch/mips16-thunks.exp ...
gdb compile failed, Assembler messages:
Fatal error: can't create .../gdb/testsuite/gdb.arch/mips16-thunks-inmain.o: No such file or directory
gdb compile failed, Assembler messages:
Fatal error: can't create .../gdb/testsuite/gdb.arch/mips16-thunks-main.o: No such file or directory
gdb compile failed, mips-mti-linux-gnu-gcc: error: .../gdb/testsuite/gdb.arch/mips16-thunks-inmain.o: No such file or directory
mips-mti-linux-gnu-gcc: error: .../gdb/testsuite/gdb.arch/mips16-thunks-main.o: No such file or directory
UNSUPPORTED: gdb.arch/mips16-thunks.exp: No MIPS16 support in the toolchain.
by using `standard_output_file' to construct output file names
throughout.
gdb/testsuite/
* gdb.arch/mips16-thunks.exp: Use `standard_output_file'
throughout.
In patch https://sourceware.org/ml/gdb-patches/2016-04/msg00529.html
I cleared reserved bits when reading CPSR. It makes a problem that
these bits (zero) are written back to kernel through ptrace, and it
changes the state of the processor on some recent kernel, which is
unexpected.
In this patch, I keep these reserved bits when write CPSR back to
hardware.
gdb:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* aarch32-linux-nat.c (aarch32_gp_regcache_collect): Keep
bits 20 to 23.
gdb/gdbserver:
2016-09-21 Yao Qi <yao.qi@linaro.org>
* linux-aarch32-low.c (arm_fill_gregset): Keep bits 20 to
23.
I tried building gdb with -Wduplicated-cond. This patch fixes the
simpler issue that was found.
In Python 3, "int" and "long" are synonyms, so code like:
else if (PyLong_Check (obj))
...
else if (PyInt_Check (obj))
.... will trigger this warning. The fix is to conditionalize the
PyInt_Check branches on Python 2.
Tested by rebuilding, with both version of Python, on x86-64 Fedora 24.
2016-09-20 Tom Tromey <tom@tromey.com>
* python/py-value.c (convert_value_from_python): Make PyInt_Check
conditional on Python 2.
* python/py-arch.c (archpy_disassemble): Make PyInt_Check
conditional on Python 2.
gdb/ChangeLog
2016-09-20 Edjunior Barbosa Machado <emachado@linux.vnet.ibm.com>
* rs6000-tdep.c (ppc_process_record_op31): Fix record of Store String
Word instructions.
There was a gap in the documentation of EXCLUDE_FILE that could cause
confusion to a user. When writing an input section specifier like this:
*(EXCLUDE_FILE (somefile.o) .text .text.*)
this could mean one of the following:
1. All '.text' and '.text.*' from all files except for 'somefile.o',
or
2. All '.text' from all files except 'somefile.o', and all '.text.*'
sections from all files.
It turns out that the second interpretation is correct, but the manual
does not make this clear (to me at least). Hopefully this patch makes
things clearer.
ld/ChangeLog:
* ld/ld.texinfo (Input Section Basics): Expand the description of
EXCLUDE_FILE.
Pedro pointed out a regression happening on gdb.mi/mi-exec-run.exp,
and as it turned out, this was a thinko when dealing with some events
on startup_inferior. Basically, one needs to pass 'event_ptid' to
target_mourn_inferior, but I mistakenly passed 'resume_ptid'.
This commit fixes it.
Built and regtested on BuildBot, now with fixed e-mail notifications!
gdb/ChangeLog:
2016-09-20 Sergio Durigan Junior <sergiodj@redhat.com>
* fork-inferior.c (startup_inferior): Pass 'event_ptid' instead of
'resume_ptid' to 'target_mourn_inferior'. Fix regression
introduced by my last commit.
Ref: https://sourceware.org/ml/gdb-patches/2016-09/msg00203.html
The std::{min,max} patch caused build failures when configuring GDB
with with --disable-nls and using GCC 4.1.
The reason is this bit in common/gdb_locale.h:
#ifdef ENABLE_NLS
...
#else
# define gettext(Msgid) (Msgid)
...
#endif
This causes problems if the <libintl.h> header is first included at
any point after "gdb_locale.h".
Specifically, the gettext&co declarations in libintl.h:
extern char *gettext (__const char *__msgid)
__THROW __attribute_format_arg__ (1);
end up broken after preprocessing:
extern char *(__const char *__msgid)
throw () __attribute__ ((__format_arg__ (1)));
After the std::min/std::max change to include <algorithm>, this now
happens with at least the GCC 4.1 copy of <algorithm>, which includes
<libintl.h> via <bits/stl_algobase.h>, <iosfwd>, and
<bits/c++locale.h>.
The fix is to simply remove the troublesome *gettext and *textdomain
macros, leaving only the _ and N_ ones.
gdb/ChangeLog:
2016-09-19 Pedro Alves <palves@redhat.com>
* common/gdb_locale.h [!ENABLE_NLS] (gettext, dgettext, dcgettext,
textdomain, bindtextdomain): Delete macros.
* main.c (captured_main) [!ENABLE_NLS]: Skip bintextdomain and
textdomain calls.
The code compiled with the -fpic model in SPARC uses 13-bit signed
immediate PC-relative loads to fetch entries from the GOT table. In
theory this would allow using a GOT table (.got section) containing up
to 1024 entries in elf32 or 512 entries in elf64.
However, in elf64 sparc GNU targets _GLOBAL_OFFSET_TABLE_ is always
placed at the beginning of the .got section, making it impossible to use
negative offsets. This limits the usage of -fpic to GOT tables
containing a maximum of 257 entries in elf64.
This patch activates an optimization that is already used in sparc-elf32
also in sparc-elf64, that sets _GLOBAL_OFFSET_TABLE_ to point 0x1000
into the .got section if the section size is bigger than 0x1000.
2016-09-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Allow
negative offsets to _GLOBAL_OFFSET_TABLE_ if the .got section is
bigger than 0x1000 bytes.
Symbol sorting means we can't assume that the last n symbols are
synthetic.
* nm.c (print_symbol): Remove is_synthetic param. Test sym->flags
instead.
(print_size_symbols, print_symbols): Adjust to suit, deleting
now unused synth_count param and fromsynth var.
(display_rel_file): Adjust, localizing synth_count.
This patch consolidates the API of target_mourn_inferior between GDB
and gdbserver, in my continuing efforts to make sharing the
fork_inferior function possible between both.
GDB's version of the function did not care about the inferior's ptid
being mourned, but gdbserver's needed to know this information. Since
it actually makes sense to pass the ptid as an argument, instead of
depending on a global value directly (which GDB's version did), I
decided to make the generic API to accept it. I then went on and
extended all calls being made on GDB to include a ptid argument (which
ended up being inferior_ptid most of the times, anyway), and now we
have a more sane interface.
On GDB's side, after talking to Pedro a bit about it, we decided that
just an assertion to make sure that the ptid being passed is equal to
inferior_ptid would be enough for now, on the GDB side. We can remove
the assertion and perform more operations later if we ever pass
anything different than inferior_ptid.
Regression tested on our BuildBot, everything OK.
I'd appreciate a special look at gdb/windows-nat.c's modification
because I wasn't really sure what to do there. It seemed to me that
maybe I should build a ptid out of the process information there, but
then I am almost sure the assertion on GDB's side would trigger.
gdb/ChangeLog:
2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com>
* darwin-nat.c (darwin_kill_inferior): Adjusting call to
target_mourn_inferior to include ptid_t argument.
* fork-child.c (startup_inferior): Likewise.
* gnu-nat.c (gnu_kill_inferior): Likewise.
* inf-ptrace.c (inf_ptrace_kill): Likewise.
* infrun.c (handle_inferior_event_1): Likewise.
* linux-nat.c (linux_nat_attach): Likewise.
(linux_nat_kill): Likewise.
* nto-procfs.c (interrupt_query): Likewise.
(procfs_interrupt): Likewise.
(procfs_kill_inferior): Likewise.
* procfs.c (procfs_kill_inferior): Likewise.
* record.c (record_mourn_inferior): Likewise.
* remote-sim.c (gdbsim_kill): Likewise.
* remote.c (remote_detach_1): Likewise.
(remote_kill): Likewise.
* target.c (target_mourn_inferior): Change declaration to accept
new ptid_t argument; use gdb_assert on it.
* target.h (target_mourn_inferior): Move function prototype from
here...
* target/target.h (target_mourn_inferior): ... to here. Adjust it
to accept new ptid_t argument.
* windows-nat.c (get_windows_debug_event): Adjusting call to
target_mourn_inferior to include ptid_t argument.
gdb/gdbserver/ChangeLog:
2016-09-19 Sergio Durigan Junior <sergiodj@redhat.com>
* server.c (start_inferior): Call target_mourn_inferior instead of
mourn_inferior; pass ptid_t argument to it.
(resume): Likewise.
(handle_target_event): Likewise.
* target.c (target_mourn_inferior): New function.
* target.h (mourn_inferior): Delete macro.
[...]
.../gdb/s390-linux-nat.c: In function 'void s390_prepare_to_resume(lwp_info*)':
.../gdb/s390-linux-nat.c:703:20: error: 'min' is not a member of 'std'
watch_lo_addr = std::min (watch_lo_addr, area->lo_addr);
[...]
gdb/ChangeLog:
2016-09-18 Pedro Alves <palves@redhat.com>
* s390-linux-nat.c: Include <algorithm>.
Building on a 32-bit host fails currently with errors like:
.../src/gdb/exec.c: In function ‘target_xfer_status section_table_read_available_memory(gdb_byte*, ULONGEST, ULONGEST, ULONGEST*)’:
.../src/gdb/exec.c:801:54: error: no matching function for call to ‘min(ULONGEST, long unsigned int)’
end = std::min (offset + len, r->start + r->length);
^
In file included from /usr/include/c++/5.3.1/algorithm:61:0,
from .../src/gdb/exec.c:46:
/usr/include/c++/5.3.1/bits/stl_algobase.h:195:5: note: candidate: template<class _Tp> const _Tp& std::min(const _Tp&, const _Tp&)
min(const _Tp& __a, const _Tp& __b)
^
/usr/include/c++/5.3.1/bits/stl_algobase.h:195:5: note: template argument deduction/substitution failed:
.../src/gdb/exec.c:801:54: note: deduced conflicting types for parameter ‘const _Tp’ (‘long long unsigned int’ and ‘long unsigned int’)
end = std::min (offset + len, r->start + r->length);
^
In file included from /usr/include/c++/5.3.1/algorithm:61:0,
from .../src/gdb/exec.c:46:
/usr/include/c++/5.3.1/bits/stl_algobase.h:243:5: note: candidate: template<class _Tp, class _Compare> const _Tp& std::min(const _Tp&, const _Tp&, _Compare)
min(const _Tp& __a, const _Tp& __b, _Compare __comp)
^
The problem is that the std::min/std::max function templates use the
same type for both parameters. When the argument types are different,
the compiler can't automatically deduce which template specialization
to pick from the arguments' types.
Fix that by specifying the specialization we want explicitly.
gdb/ChangeLog:
2016-09-18 Pedro Alves <palves@redhat.com>
* breakpoint.c (hardware_watchpoint_inserted_in_range): Explicitly
specify the std:min/std::max specialization.
* exec.c (section_table_read_available_memory): Likewise.
* remote.c (remote_read_qxfer): Likewise.
* target.c (simple_verify_memory): Likewise.
These changes were already accepted upstream in Readline,
but GDB did not yet import a newer Readline version.
readline/Changelog.gdb:
* util.c: Include rlshell.h.
(_rl_tropen) [_WIN32 && !__CYGWIN__]: Open the trace file in the
user's temporary directory.
* tcap.h [HAVE_NCURSES_TERMCAP_H]: Include ncurses/termcap.h.
* input.c (w32_isatty) [_WIN32 && !__CYGWIN__]: New function, to
replace isatty that is not reliable enough on MS-Windows.
(isatty) [_WIN32 && !__CYGWIN__]: Redirect to w32_isatty.
(rl_getc): Call _getch, not getch, which could be an ncurses
function when linked with ncurses, in which case getch will return
EOF for any keystroke, because there's no curses window.
* tilde.c (tilde_expand_word) [_WIN32]:
* histfile.c (history_filename) [_WIN32]: Windows-specific
environment variable to replace HOME if that is undefined.
* funmap.c (default_funmap): Compile rl_paste_from_clipboard on
all Windows platforms, not just Cygwin.
* readline.h (rl_paste_from_clipboard): Include declaration for
all Windows platforms.
* display.c (insert_some_chars, delete_chars): Don't use the
MinGW-specific code if linked with ncurses.
* configure.in:
* config.h.in: Support ncurses/termcap.h. The configure script
was updated accordingly.
* complete.c [_WIN32 && !__CYGWIN__]: Initialize
_rl_completion_case_fold to 1.
(printable_part, rl_filename_completion_function)
[_WIN32 && !__CYGWIN__]: Handle the drive letter.
Make a globally available cleanup from a pre-existing one in infrun.c.
This is used in a following patch.
gdb/ChangeLog:
* infrun.c (restore_current_uiout_cleanup): Move to ui-out.c.
(print_stop_event): Use make_cleanup_restore_current_uiout.
* python/python.c (execute_gdb_command): Likewise.
* ui-out.c (restore_current_uiout_cleanup): Move from infrun.c.
(make_cleanup_restore_current_uiout): New function definition.
* ui-out.h (make_cleanup_restore_current_uiout): New function
declaration.
* utils.c (do_restore_ui_out): Remove.
(make_cleanup_restore_ui_out): Remove.
* utils.h (make_cleanup_restore_ui_out): Remove.
Add the function lwp_is_stepping which indicates whether the given LWP
is currently single-stepping. This is a common interface, usable from
native GDB as well as from gdbserver.
gdb/gdbserver/ChangeLog:
* linux-low.c (lwp_is_stepping): New function.
gdb/ChangeLog:
* nat/linux-nat.h (lwp_is_stepping): New declaration.
* linux-nat.c (lwp_is_stepping): New function.
Implement a new function for dumping the S390 "debug
registers" (actually, the PER info) and invoke it at appropriate places.
Respect the variable show_debug_regs and make it settable by the user.
gdb/ChangeLog:
* s390-linux-nat.c (gdbcmd.h): New include.
(s390_show_debug_regs): New function.
(s390_stopped_by_watchpoint): Call it, if show_debug_regs is set.
(s390_prepare_to_resume): Likewise.
(_initialize_s390_nat): Register the command "maint set
show-debug-regs".
Support different sets of watchpoints in multiple inferiors.
gdb/ChangeLog:
* s390-linux-nat.c (watch_areas): Remove variable. Replace by a
member of...
(struct s390_debug_reg_state): ...this. New struct.
(struct s390_process_info): New struct.
(s390_process_list): New variable.
(s390_find_process_pid, s390_add_process, s390_process_info_get)
(s390_get_debug_reg_state): New functions.
(s390_stopped_by_watchpoint): Now access the watch_areas VEC via
s390_get_debug_reg_state.
(s390_prepare_to_resume): Likewise.
(s390_insert_watchpoint): Likewise.
(s390_remove_watchpoint): Likewise.
(s390_forget_process, s390_linux_new_fork): New linux_nat target
methods.
(_initialize_s390_nat): Register them.
For S390, the list of active watchpoints is maintained in a list based
at "watch_base". This refactors the list to a vector "watch_areas".
gdb/ChangeLog:
* s390-linux-nat.c (s390_watch_area): New typedef. Define a VEC.
(watch_base): Remove variable.
(watch_areas): New variable.
(s390_stopped_by_watchpoint): Transform operations on the
watch_base list to equivalent operations on the watch_areas VEC.
(s390_prepare_to_resume): Likewise.
(s390_insert_watchpoint): Likewise.
(s390_remove_watchpoint): Likewise.
When using the lwp_info structure, avoid accessing its members directly,
and use the advertised function interfaces instead. This is according
to the instructions in linux-nat.h and prepares for making some of the
code common between gdb and gdbserver.
gdb/ChangeLog:
* s390-linux-nat.c (s390_prepare_to_resume): Use advertised lwp
functions instead of accessing lwp_info structure members.
(s390_mark_per_info_changed): New function.
(s390_new_thread): Use it.
(s390_refresh_per_info_cb): New function.
(s390_refresh_per_info): Remove parameter. Refresh all lwps of
the current process.
(s390_insert_watchpoint): Adjust call to s390_refresh_per_info.
(s390_remove_watchpoint): Likewise.
gcc-6.2.1-1.fc26.x86_64
gdb compile failed, /home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:40:10: error: expected primary-expression before 'int'
decltype(int x)
^~~
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:40:10: error: expected ')' before 'int'
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:40:1: error: expected unqualified-id before 'decltype'
decltype(int x)
^~~~~~~~
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc: In function 'int main(int, char**)':
/home/jkratoch/redhat/gdb-clean/gdb/testsuite/gdb.cp/casts.cc:59:14: error: expected primary-expression before 'decltype'
double y = decltype(2);
^~~~~~~~
'decltype' is a registered keyword since C++11 which is now a default for GCC.
On Thu, 15 Sep 2016 14:06:56 +0200, Pedro Alves wrote:
Seems to be exercising the FLAG_SHADOW bits:
...
{"__typeof__", TYPEOF, OP_TYPEOF, 0 },
{"__typeof", TYPEOF, OP_TYPEOF, 0 },
{"typeof", TYPEOF, OP_TYPEOF, FLAG_SHADOW },
{"__decltype", DECLTYPE, OP_DECLTYPE, FLAG_CXX },
{"decltype", DECLTYPE, OP_DECLTYPE, FLAG_CXX | FLAG_SHADOW },
...
/* This is used to associate some attributes with a token. */
enum token_flag
{
...
/* If this bit is set, the token is conditional: if there is a
symbol of the same name, then the token is a symbol; otherwise,
the token is a keyword. */
FLAG_SHADOW = 2
};
So perhaps a better fix is to move that particular test to a
separate testcase that force-compiles with -std=c++03.
gdb/testsuite/ChangeLog
2016-09-16 Jan Kratochvil <jan.kratochvil@redhat.com>
* gdb.cp/casts.cc (decltype): Move it ...
(main): ... with its call to ...
* gdb.cp/casts03.cc: ... a new file.
* gdb.cp/casts.exp: Add new file casts03.cc, move decltype test to it.
Richard Sandiford
Maciej W. Rozycki
Yao Qi
GDB Administrator
Tom Tromey
Edjunior Barbosa Machado
Andrew Burgess
Sergio Durigan Junior
Pedro Alves
Jose E. Marchesi
Alan Modra
Eli Zaretskii
Simon Marchi
Andreas Arnez
Jan Kratochvil