Replace a global `mips_opts.isa' reference in `is_opcode_valid' and use
a local copy just made in `isa'. No functional change.
gas/
* config/tc-mips.c (is_opcode_valid): Use local `isa'
consistently.
Adds a new option, defaulting to off, that allows a group of stubs to
serve multiple output sections. Prior to this patch powerpc gold
allowed this unconditionally, which is a little unsafe with clever
code that discards/reuses sections at runtime.
* options.h (--stub-group-multi): New PowerPC option.
* powerpc.cc (Stub_control): Add multi_os_ var and param
to constructor. Sort start_ var later. Comment State.
(Stub_control::can_add_to_stub_group): Heed multi_os_.
(Target_powerpc::group_sections): Update.
Gold attaches stubs to an existing section in contrast to ld.bfd which
inserts a new section for stubs. If we want stubs before branches,
then the stubs must be added to the previous section. Adding to the
previous section is a disaster if there is a large gap between the
previous section and the group.
PR gold/20878
* powerpc.cc (Stub_control): Replace stubs_always_before_branch_
with stubs_always_after_branch_, group_end_addr_ with
group_start_addr_.
(Stub_control::can_add_to_stub_group): Rewrite to suit scanning
sections by increasing address.
(Target_powerpc::group_sections): Scan that way. Delete corner
case.
* options.h (--stub-group-size): Update help string.
Some more debug output, and a little hardening.
* powerpc.cc (Stub_table_owner): Provide constructor.
(Powerpc_relobj::set_stub_table): Resize fill with -1.
(Target_powerpc::Branch_info::make_stub): Provide target debug
output on returning false.
In the case where we switch to a non-running inferior, we do a
"find_inferior_id (num)", although we did the same call right before.
gdb/ChangeLog:
* inferior.c (inferior_command): Remove duplicate
find_inferior_id call.
PR binutils/20930
* objcopy.c (mark_symbols_used_in_relocations): Check for a null
symbol pointer pointer before attempting to mark the symbol as
kept.
This patch adds asserts where the value's lval must be lval_register.
This triggers an error in frame_register_unwind because VALUE_REGNUM
is used but value's lval is not lval_register.
This also reveals a design issue in frame_register_unwind, that is
arguments addrp and realnump are mutually exclusive, we either use
addrp (for lval_memory), or use realnump (for lval_register). This
can be done in a separate patch.
gdb:
2016-12-06 Yao Qi <yao.qi@linaro.org>
* frame.c (frame_register_unwind): Set *realnump if *lvalp is
lval_register.
* value.c (deprecated_value_next_frame_id_hack): Assert
value->lval is lval_register.
(deprecated_value_regnum_hack): Likewise.
Recognize power9 and a few other insns from older machines. Fixes
linker complaints like "toc optimization is not supported for
0xf4090002 instruction". 0xf4090002 is stxsd v0,0(r9)
bfd/
* elf64-ppc.c (ok_lo_toc_insn): Add r_type param. Recognize
lq,lfq,lxv,lxsd,lxssp,lfdp,stq,stfq,stxv,stxsd,stxssp,stfdp.
Don't match lmd and stmd.
ld/
* testsuite/ld-powerpc/tocopt7.s,
* testsuite/ld-powerpc/tocopt7.out,
* testsuite/ld-powerpc/tocopt7.d: New test.
* testsuite/ld-powerpc/tocopt8.s,
* testsuite/ld-powerpc/tocopt8.d: New test.
* testsuite/ld-powerpc/powerpc.exp: Run them.
Add support for VCMLA and VCADD advanced SIMD complex number instructions.
The command line option is -march=armv8.3-a+fp16+simd for enabling all
instructions.
In arm-dis.c the formatting syntax was abused a bit to select between
0 vs 90 or 180 vs 270 or 90 vs 270 based on a bit value instead of
duplicating entries in the opcode table.
gas/
* config/tc-arm.c (do_vcmla, do_vcadd): Define.
(neon_scalar_for_vcmla): Define.
(enum operand_parse_code): Add OP_IROT1 and OP_IROT2.
(NEON_ENC_TAB): Add DDSI and QQSI variants.
(insns): Add vcmla and vcadd.
* testsuite/gas/arm/armv8_3-a-simd.d: New.
* testsuite/gas/arm/armv8_3-a-simd.s: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.d: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.l: New.
* testsuite/gas/arm/armv8_3-a-simd-bad.s: New.
opcodes/
* arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
(print_insn_coprocessor): Add 'V' format for neon D or Q regs.
ARMv8.3 is an architectural extension of ARMv8. Add the
feature macro and -march=armv8.3-a gas command line option
for the ARM target.
https://community.arm.com/groups/processors/blog/2016/10/27/armv8-a-architecture-2016-additions
gas/
* config/tc-arm.c (arm_archs): Add "armv8.3-a".
* doc/c-arm.texi (-march): Add "armv8.3-a".
include/
* opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New.
(ARM_ARCH_V8_3A): New.
bfd/ChangeLog:
2016-12-05 Alyssa Milburn <amilburn@zall.org>
* elfxx-sparc.c: Do not stop processing relocations after
partially relaxing a call with WDISP30.
ld/ChangeLog:
2016-12-05 Alyssa Milburn <amilburn@zall.org>
* testsuite/ld-sparc/wdispcall.s: New file.
* testsuite/ld-sparc/wdispcall.dd: Likewise.
* testsuite/ld-sparc/sparc.exp: Run new test.
Lots of fixes for the compatibility code that handles linking of
-mcall-aixdesc code (or that generated by 12 year old gcc) with
current ELFv1 ABI code.
1) A reference to a dot-symbol in an object file wasn't satisfied by a
function descriptor in later object files.
2) The as-needed code had bit-rotted; Shared libs now need a strong
reference to be counted as needed.
3) --gc-sections involving dot-symbols was broken, needing
func_desc_adjust to be run early and lots of other fixes.
bfd/
* elf64-ppc.c (struct ppc_link_hash_entry): Delete "was_undefined".
(struct ppc_link_hash_table): Delete "twiddled_syms". Add
"need_func_desc_adj".
(lookup_fdh): Link direct fdh sym via oh field and set flags.
(make_fdh): Make strong and weak undefined function descriptor
symbols.
(ppc64_elf_merge_symbol): New function.
(elf_backend_merge_symbol): Define.
(ppc64_elf_archive_symbol_lookup): Don't test undefweak for fake
function descriptors.
(add_symbol_adjust): Don't twiddle symbols to undefweak.
Propagate more ref flags to function descriptor symbol. Make
some function descriptor symbols dynamic.
(ppc64_elf_before_check_relocs): Only run add_symbol_adjust for
ELFv1. Set need_func_desc_adj. Don't fix undefs list.
(ppc64_elf_check_relocs): Set non_ir_ref for descriptors.
Don't call lookup_fdh here.
(ppc64_elf_gc_sections): New function.
(bfd_elf64_bfd_gc_sections): Define.
(ppc64_elf_gc_mark_hook): Mark descriptor.
(func_desc_adjust): Don't make fake function descriptor syms strong
here. Exit earlier on non-dotsyms. Take note of elf.dynamic
flag when deciding whether a dynamic function descriptor might
be needed. Transfer elf.dynamic and set elf.needs_plt. Move
plt regardless of visibility. Make descriptor dynamic if
entry sym is dynamic, not for other cases.
(ppc64_elf_func_desc_adjust): Don't run func_desc_adjust if
already done.
(ppc64_elf_edit_opd): Use oh field rather than lookup_fdh.
(ppc64_elf_size_stubs): Likewise.
(ppc_build_one_stub): Don't clear was_undefined. Only set sym
undefweak if stub symbol is defined.
(undo_symbol_twiddle, ppc64_elf_restore_symbols): Delete.
* elf64-ppc.h (ppc64_elf_restore_symbols): Don't declare.
ld/
* emultempl/ppc64elf.em (gld${EMULATION_NAME}_finish): Don't call
ppc64_elf_restore_symbols.
* testsuite/ld-powerpc/dotsym1.d: New.
* testsuite/ld-powerpc/dotsym2.d: New.
* testsuite/ld-powerpc/dotsym3.d: New.
* testsuite/ld-powerpc/dotsym4.d: New.
* testsuite/ld-powerpc/dotsymref.s: New.
* testsuite/ld-powerpc/nodotsym.s: New.
* testsuite/ld-powerpc/powerpc.exp: Run new tests.
GDB Administrator
Thomas Schwinge
Maciej W. Rozycki
Nick Clifton
Alan Modra
Simon Marchi
Yao Qi
DJ Delorie
Cary Coutant
Jose E. Marchesi
Szabolcs Nagy
Claudiu Zissulescu
Alyssa Milburn
Jim Wilson