Fixes an error reported by Tristan and which can be evidenced by
doing:
% powerpc-elf-gdb
(gdb) target sim --sysroot=var
Invalid option: --sysroot=/var
[...]
sim/ppc/ChangeLog:
* psim.c (psim_options): Fix length of comparison when checking
for --sysroot= option.
This patch improves the error message when an invalid option is
detected, by also printing the option that actually caused the error.
For instance, from GDB:
(gdb) target sim --hello
Invalid option: --hello
Usage:
[...]
We also added the usage after an invalid long-name option (Eg: --hello)
to be in line with what's being done for all other invalid options
being detected.
sim/ppc/ChangeLog:
* psim.c (psim_options): Add option that cause the error
in invalid-option error messages. Print the usage when
detecting an invalid long-name option.
There was a recent change that cuased the "target sim" command
to add a --sysroot option to the argument vector passed down to
the simulator. This caused a failure in the powerpc simulator,
as it did not recognize it. This patch fixes the problem by adding
support for the --sysroot option (it ignores it).
sim/ppc/ChangeLog:
* psim.c (psim_options): Accept and ignore `--sysroot=...'.
Now that the common sim testsuite code supports .S and .c files, we
can import the Blackfin testsuite. There are about ~800 tests here,
so I'm only attaching a compressed patch of them. Other than adding
files to sim/testsuite/sim/bfin/, the sim/configure.tgt file was
updated to mark Blackfin as having a testsuite, and sim/configure
regenerated.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The BF537 family glues a bunch of peripherals into single interrupt lines
that run into the SIC. To model this same behavior in the sim, we need to
use the glue-or device, and in order to use that, we need to tweak things
a bit in the mach code to allow declaring of these new devices.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The machs.c file is the best place for holding cpu-specific details, so
restructure the way the SIC manages its ports to do just that. Now the
SIC's have a standard set of input pins and the different line routing
from peripherals is kept in the device tree only. This better models
the hardware where the SIC doesn't care about the exact peripheral that
is sending it stuff, just which input pin it gets it on.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This patch fixes a build failure at link time due to
sim_complete_command being undefined. There was a recent change
that added this function to all the ports that do not use the
common/ subdir. But somehow, the erc32 port got missed.
sim/erc32/ChangeLog:
* interf.c (sim_complete_command): New stub function.
The current --sysroot parsing attempts to keep from leaking memory by
treating the empty string specially (sine this is the initial value),
but it ends up leaking memory when the arg is an empty string. So if
someone uses --sysroot "", the old value is leaked, as is the new one.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
A semi-recent change which regenerated nltvals.def somehow missed all of
the Blackfin syscalls. So regenerate against the latest tree to get them
back.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that the common code supports the syscall trace level, change the
Blackfin code from using the event level to the syscall level.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
It's useful to be able to trace just the system calls the simulated
program is calling, so add a new --trace-syscall option for ports to
leverage if they choose.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Pull the model data (register addresses/sizes) out of the different model
files and into the machs.h header. The models themselves don't care about
where they're mapped, only the mach code does. This allows us to keep the
model headers from being included in the mach code which can cause issues
with model-specific names colliding. Such as when a newer device model is
created, but with incompatible register names/layouts.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some Blackfin parts tie a bunch of interrupt lines into a single OR
gate before feeding the result into the SIC. The glue-or device in
the sim provides a nice way of modeling this exact behavior. At the
moment though, it requires the device to be mapped into the address
space so that things could write to it directly. This is not needed
for the Blackfin usage, so make it optional. Now the glue devices
can be used to simply tie interrupt lines together.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The glue device has a bunch of "todos" for the misc bitwise devices.
So implement two for fun -- the glue-or and glue-xor.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Rather than requiring all sim tests to be preprocessed .s files, add
support for .S and .c files so we can easily write code using a higher
level language like C.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The UART has a LOOP_ENA bit in its MCR register where writes to the THR
go to the RBR. Implement support for this mode.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
A few bits in the newer UART LSR register are not sticky, so make sure
we clear them when returning updated status rather than leaving them
always set.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Make all of the pins bidirectional, and support sending signals when
software drives the pins as outputs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When the mask a/b MMRs are written, the output signal might change levels
(as pins are [un]masked), so make sure we update the output level.
Further, make sure we handle edge ints correctly by first sending a high
signal followed by a low signal.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
For the ports that don't use the common/ subdir, we need to add stub funcs
to them to avoid build failures with gdb and command completion. These do
not implement the actual completion functionality ... any port that wants
that can either convert to the common/ subdir, or fill out the function on
their own time.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
A bunch of 32bit insns were not using the store buffer, so when they were
used in parallel insns, they would incorrectly clobber a register early.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
For now, only the sub-command name is completed. No support yet for
completing options to that command. But even this is a huge step as
currently, nothing is completed, and the basic "help sim" is fairly
obtuse as to what exactly the "sim" command accepts.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
When most video related insns are used in parallel with Ireg loads, the
DISALGNEXCPT insn behavior is implicitly in effect.
Reported-by: Anton Shokurov <shokurov.anton.v@yandex.ru>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The SIC latches ints from peripherals to the CEC, but the peripherals
need to be able to tell the SIC when to stop. So use the incoming level
to figure out when to set the int bits and when to clear it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This doesn't currently generate any interrupts (as there doesn't appear
to be any documentation to *when* it would even do so), but since the
HRM does say an interrupt line exists between the OTP and the SIC, add
one for completeness sake. This will make a follow up patch easier.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This simulates a CFI flash. Its pretty configurable via the device
tree. For now, only basic read/write/erase operations are supported
for the Intel command set, but it's easy enough to extend support.
It's certainly enough to trick Das U-Boot into using it for probing,
reading, writing, and erasing.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current implementation attempts to handle the 16bit sign extension
itself. Unfortunately, it gets it right in some cases. So rather than
fix that logic, just drop it in favor of using 16bit signed casts. Now
gcc will take care of getting the logic right.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved. So add handling for this edge
case to match the hardware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The 16bit add/sub insns missed setting the VS bit in ASTAT whenever the
V bit was also set.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Makes it a lot easier to find out what's going on with interrupt lines
if the ports have tracing output.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
We need the DIR bit cleared, not set, in order for the pin to be treated
as an input.
When looking up the data value, we need to shift the "level" value over by
"my_port" rather than "bit" as the latter has already been shifted over.
We also should normalize the "level" coming in from the outside worlds to
the set of {0,1} since those are the only values that matter to GPIOs.
We need the BOTH bit set, not cleared, in order for the pin to trigger
on both edges.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The clear/set/toggle MMRs aren't backed by "real" data; they implicitly
perform bit operations on the associated data register. So when we go
to process writes to them, we need to adjust the pointer accordingly so
that the actual backing data is modified.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Mike Frysinger
Joel Brobecker
Hans-Peter Nilsson
Joseph Myers