Commit Graph

87459 Commits

Author SHA1 Message Date
Alan Modra f7433f011e objcopy add-symbol uninitialised struct
* objcopy.c: Formatting, whitespace throughout.
	(copy_main): Init newsym->othersym.
	(parse_symflags): Make len a size_t.  Adjust uses.
2016-05-31 20:35:01 +09:30
Alan Modra c12969f8b5 Don't needlessly clear xmemdup allocated memory.
* xmemdup.c (xmemdup): Use xmalloc rather than xcalloc.
2016-05-31 20:34:47 +09:30
GDB Administrator c7022704e9 Automatic date update in version.in 2016-05-31 00:00:16 +00:00
Marcin Kościelnicki 40d85a7f9c gold/s390: Fix compilation on gcc 4.4
gold/ChangeLog:

	PR/19960
	* s390.cc (Target_s390::ss_code_st_r14): Removed.
	(Target_s390::ss_code_l_r14): Removed.
	(Target_s390::ss_code_ear): Removed.
	(Target_s390::ss_code_c): Removed.
	(Target_s390::ss_match_st_r14): New function.
	(Target_s390::ss_match_l_r14): New function.
	(Target_s390::ss_match_mcount): Call ss_match_{l,st}_r14 instead
	of matching code directly.
	(Target_s390::ss_match_ear): New function.
	(Target_s390::ss_match_c): New function.
	(Target_s390::do_calls_non_split): Call ss_match_{ear,c} instead
	of matching code directly.
2016-05-30 19:06:45 +02:00
Antoine Tremblay 825c8ef28f Add tests for 64bit values in trace-condition.exp
This patch adds tests for emit operations with 64 bit values. It takes
special care to avoid mistakes that one could make on a 32bit architecture
using 64bit values.

gdb/testsuite/ChangeLog:

	* gdb.trace/trace-condition.exp: Add 64bit tests.
2016-05-30 12:51:13 -04:00
Antoine Tremblay 2320162a62 Add variable length tests for emit_ref in trace-condition.exp
This patch add variable length tests for emit_ref by reading the variable
passed as argument of 8 to 64 bit.

gdb/testsuite/ChangeLog:

	* gdb.trace/trace-condition.c (marker): Adapt signature to 8 to 64
	bits types.
	(main): Adapt to 8 to 64 bits types.
	* gdb.trace/trace-condition.exp: Add new tests.
2016-05-30 12:51:13 -04:00
Antoine Tremblay a781823347 Add emit_less_unsigned test in trace-condition.exp
This patch adds coverage for emit_less_unsigned.

gdb/testsuite/ChangeLog:

	* gdb.trace/trace-condition.exp: Add emit_less_unsigned test.
2016-05-30 12:51:13 -04:00
Antoine Tremblay 0d33646690 Move trace conditions tests from ftrace.exp to trace-condition.exp
This patch moves conditional tests that were done in ftrace.exp to
trace-condition.exp.

Note that emit_ref is now tested by the anarg local variable there is no
need to test the register directly.

All emit calls have been tested using asserts before / after the move, to
ensure that the tests cover the same functions.

Note that these function were not covered before and are still not:
emit_gt_goto, emit_lt_goto, emit_pop, emit_unsigned_less.

gdb/testsuite/ChangeLog:

	* gdb.trace/ftrace.exp (test_ftrace_condition): Remove.
	Move condition tests...
	* gdb.trace/trace-condition.exp: Here.
2016-05-30 12:51:13 -04:00
Antoine Tremblay 7faeb45ae3 Add counter-cases for trace-condition.exp tests
In trace-condition.exp, tests are done by doing a conditional tracepoint
and validating that the trace contains all the frames that could be
collected if that condition is true.

E.g. test_tracepoints $trace_command "21 + 21 == 42" 10

This will always return true and collect the 10 frames possible to collect
with the test program.

However, if the condition evaluation is broken such that the condition is
unconditional we will not notice this problem.

This patch adds counter-cases to such conditions like so:

$trace_command "21 + 11 == 42" 0

This way such a problem would be noticed.

gdb/testsuite/ChangeLog:

	* gdb.trace/trace-condition.exp: Add counter-case tests.
2016-05-30 12:51:13 -04:00
Jan Kratochvil e385593eef PR 15231: import bare DW_TAG_lexical_block
Local variables in lambdas are not accessible
https://sourceware.org/bugzilla/show_bug.cgi?id=15231

GDB: read_lexical_block_scope
  /* Ignore blocks with missing or invalid low and high pc attributes.  */
[...]
  if (!dwarf2_get_pc_bounds (die, &lowpc, &highpc, cu, NULL))
    return;

But sometimes there is:

FAIL: gcc-5.3.1-6.fc23.x86_64
 <2><92>: Abbrev Number: 11 (DW_TAG_lexical_block)
 <3><9c>: Abbrev Number: 13 (DW_TAG_structure_type)
    <9d>   DW_AT_name        : (indirect string, offset: 0x3c): <lambda()>
    [...]

Where DW_TAG_lexical_block has no attributes.  Such whole subtree is currently
dropped by GDB while I think it should just import all its children DIEs.

It even XFAIL->XPASSes gdb.ada/out_of_line_in_inlined.exp:
	commit 0fa7fe506c
	Author: Joel Brobecker <brobecker@adacore.com>
	    out of line functions nested inside inline functions.
So I have removed that xfail.

gdb/ChangeLog
2016-05-30  Jan Kratochvil  <jan.kratochvil@redhat.com>

	PR c++/15231
	* dwarf2read.c (enum pc_bounds_kind): Add PC_BOUNDS_INVALID.
	(process_psymtab_comp_unit_reader, read_func_scope): Adjust callers.
	(read_lexical_block_scope): Import DIEs from bare DW_TAG_lexical_block.
	(read_call_site_scope): Adjust callers.
	(dwarf2_get_pc_bounds): Implement pc_bounds_invalid.
	(dwarf2_get_subprogram_pc_bounds, get_scope_pc_bounds): Adjust callers.

gdb/testsuite/ChangeLog
2016-05-30  Jan Kratochvil  <jan.kratochvil@redhat.com>

	PR c++/15231
	* gdb.ada/out_of_line_in_inlined.exp: Remove xfails.
	* gdb.dwarf2/dw2-lexical-block-bare.exp: New file.
2016-05-30 14:14:43 +02:00
Jan Kratochvil 3a2b436ae9 Code cleanup: dwarf2_get_pc_bounds: -1/0/+1 -> enum
Make the code (maybe) more readable + primarily prepare it for [patch 2/2]
enum extension.

This change should have no code change impact.

gdb/ChangeLog
2016-05-30  Jan Kratochvil  <jan.kratochvil@redhat.com>

	Code cleanup: dwarf2_get_pc_bounds: -1/0/+1 -> enum
	* dwarf2read.c (enum pc_bounds_kind) New.
	(dwarf2_get_pc_bounds): Use it in the declaration.
	(process_psymtab_comp_unit_reader): Adjust caller.  Rename has_pc_info
	to cu_bounds_kind.
	(read_func_scope, read_lexical_block_scope, read_call_site_scope):
	Adjust callers.
	(dwarf2_get_pc_bounds): Use enum pc_bounds_kind in the definition.
	(dwarf2_get_subprogram_pc_bounds, get_scope_pc_bounds): Adjust callers.
2016-05-30 14:11:43 +02:00
GDB Administrator 2adb06b571 Automatic date update in version.in 2016-05-30 00:00:15 +00:00
Jan Kratochvil aab3c527d7 NEWS: QCatchSyscalls: simplify
Standardize the QCatchSyscalls NEWS entry.

gdb/ChangeLog
2016-05-29  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* NEWS (QCatchSyscalls): Remove the parameter.  Include ...
	(QCatchSyscalls:1 in qSupported) ... this separate entry which got
	deleted.
2016-05-29 20:45:42 +02:00
Jan Kratochvil c64e0f6165 NEWS: Remove empty line.
gdb/ChangeLog
2016-05-29  Jan Kratochvil  <jan.kratochvil@redhat.com>

	* NEWS (N stop reply): Remove empty line.
2016-05-29 18:42:15 +02:00
H.J. Lu 0cbd0046fa Add missing ChangeLog entries 2016-05-29 08:26:43 -07:00
H.J. Lu 144b71e2a8 Add .noavx512XX directives to x86 assembler
Add .noavx512f, .noavx512cd, .noavx512er, .noavx512pf, .noavx512dq,
.noavx512bw, .noavx512vl, .noavx512ifma, .noavx512vbmi directives to x86
assembler.

gas/

	PR gas/20145
	* config/tc-i386.c (cpu_noarch): Add noavx512f, noavx512cd,
	noavx512er, noavx512pf, noavx512dq, noavx512bw, noavx512vl,
	noavx512ifma and noavx512vbmi.
	* doc/c-i386.texi: Mention noavx512f, noavx512cd, noavx512er,
	noavx512pf, noavx512dq, noavx512bw, noavx512vl, noavx512ifma
	and noavx512vbmi.
	* testsuite/gas/i386/i386.exp: Run noavx512-1 and noavx512-2.
	* testsuite/gas/i386/noavx512-1.l: New file.
	* testsuite/gas/i386/noavx512-1.s: Likewise.
	* testsuite/gas/i386/noavx512-2.l: Likewise.
	* testsuite/gas/i386/noavx512-2.s: Likewise.

opcodes/

	PR gas/20145
	* i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
	CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
	CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
	CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
	CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
	* i386-init.h: Regenerated.
2016-05-29 07:56:23 -07:00
GDB Administrator bb69990f86 Automatic date update in version.in 2016-05-29 00:00:19 +00:00
Alan Modra 0597bdc443 Add dependencies to configure rule
* Makefile.tpl (configure): Depend on m4 files included.
	* Makefile.in: Regenerate.
2016-05-28 22:36:04 +09:30
Maciej W. Rozycki 99aefae681 MIPS/BFD: Correctly handle `bfd_reloc_outofrange' with branches
Fix internal errors like:

ld: BFD (GNU Binutils) 2.26.51.20160526 internal error, aborting at .../bfd/elfxx-mips.c:10278 in _bfd_mips_elf_relocate_section

ld: Please report this bug.

triggered by the `bfd_reloc_outofrange' condition on branch relocations.

	bfd/
	* elfxx-mips.c (b_reloc_p): New function.
	(_bfd_mips_elf_relocate_section) <bfd_reloc_outofrange>: Handle
	branch relocations.

	ld/
	* testsuite/ld-mips-elf/unaligned-branch.d: New test.
	* testsuite/ld-mips-elf/unaligned-branch.s: New test source.
	* testsuite/ld-mips-elf/unaligned-text.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2016-05-28 10:59:45 +01:00
Maciej W. Rozycki 3b4412a041 MIPS/LD/testsuite: Rename `unaligned-syms' to `unaligned-data'
ld/
	* testsuite/ld-mips-elf/unaligned-syms.s: Rename to...
	* testsuite/ld-mips-elf/unaligned-data.s: ... this.
	* testsuite/ld-mips-elf/unaligned-ldpc-0.d: Adjust accordingly.
	* testsuite/ld-mips-elf/unaligned-ldpc-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-lwpc-0.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-lwpc-1.d: Likewise.
2016-05-28 10:38:02 +01:00
Maciej W. Rozycki 7743482350 MIPS/BFD: Enable local R_MIPS_26 overflow detection
The original MIPS SVR4 psABI defines the calculation for the R_MIPS_26
relocation in a complex way, as follows[1]:

Name        Value Field    Symbol   Calculation
R_MIPS_26     4   T-targ26 local    (((A << 2) | \
                                      (P & 0xf0000000)) + S) >> 2
              4   T-targ26 external (sign-extend(A << 2) + S) >> 2

This is further clarified, by correcting typos (already applied in the
excerpt above) in the 64-bit psABI extension[2].  A note is included in
both documents to specify that for the purpose of relocation processing
a local symbol is one with binding STB_LOCAL and type STT_SECTION, and
otherwise, a symbol is external.

We have both calculations implemented for the R_MIPS_26 relocation, and
by extension also for the R_MIPS16_26 and R_MICROMIPS_26_S1 relocations,
from now on collectively called jump relocations.  However our code uses
a different condition to tell local and external symbols apart, that is
it only checks for the STB_LOCAL binding and ignores the symbol type,
however for REL relocations only.  The external calculation is used for
all RELA jump relocations.

In reality the difference matters for jump relocations referring local
MIPS16 and, as from recent commit 44d3da2338 ("MIPS/GAS: Treat local
jump relocs the same no matter if REL or RELA"), also local microMIPS
symbols.  Such relocations are not converted to refer to corresponding
section symbols instead and retain the original local symbol reference.

It can be inferred from the relocation calculation definitions that the
addend is effectively unsigned for the local case and explicitly signed
for the external case.  With the REL relocation format it makes sense
given the limited range provided for by the field being relocated: the
use of an unsigned addend expands the range by one bit for the local
case, because a negative offset from a section symbol makes no sense,
and any usable negative offset from the original local symbol will have
worked out positive if converted to a section-relative reference.  In
the external case a signed addend gives more flexibility as offsets both
negative and positive can be used with a symbol.  Any such offsets will
typically have a small value.

The inclusion of the (P & 0xf0000000) component, ORed in the calculation
in the local case, seems questionable as bits 31:28 are not included in
the relocatable field and are masked out as the relocation is applied.
Their value is therefore irrelevant for output processing, the relocated
field ends up the same regardless of their value.  They could be used
for overflow detection, however this is precluded by adding them to bits
31:28 of the symbol referred, as the sum will not correspond to the
value calculated by the processor at run time whenever bits 31:28 of the
symbol referred are not all zeros, even though it is valid as long they
are the same as bits 31:28 of P.

We deal with this problem by ignoring any overflow resulting from the
local calculation.  This however makes us miss genuine overflow cases,
where 31:28 of the symbol referred are different from bits 31:28 of P,
and non-functional code is produced.

Given the situation, for the purpose of overflow detection we can change
our code to follow the original psABI and only treat the in-place addend
as unsigned in the section symbol case, permitting jumps to offsets
128MiB and above into section.  Sections so large may be uncommon, but
still a reasonable use case.  On the other hand such large offsets from
regular local symbols are not expected and it makes sense to support
(possibly small) negative offsets instead, also in consistency with what
we do for global symbols.

Drop the (P & 0xf0000000) component then, treat the addend as signed
with local non-section symbols and also detect an overflow in the result
of such calculation with local symbols.  NB it does not affect the value
computed for the relocatable field, it only affects overflow detection.

References:

[1] "SYSTEM V APPLICATION BINARY INTERFACE, MIPS RISC Processor
    Supplement, 3rd Edition", Figure 4-11: "Relocation Types", p. 4-19
    <http://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf>

[2] "64-bit ELF Object File Specification, Draft Version 2.5", Table 32
    "Relocation Types", p. 45
    <http://techpubs.sgi.com/library/manuals/4000/007-4658-001/pdf/007-4658-001.pdf>

	bfd/
	* elfxx-mips.c (mips_elf_calculate_relocation): <R_MIPS16_26>
	<R_MIPS_26, R_MICROMIPS_26_S1>: Drop the region bits of the
	reloc location from calculation, treat the addend as signed with
	local non-section symbols and enable overflow detection.

	ld/
	* testsuite/ld-mips-elf/jal-global-overflow-0.d: New test.
	* testsuite/ld-mips-elf/jal-global-overflow-1.d: New test.
	* testsuite/ld-mips-elf/jal-local-overflow-0.d: New test.
	* testsuite/ld-mips-elf/jal-local-overflow-1.d: New test.
	* testsuite/ld-mips-elf/jal-global-overflow.s: New test source.
	* testsuite/ld-mips-elf/jal-local-overflow.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-28 10:33:54 +01:00
Alan Modra 1a72702bb3 Return void from linker callbacks
The ldmain.c implementation of these linker callback functions always
return true, so any code handling a false return is dead.  What's
more, some of the bfd backends abort if ever a false return is seen,
and there seems to be some confusion in gdb's compile-object-load.c.
The return value was never meant to be "oh yes, a multiple_definition
error occurred", but rather "out of memory or other catastrophic
failure".

This patch removes the status return on the callbacks that always
return true.  I kept the return status for "notice" because that one
does happen to need to return "out of memory".

include/
	* bfdlink.h (struct bfd_link_callbacks): Update comments.
	Return void from multiple_definition, multiple_common,
	add_to_set, constructor, warning, undefined_symbol,
	reloc_overflow, reloc_dangerous and unattached_reloc.
bfd/
	* aoutx.h: Adjust linker callback calls throughout file,
	removing dead code.
	* bout.c: Likewise.
	* coff-alpha.c: Likewise.
	* coff-arm.c: Likewise.
	* coff-h8300.c: Likewise.
	* coff-h8500.c: Likewise.
	* coff-i960.c: Likewise.
	* coff-mcore.c: Likewise.
	* coff-mips.c: Likewise.
	* coff-ppc.c: Likewise.
	* coff-rs6000.c: Likewise.
	* coff-sh.c: Likewise.
	* coff-tic80.c: Likewise.
	* coff-w65.c: Likewise.
	* coff-z80.c: Likewise.
	* coff-z8k.c: Likewise.
	* coff64-rs6000.c: Likewise.
	* cofflink.c: Likewise.
	* ecoff.c: Likewise.
	* elf-bfd.h: Likewise.
	* elf-m10200.c: Likewise.
	* elf-m10300.c: Likewise.
	* elf32-arc.c: Likewise.
	* elf32-arm.c: Likewise.
	* elf32-avr.c: Likewise.
	* elf32-bfin.c: Likewise.
	* elf32-cr16.c: Likewise.
	* elf32-cr16c.c: Likewise.
	* elf32-cris.c: Likewise.
	* elf32-crx.c: Likewise.
	* elf32-d10v.c: Likewise.
	* elf32-epiphany.c: Likewise.
	* elf32-fr30.c: Likewise.
	* elf32-frv.c: Likewise.
	* elf32-ft32.c: Likewise.
	* elf32-h8300.c: Likewise.
	* elf32-hppa.c: Likewise.
	* elf32-i370.c: Likewise.
	* elf32-i386.c: Likewise.
	* elf32-i860.c: Likewise.
	* elf32-ip2k.c: Likewise.
	* elf32-iq2000.c: Likewise.
	* elf32-lm32.c: Likewise.
	* elf32-m32c.c: Likewise.
	* elf32-m32r.c: Likewise.
	* elf32-m68hc1x.c: Likewise.
	* elf32-m68k.c: Likewise.
	* elf32-mep.c: Likewise.
	* elf32-metag.c: Likewise.
	* elf32-microblaze.c: Likewise.
	* elf32-moxie.c: Likewise.
	* elf32-msp430.c: Likewise.
	* elf32-mt.c: Likewise.
	* elf32-nds32.c: Likewise.
	* elf32-nios2.c: Likewise.
	* elf32-or1k.c: Likewise.
	* elf32-ppc.c: Likewise.
	* elf32-s390.c: Likewise.
	* elf32-score.c: Likewise.
	* elf32-score7.c: Likewise.
	* elf32-sh.c: Likewise.
	* elf32-sh64.c: Likewise.
	* elf32-spu.c: Likewise.
	* elf32-tic6x.c: Likewise.
	* elf32-tilepro.c: Likewise.
	* elf32-v850.c: Likewise.
	* elf32-vax.c: Likewise.
	* elf32-visium.c: Likewise.
	* elf32-xstormy16.c: Likewise.
	* elf32-xtensa.c: Likewise.
	* elf64-alpha.c: Likewise.
	* elf64-hppa.c: Likewise.
	* elf64-ia64-vms.c: Likewise.
	* elf64-mmix.c: Likewise.
	* elf64-ppc.c: Likewise.
	* elf64-s390.c: Likewise.
	* elf64-sh64.c: Likewise.
	* elf64-x86-64.c: Likewise.
	* elflink.c: Likewise.
	* elfnn-aarch64.c: Likewise.
	* elfnn-ia64.c: Likewise.
	* elfxx-mips.c: Likewise.
	* elfxx-sparc.c: Likewise.
	* elfxx-tilegx.c: Likewise.
	* linker.c: Likewise.
	* pdp11.c: Likewise.
	* pe-mips.c: Likewise.
	* reloc.c: Likewise.
	* reloc16.c: Likewise.
	* simple.c: Likewise.
	* vms-alpha.c: Likewise.
	* xcofflink.c: Likewise.
	* elf32-rl78.c (get_symbol_value, get_romstart, get_ramstart): Delete
	status param.  Adjust calls to these and linker callbacks throughout.
	* elf32-rx.c: (get_symbol_value, get_gp, get_romstart,
	get_ramstart): Delete status param.  Adjust calls to these and
	linker callbacks throughout.
ld/
	* ldmain.c (multiple_definition, multiple_common, add_to_set,
	constructor_callback, warning_callback, undefined_symbol,
	reloc_overflow, reloc_dangerous, unattached_reloc): Return void.
	* emultempl/elf32.em: Adjust callback calls.
gdb/
	* compile/compile-object-load.c (link_callbacks_multiple_definition,
	link_callbacks_warning, link_callbacks_undefined_symbol,
	link_callbacks_undefined_symbol, link_callbacks_reloc_overflow,
	link_callbacks_reloc_dangerous,
	link_callbacks_unattached_reloc): Return void.
2016-05-28 11:17:20 +09:30
GDB Administrator d5dca95ffc Automatic date update in version.in 2016-05-28 00:00:19 +00:00
Maciej W. Rozycki bc27bb0573 MIPS/BFD: Include the addend in JALX's target alignment verification
On RELA targets the addend can affect JALX target's alignment, so only
verify it once the whole relocation calculation has completed.

	bfd/
	* elfxx-mips.c (mips_elf_calculate_relocation) <R_MIPS16_26>
	<R_MIPS_26, R_MICROMIPS_26_S1>: Include the addend in JALX's
	target alignment verification.

	ld/
	* testsuite/ld-mips-elf/unaligned-jalx-addend-0.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-0.d: New
	test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d: New
	test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-0.d: New
	test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d: New
	test.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-0.s: New test
	source.
	* testsuite/ld-mips-elf/unaligned-jalx-addend-1.s: New test
	source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-27 22:31:29 +01:00
Maciej W. Rozycki ceab86af75 MIPS/BFD: Fix section symbol name fetching in relocation
Symbol table entries for section symbols are different between IRIX and
traditional MIPS ELF targets in that IRIX entries have their `st_name'
member pointing at the section's name in the string table section, while
traditional entries have 0 there and the section header string table has
to be referred via the relevant section header's `shn_name' member
instead.

This is chosen with the `elf_backend_name_local_section_symbols' backend
and can be observed with `readelf -s' output for an IRIX object:

Symbol table '.symtab' contains 12 entries:
   Num:    Value  Size Type    Bind   Vis      Ndx Name
     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND
     1: 00000000     0 SECTION LOCAL  DEFAULT    1 .text
     2: 00000000     0 SECTION LOCAL  DEFAULT    3 .data
     3: 00000000     0 SECTION LOCAL  DEFAULT    4 .bss
     4: 00000000     0 SECTION LOCAL  DEFAULT    5 .reginfo
     5: 00000000     0 SECTION LOCAL  DEFAULT    6 .MIPS.abiflags
     6: 00000000     0 SECTION LOCAL  DEFAULT    7 .pdr
     7: 00000000     0 SECTION LOCAL  DEFAULT    9 .gnu.attributes
     8: 00002000    16 FUNC    GLOBAL DEFAULT    1 foo
     9: 00004008     0 FUNC    LOCAL  DEFAULT    1 abar
    10: 00002008     0 FUNC    LOCAL  DEFAULT    1 afoo
    11: 00004000    16 FUNC    GLOBAL DEFAULT    1 bar

and a corresponding traditional object:

Symbol table '.symtab' contains 12 entries:
   Num:    Value  Size Type    Bind   Vis      Ndx Name
     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND
     1: 00000000     0 SECTION LOCAL  DEFAULT    1
     2: 00000000     0 SECTION LOCAL  DEFAULT    3
     3: 00000000     0 SECTION LOCAL  DEFAULT    4
     4: 00004008     0 FUNC    LOCAL  DEFAULT    1 abar
     5: 00002008     0 FUNC    LOCAL  DEFAULT    1 afoo
     6: 00000000     0 SECTION LOCAL  DEFAULT    5
     7: 00000000     0 SECTION LOCAL  DEFAULT    6
     8: 00000000     0 SECTION LOCAL  DEFAULT    7
     9: 00000000     0 SECTION LOCAL  DEFAULT    9
    10: 00002000    16 FUNC    GLOBAL DEFAULT    1 foo
    11: 00004000    16 FUNC    GLOBAL DEFAULT    1 bar

respectively.  Consequently the right way to retrieve a section symbol's
name has to be chosen in `mips_elf_calculate_relocation' for the purpose
of error reporting.

Originally we produced symbol tables in the traditional object format
only and we handled it correctly until it was lost in a rewrite with:

commit 7403cb6305
Author: Mark Mitchell <mark@codesourcery.com>
Date:   Wed Jun 30 20:13:43 1999 +0000

probably because of the extra pointer indirection added which made the
same expression have a different meaning.

With the addition of IRIX symbol table format with:

commit 174fd7f955
Author: Richard Sandiford <rdsandiford@googlemail.com>
Date:   Mon Feb 9 08:04:00 2004 +0000

the bug has been partially covered and now when a relocation error is
triggered with an IRIX object the offending section symbol is correctly
reported:

tmpdir/dump0.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `.text'
tmpdir/dump0.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `.text'

because `bfd_elf_string_from_elf_section' retrieves the name from the
string table section.  With a traditional object however the function
returns an empty string and consequently `no symbol' is printed instead:

tmpdir/dump0.o: In function `foo':
(.text+0x2000): relocation truncated to fit: R_MIPS_26 against `no symbol'
tmpdir/dump0.o: In function `bar':
(.text+0x4000): relocation truncated to fit: R_MIPS_26 against `no symbol'

Restore the original semantics so that the section name is always
correctly retrieved.

	bfd/
	* elfxx-mips.c (mips_elf_calculate_relocation): Also use the
	section name if `bfd_elf_string_from_elf_section' returns an
	empty string.

	ld/
	* testsuite/ld-mips-elf/reloc-local-overflow.d: New test.
	* testsuite/ld-mips-elf/reloc-local-overflow.s: Source for the
	new test.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new test.
2016-05-27 22:25:42 +01:00
H.J. Lu 1848e56734 Update x86 CPU_XXX_FLAGS handling
Support defining CPU_XXX_FLAGS with other CPU_XXX_FLAGS.  Update
CPU_XXX_FLAGS to enable more bits like x87 and SYSCALL.  Don't enable
MMX when enabling SSE, AVX or AVX512.  Don't disable AVX nor AVX512 when
disabling SSE.  Don't disable AVX512 when disabling AVX.  Disable F16C,
FMA, FMA4 and XOP when disabling AVX.  Add 87, no287, no387, no687,
nosse2, nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2 directives
to x86 assembler.

TODO: Add more .noXXX, like .noavx512f, directives to x86 assembler.

gas/

	PR gas/20145
	* config/tc-i386.c (cpu_arch): Add 687.
	(cpu_noarch): Add no287, no387, no687, nosse2, nosse3, nossse3,
	nosse4.1, nosse4.2, nosse4 and noavx2.
	(parse_real_register): Check cpuregmmx instead of cpummx for MMX
	register.  Check cpuregxmm instead of cpusse for XMM register.
	Check cpuregymm instead of cpuavx for YMM register.  Check
	cpuregzmm/cpuregmask instead of cpuavx512f for ZMMM/mask register.
	* doc/c-i386.texi: Mention 687, no287, no387, no687, nosse2,
	nosse3, nossse3, nosse4.1, nosse4.2, nosse4 and noavx2.
	* testsuite/gas/i386/arch-10-prefetchw.d (as): Add mmx.
	* testsuite/gas/i386/arch-10.d (as): Likewise.
	* testsuite/gas/i386/arch-11.s: Add ".arch .mmx".
	* testsuite/gas/i386/i386.exp: Pass mmx to assembler for
	arch-10-3 and arch-10-4.  Run no87-3, nosse-4, nosse-5, noavx-3
	and noavx-4.
	* testsuite/gas/i386/no87-3.l: New file.
	* testsuite/gas/i386/no87-3.s: Likewise.
	* testsuite/gas/i386/noavx-3.l: Likewise.
	* testsuite/gas/i386/noavx-3.s: Likewise.
	* testsuite/gas/i386/noavx-4.d: Likewise.
	* testsuite/gas/i386/noavx-4.s: Likewise.
	* testsuite/gas/i386/nosse-4.l: Likewise.
	* testsuite/gas/i386/nosse-4.s: Likewise.
	* testsuite/gas/i386/nosse-5.d: Likewise.
	* testsuite/gas/i386/nosse-5.s: Likewise.

opcodes/

	PR gas/20145
	* i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS.  Remove
	CpuMMX from CPU_SSE_FLAGS.  Remove AVX and AVX512 bits from
	CPU_ANY_SSE_FLAGS.  Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
	Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
	CpuXSAVEC.  Add CPU_AVX_FLAGS to CpuF16C.  Remove CpuMMX from
	CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
	CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
	Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS.   Add CPU_ANY_287_FLAGS,
	CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
	CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
	CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS.  Enable CpuRegMMX
	for MMX.  Enable CpuRegXMM for SSE, AVX and AVX512.  Enable
	CpuRegYMM for AVX and AVX512VL,  Enable CpuRegZMM and
	CpuRegMask for AVX512.
	(cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
	and CpuRegMask.
	(set_bitfield_from_cpu_flag_init): New function.
	(set_bitfield): Remove const on f.  Call
	set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
	* i386-opc.h (CpuRegMMX): New.
	(CpuRegXMM): Likewise.
	(CpuRegYMM): Likewise.
	(CpuRegZMM): Likewise.
	(CpuRegMask): Likewise.
	(i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
	and cpuregmask.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2016-05-27 10:05:57 -07:00
Pedro Alves 744608cc85 Skip attach-many-short-lived-threads.exp on known-broken DejaGnu versions
If the testsuite is run with a DejaGnu version that predates the fix
from last year:

  [PATCH] DejaGnu kills the wrong process due to PID-reuse races
  http://lists.gnu.org/archive/html/dejagnu/2015-07/msg00005.html

... gdb.threads/attach-many-short-lived-threads.exp fails randomly,
often.  Other tests randomly fail due to that issue too, but this one
is _much_ more exposed.

DejaGnu 1.6 was released meanwhile, which includes that DejaGnu fix,
and also some distros backported the fix too.

So skip the test when run with older/broken DejaGnus.

gdb/testsuite/ChangeLog:
2016-05-27  Pedro Alves  <palves@redhat.com>

	* gdb.threads/attach-many-short-lived-threads.exp (bad_dejagnu):
	New procedure.
	(top level): Call it, and bail out of DejaGnu is known to be bad.
2016-05-27 16:18:28 +01:00
H.J. Lu e92bae6260 Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
AMD64 vs CpuIntel64 ISA should be handled similar as AT&T vs Intel
syntax.  Since cpu_flags isn't sorted by position, we need to check
the whole cpu_flags array for the maximum position when verifying
CpuMax.

gas/

	PR gas/20154
	* config/tc-i386.c (cpu_flags_match): Don't set cpuamd64 nor
	cpuintel64.
	(match_template): Check Intel64/AMD64 ISA.

opcodes/

	PR gas/20154
	* i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
	(opcode_modifiers): Add AMD64 and Intel64.
	(main): Properly verify CpuMax.
	* i386-opc.h (CpuAMD64): Removed.
	(CpuIntel64): Likewise.
	(CpuMax): Set to CpuNo64.
	(i386_cpu_flags): Remove cpuamd64 and cpuintel64.
	(AMD64): New.
	(Intel64): Likewise.
	(i386_opcode_modifier): Add amd64 and intel64.
	(i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
	on call and jmp.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
2016-05-27 08:03:17 -07:00
Eli Zaretskii c185ba27ca Improve documentation of general query packets
gdb/doc/ChangeLog:

	* gdb.texinfo (General Query Packets): Move the description of the
	response before the long list of the specific 'read' and 'write'
	requests.
2016-05-27 16:59:22 +03:00
H.J. Lu e89c5eaa72 Correct CpuMax in i386-opc.h
CpuMax should be CpuIntel64, not CpuNo64.  i386-gen.c is updated to
verify that CpuMax is correct.  X86 assembler is updated to properly
set cpuamd64 and cpuintel64.

gas/

	PR gas/20154
	* config/tc-i386.c (intel64): New.
	(cpu_flags_match): Set cpuamd64 and cpuintel64.
	(md_parse_option): Set intel64 instead of cpuamd64 and
	cpuintel64.

opcodes/

	PR gas/20154
	* i386-gen.c (main): Fail if CpuMax is incorrect.
	* i386-opc.h (CpuMax): Set to CpuIntel64.
	* i386-tbl.h: Regenerated.
2016-05-27 06:55:53 -07:00
Nick Clifton 1690f1db1a Fix typo introduced during the most recent synchronization update. 2016-05-27 14:34:06 +01:00
Nick Clifton 77d66e7b30 Improve the MSP430 disassembler's handling of memory read errors.
PR target/20150
	* msp430-dis.c (msp430dis_read_two_bytes): New function.
	(msp430dis_opcode_unsigned): New function.
	(msp430dis_opcode_signed): New function.
	(msp430_singleoperand): Use the new opcode reading functions.
	Only disassenmble bytes if they were successfully read.
	(msp430_doubleoperand): Likewise.
	(msp430_branchinstr): Likewise.
	(msp430x_callx_instr): Likewise.
	(print_insn_msp430): Check that it is safe to read bytes before
	attempting disassembly.  Use the new opcode reading functions.
2016-05-27 13:49:58 +01:00
Andrew Burgess 51415b9f30 gdb: Forward VALUE_LVAL when avoiding side effects for STRUCTOP_STRUCT
When evaluating an expression with EVAL_AVOID_SIDE_EFFECTS if the value
we return is forced to be of type not_lval then GDB will be unable to
take the address of the returned value.

Instead, we should properly initialise the LVAL of the returned value.

This commit builds on two previous commits 2520f728b7 (Forward
VALUE_LVAL when avoiding side effects for STRUCTOP_STRUCT) and
ac775bf4d3 (gdb: Forward VALUE_LVAL when avoiding side effects for
STRUCTOP_PTR), which in turn build on ac1ca910d7 (Fixes for PR
exp/15364).

This commit is currently untested due to my lack of access to an OpenCL
compiler, however, if follows the same pattern as the first two commits
mentioned above and so I believe that it is correct.

gdb/ChangeLog:

	* opencl-lang.c (evaluate_subexp_opencl): If
	EVAL_AVOID_SIDE_EFFECTS mode, forward the VALUE_LVAL attribute to
	the returned value in the STRUCTOP_STRUCT case.
2016-05-27 13:07:15 +01:00
Andrew Burgess ac775bf4d3 gdb: Forward VALUE_LVAL when avoiding side effects for STRUCTOP_PTR
Assume that we have a C program like this:

  struct foo_type
  {
    int var;
  } foo;

  struct foo_type *foo_ptr = &foo;

  int
  main ()
  {
    return foo_ptr->var;
  }

Then GDB should be able to evaluate the following, however, it currently
does not:

  (gdb) start
  ...
  (gdb) whatis &(foo_ptr->var)
  Attempt to take address of value not located in memory.

The problem is that in EVAL_AVOID_SIDE_EFFECTS mode,
eval.c:evaluate_subexp_standard always returns a not_lval value as the
result for a STRUCTOP_PTR operation. As a consequence, the rest of
the code believes that one cannot take the address of the returned
value.

This patch fixes STRUCTOP_PTR handling so that the VALUE_LVAL
attribute for the returned value is properly initialized.  After this
change, the above session becomes:

  (gdb) start
  ...
  (gdb) whatis &(foo_ptr->var)
  type = int *

This commit is largely the same as commit 2520f728b7 (Forward
VALUE_LVAL when avoiding side effects for STRUCTOP_STRUCT) but applied
to STRUCTOP_PTR rather than STRUCTOP_STRUCT.  Both of these commits are
building on top of commit ac1ca910d7 (Fixes for PR exp/15364).

gdb/ChangeLog:

	* eval.c (evaluate_subexp_standard): If EVAL_AVOID_SIDE_EFFECTS
	mode, forward the VALUE_LVAL attribute to the returned value in
	the STRUCTOP_PTR case.

gdb/testsuite/ChangeLog:

	* gdb.base/whatis.c: Extend the test case.
	* gdb.base/whatis.exp: Add additional tests.
2016-05-27 13:06:25 +01:00
H.J. Lu 9d07ebe108 Don't clear cpu64 nor cpuno64
No need to clear cpu64 nor cpuno64 since they will be cleared by
cpu_flags_and.

	* config/tc-i386.c (cpu_flags_match): Don't clear cpu64 nor
	cpuno64.
2016-05-27 04:56:05 -07:00
Peter Bergner 19dfcc89e8 Add support for new POWER ISA 3.0 instructions.
opcodes/

	* ppc-opc.c (CY): New define.  Document it.
	(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.

gas/
	* testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
	* testsuite/gas/ppc/altivec3.s: Likewise.
	* testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
	* testsuite/gas/ppc/power9.s: Likewise.
2016-05-26 19:06:51 -05:00
GDB Administrator 5e0bc41893 Automatic date update in version.in 2016-05-27 00:00:20 +00:00
H.J. Lu 8d5b9a5a30 Append ".p2align 4" to some x86 directive tests
Append ".p2align 4" to some x86 directive tests for explicit paddings
for section alignment to avoid implicit section alignment in assembler
listings.

	* testsuite/gas/i386/avx512vl-2.l: Append "#pass".
	* testsuite/gas/i386/noavx-1.l: Likewise.
	* testsuite/gas/i386/nommx-1.l: Likewise.
	* testsuite/gas/i386/nosse-1.l: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
	* testsuite/gas/i386/avx512vl-2.s: Append ".p2align 4".
	* testsuite/gas/i386/noavx-1.s: Likewise.
	* testsuite/gas/i386/nommx-1.s: Likewise.
	* testsuite/gas/i386/nosse-1.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-26 07:55:38 -07:00
Trevor Saunders 81cead6f5e metag: make an array's type unsigned char[]
It contains values between 128 and 256 which fit in an unsigned char, but not a
signed char, so we should explicitly use unsigned char to not rely on how these
values are converted to signed char.

gas/ChangeLog:

2016-05-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-metag.c (metag_handle_align): Make the type of noop
	unsigned char.
2016-05-26 08:46:01 -04:00
Trevor Saunders 79052aaec9 rx: make the type of a variable bfd_reloc_code_real_type
gas/ChangeLog:

2016-05-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* config/tc-rx.c (md_convert_frag): Make the type of reloc_type
	bfd_reloc_code_real_type.
2016-05-26 08:45:03 -04:00
Maciej W. Rozycki ed53407eec MIPS/BFD: Don't stop processing on `bfd_reloc_outofrange'
Upon a `bfd_reloc_outofrange' error continue processing so that any
further issues are also reported, similarly to how `bfd_reloc_overflow'
is handled.  Adjust message formatting accordingly, using `%X' to abort
processing at conclusion.

Reduce the number of test cases by grouping relocations the handling of
which can now be verified together with a single source and dump.

	bfd/
	* elfxx-mips.c (_bfd_mips_elf_relocate_section)
	<bfd_reloc_outofrange>: Use the `%X%H' rather than `%C' format
	for message.  Continue processing rather than returning failure.

	ld/
	* testsuite/ld-mips-elf/unaligned-jalx-0.d: Fold
	`unaligned-jalx-2' here.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: Fold
	`unaligned-jalx-mips16-2' here.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: Fold
	`unaligned-jalx-micromips-2' here.
	* testsuite/ld-mips-elf/unaligned-jalx-0.s: Update accordingly.
	* testsuite/ld-mips-elf/unaligned-jalx-1.d: Update error
	message.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: Likewise.
	* testsuite/ld-mips-elf/unaligned-jalx-2.d: Remove test.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: Remove test.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: Remove
	test.
	* testsuite/ld-mips-elf/unaligned-jalx-2.s: Remove test source.
	* testsuite/ld-mips-elf/unaligned-lwpc-0.d: Fold
	`unaligned-lwpc-3' here.
	* testsuite/ld-mips-elf/unaligned-lwpc-0.s: Update accordingly.
	* testsuite/ld-mips-elf/unaligned-lwpc-1.d: Fold
	`unaligned-lwpc-2' here.
	* testsuite/ld-mips-elf/unaligned-lwpc-1.s: Update accordingly.
	* testsuite/ld-mips-elf/unaligned-lwpc-2.d: Remove test.
	* testsuite/ld-mips-elf/unaligned-lwpc-2.s: Remove test source.
	* testsuite/ld-mips-elf/unaligned-lwpc-3.d: Remove test.
	* testsuite/ld-mips-elf/unaligned-lwpc-3.s: Remove test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-0.d: Fold
	`unaligned-ldpc-4' here.
	* testsuite/ld-mips-elf/unaligned-ldpc-0.s: Update accordingly.
	* testsuite/ld-mips-elf/unaligned-ldpc-1.d: Update error
	message.  Fold `unaligned-ldpc-2' and `unaligned-ldpc-3' here.
	* testsuite/ld-mips-elf/unaligned-ldpc-1.s: Update accordingly.
	* testsuite/ld-mips-elf/unaligned-ldpc-2.d: Remove test.
	* testsuite/ld-mips-elf/unaligned-ldpc-2.s: Remove test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-3.d: Remove test.
	* testsuite/ld-mips-elf/unaligned-ldpc-3.s: Remove test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-4.d: Remove test.
	* testsuite/ld-mips-elf/unaligned-ldpc-4.s: Remove test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Delete removed tests.
2016-05-26 12:28:59 +01:00
Nick Clifton 0d832c8ea7 Provide the __bssstart and __bsssize symbols needed by the MSP430's crt0.o code.
PR target/20134
	* scripttempl/elf32msp430.sc (.bss): Provide __bssstart and
	__bsssize.
	* scripttempl/elf32msp430_3.sc (.bss): Likewise.
2016-05-26 11:43:38 +01:00
Trevor Saunders 94740f9c4b metag: add extern C to header
include/ChangeLog:

2016-05-26  Trevor Saunders  <tbsaunde+binutils@tbsaunde.org>

	* opcode/metag.h: wrap declarations in extern "C".
2016-05-26 06:12:15 -04:00
GDB Administrator d7b61136f9 Automatic date update in version.in 2016-05-26 00:00:20 +00:00
H.J. Lu 73b090a922 Require another match for AVX512VL
The AVX512VL bit alone isn't sufficient to select a 128-bit or 256-bit
AVX512 instruction.  We must match another AVX512 bit.

	PR gas/20140
	* config/tc-i386.c (cpu_flags_match): Require another match
	for AVX512VL.
	* testsuite/gas/i386/i386.exp: Run avx512vl-1, avx512vl-2,
	x86-64-avx512vl-1 and x86-64-avx512vl-2.
	* testsuite/gas/i386/avx512vl-1.l: New file.
	* testsuite/gas/i386/avx512vl-1.s: Likewise.
	* testsuite/gas/i386/avx512vl-2.l: Likewise.
	* testsuite/gas/i386/avx512vl-2.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-1.l: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-1.s: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.l: Likewise.
	* testsuite/gas/i386/x86-64-avx512vl-2.s: Likewise.
2016-05-25 15:04:47 -07:00
Maciej W. Rozycki de341542a6 MIPS/BFD: Report `bfd_reloc_outofrange' errors as such
A `bfd_reloc_outofrange' condition from `mips_elf_calculate_relocation'
currently triggers the warning callback, which in the case of LD prints
messages like:

foo.o: In function `foo':
(.text+0x0): warning: JALX to a non-word-aligned address

or:

foo.o: In function `foo':
(.text+0x0): warning: PC-relative load from unaligned address

and nothing else, which suggests this is a benign condition and link has
otherwise successfully run to completion.  This is however not the case,
the link terminates right away with no further messages and no output
produced.

Use the general error or warning info callback then, preserving the
message format.  Also set a BFD error condition so that a failure is
unambiguously reported.  Complement the change with a set of suitable
test suite additions.

	bfd/
	* elfxx-mips.c (_bfd_mips_elf_relocate_section)
	<bfd_reloc_outofrange>: Call `->einfo' rather than `->warning'.
	Call `bfd_set_error'.

	ld/
	* testsuite/ld-mips-elf/unaligned-jalx-0.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-0.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-0.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-lwpc-0.d: New test.
	* testsuite/ld-mips-elf/unaligned-lwpc-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-lwpc-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-lwpc-3.d: New test.
	* testsuite/ld-mips-elf/unaligned-ldpc-0.d: New test.
	* testsuite/ld-mips-elf/unaligned-ldpc-1.d: New test.
	* testsuite/ld-mips-elf/unaligned-ldpc-2.d: New test.
	* testsuite/ld-mips-elf/unaligned-ldpc-3.d: New test.
	* testsuite/ld-mips-elf/unaligned-ldpc-4.d: New test.
	* testsuite/ld-mips-elf/unaligned-jalx-0.s: New test source.
	* testsuite/ld-mips-elf/unaligned-jalx-1.s: New test source.
	* testsuite/ld-mips-elf/unaligned-jalx-2.s: New test source.
	* testsuite/ld-mips-elf/unaligned-insn.s: New test source.
	* testsuite/ld-mips-elf/unaligned-lwpc-0.s: New test source.
	* testsuite/ld-mips-elf/unaligned-lwpc-1.s: New test source.
	* testsuite/ld-mips-elf/unaligned-lwpc-2.s: New test source.
	* testsuite/ld-mips-elf/unaligned-lwpc-3.s: New test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-0.s: New test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-1.s: New test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-2.s: New test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-3.s: New test source.
	* testsuite/ld-mips-elf/unaligned-ldpc-4.s: New test source.
	* testsuite/ld-mips-elf/unaligned-syms.s: New test source.
	* testsuite/ld-mips-elf/mips-elf.exp: Run the new tests.
2016-05-25 21:03:22 +01:00
H.J. Lu f3ad76370f Enable VREX for all AVX512 directives
Add all AVX512 bits to CPU_ANY_AVX_FLAGS.

	* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
	CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
	and CPU_AVX512VBMI_FLAGS.  Add CpuAVX512DQ, CpuAVX512BW,
	CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
	CPU_ANY_AVX_FLAGS.
	* i386-init.h: Regenerated.
2016-05-25 11:23:40 -07:00
H.J. Lu f1360d5830 Enable VREX for AVX512 directives
Enable VREX for AVX512 instructions with upper 16 vector registers.

gas/

	PR gas/20141
	* testsuite/gas/i386/i386.exp: Run x86-64-pr20141.
	* testsuite/gas/i386/x86-64-pr20141.d: New file.
	* testsuite/gas/i386/x86-64-pr20141.s: Likewise.

opcodes/

	PR gas/20141
	* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
	CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
	* i386-init.h: Regenerated.
2016-05-25 10:49:25 -07:00
H.J. Lu 293f5f6543 Reimplement .no87/.nommx/.nosse/.noavx directives
Move all .noXXX directives to cpu_noarch.

gas/

	* config/tc-i386.c (arch_entry): Remove negated.
	(noarch_entry): New struct.
	(cpu_arch): Updated.  Remove .no87, .nommx, .nosse and .noavx.
	(cpu_noarch): New.
	(set_cpu_arch): Check cpu_noarch after cpu_arch.
	(md_parse_option): Allow -march=+nosse.  Check cpu_noarch after
	cpu_arch.
	(output_message): New function.
	(show_arch): Use it.  Handle cpu_noarch.
	* testsuite/gas/i386/i386.exp: Run nommx-1, nommx-2, nommx-3,
	nosse-1, nosse-2, nosse-3, noavx-1 and noavx-2.
	* testsuite/gas/i386/noavx-1.l: New file.
	* testsuite/gas/i386/noavx-1.s: Likewise.
	* testsuite/gas/i386/noavx-2.s: Likewise.
	* testsuite/gas/i386/noavx-2.l: Likewise.
	* testsuite/gas/i386/nommx-1.s: Likewise.
	* testsuite/gas/i386/nommx-1.l: Likewise.
	* testsuite/gas/i386/nommx-2.s: Likewise.
	* testsuite/gas/i386/nommx-2.l: Likewise.
	* testsuite/gas/i386/nommx-3.s: Likewise.
	* testsuite/gas/i386/nommx-3.l: Likewise.
	* testsuite/gas/i386/nosse-1.s: Likewise.
	* testsuite/gas/i386/nosse-1.l: Likewise.
	* testsuite/gas/i386/nosse-2.s: Likewise.
	* testsuite/gas/i386/nosse-2.l: Likewise.
	* testsuite/gas/i386/nosse-3.s: Likewise.
	* testsuite/gas/i386/nosse-3.l: Likewise.

opcodes/

	* i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
	CPU_ANY_X87_FLAGS.  Add CPU_ANY_MMX_FLAGS.
	* i386-init.h: Regenerated.
2016-05-25 10:26:13 -07:00
H.J. Lu e6cc316af9 Enable 64-bit archives in ar and ranlib
Since existing ld and gold support the 64-bit (MIPS) ELF archives, we
can use the 64-bit (MIPS) ELF archives as 64-bit archives.  Since the
plugin target is used to create archive in plugin-enabled ar, we need
a way to enable 64-bit archives in the plugin target.  This patch adds
--enable-64-bit-archive to bfd to force 64-bit archives in ar and
ranlib.  Since both 64-bit MIPS and s390 ELF targets currently use
64-bit archives, 64-bit archives are enabled by default for them.
64-bit archive is generated automatically if the archive is too big.

Tested on Linux/x86 and Linux/x86-64 with existing ld and gold.

bfd/

	PR binutils/14625
	* archive.c (bfd_slurp_armap): Replace
	bfd_elf64_archive_slurp_armap with
	_bfd_archive_64_bit_slurp_armap.
	(bsd_write_armap): Call _bfd_archive_64_bit_write_armap if
	BFD64 is defined and the archive is too big.
	(coff_write_armap): Likewise.
	* archive64.c (bfd_elf64_archive_slurp_armap): Renamed to ...
	(_bfd_archive_64_bit_slurp_armap): This.
	(bfd_elf64_archive_write_armap): Renamed to ...
	(_bfd_archive_64_bit_write_armap): This.
	* configure.ac: Add --enable-64-bit-archive.
	(want_64_bit_archive): New.  Set to true by default for 64-bit
	MIPS and s390 ELF targets.
	(USE_64_BIT_ARCHIVE): New AC_DEFINE.
	* config.in: Regenerated.
	* configure: Likewise.
	* elf64-mips.c (bfd_elf64_archive_functions): Removed.
	(bfd_elf64_archive_slurp_armap): Likewise.
	(bfd_elf64_archive_write_armap): Likewise.
	(bfd_elf64_archive_slurp_extended_name_table): Likewise.
	(bfd_elf64_archive_construct_extended_name_table): Likewise.
	(bfd_elf64_archive_truncate_arname): Likewise.
	(bfd_elf64_archive_read_ar_hdr): Likewise.
	(bfd_elf64_archive_write_ar_hdr): Likewise.
	(bfd_elf64_archive_openr_next_archived_file): Likewise.
	(bfd_elf64_archive_get_elt_at_index): Likewise.
	(bfd_elf64_archive_generic_stat_arch_elt): Likewise.
	(bfd_elf64_archive_update_armap_timestamp): Likewise.
	* elf64-s390.c (bfd_elf64_archive_functions): Removed.
	(bfd_elf64_archive_slurp_armap): Likewise.
	(bfd_elf64_archive_write_armap): Likewise.
	(bfd_elf64_archive_slurp_extended_name_table): Likewise.
	(bfd_elf64_archive_construct_extended_name_table): Likewise.
	(bfd_elf64_archive_truncate_arname): Likewise.
	(bfd_elf64_archive_read_ar_hdr): Likewise.
	(bfd_elf64_archive_write_ar_hdr): Likewise.
	(bfd_elf64_archive_openr_next_archived_file): Likewise.
	(bfd_elf64_archive_get_elt_at_index): Likewise.
	(bfd_elf64_archive_generic_stat_arch_elt): Likewise.
	(bfd_elf64_archive_update_armap_timestamp): Likewise.
	* elfxx-target.h (TARGET_BIG_SYM): Use _bfd_archive_64_bit on
	BFD_JUMP_TABLE_ARCHIVE if USE_64_BIT_ARCHIVE is defined and
	bfd_elfNN_archive_functions isn't defined.
	(TARGET_LITTLE_SYM): Likewise.
	* libbfd-in.h (_bfd_archive_64_bit_slurp_armap): New prototype.
	(_bfd_archive_64_bit_write_armap): Likewise.
	(_bfd_archive_64_bit_slurp_extended_name_table): New macro.
	(_bfd_archive_64_bit_construct_extended_name_table): Likewise.
	(_bfd_archive_64_bit_truncate_arname): Likewise.
	(_bfd_archive_64_bit_read_ar_hdr): Likewise.
	(_bfd_archive_64_bit_write_ar_hdr): Likewise.
	(_bfd_archive_64_bit_openr_next_archived_file): Likewise.
	(_bfd_archive_64_bit_get_elt_at_index): Likewise.
	(_bfd_archive_64_bit_generic_stat_arch_elt): Likewise.
	(_bfd_archive_64_bit_update_armap_timestamp): Likewise.
	* libbfd.h: Regenerated.
	* plugin.c (plugin_vec): Use _bfd_archive_64_bit on
	BFD_JUMP_TABLE_ARCHIVE if USE_64_BIT_ARCHIVE is defined.

binutils/

	PR binutils/14625
	* NEWS: Mention --enable-64-bit-archive.
2016-05-25 09:47:03 -07:00