fe8afbc48f
cpu/
...
* m32c.cpu (f-dsp-32-u24): Fix mode of extract handler.
(f-dsp-40-u20, f-dsp-40-u24): Ditto.
opcodes/
* cgen-ibld.in: #include "cgen/basic-modes.h".
* fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
* lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
* mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
* xstormy16-ibld.c: Regenerate.
2010-01-06 05:30:19 +00:00
2edcd24424
PR 11123
...
* arm-dis.c (print_insn_coprocessor): Initialise value.
2010-01-04 10:18:32 +00:00
0dc9305793
bfd/
...
* archures.c: Add bfd_mach_ppc_e500mc64.
* bfd-in2.h: Regenerate.
* cpu-powerpc.c (bfd_powerpc_archs): Add entry for
bfd_mach_ppc_e500mc64.
gas/
* config/tc-ppc.c (md_show_usage): Document -me500mc64.
opcodes/
* ppc-dis.c (ppc_opts): Add entry for "e500mc64".
2010-01-04 02:32:56 +00:00
05994f45db
* cgen-asm.in: Update copyright year.
...
* cgen-dis.in: Update copyright year.
* cgen-ibld.in: Update copyright year.
* fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
* fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
* frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
* ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
* ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
* iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
* iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
* lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
* lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
* m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
* m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
* m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
* mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
* mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
* mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
* openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
* openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
* xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
* xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
* xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
* xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2010-01-02 18:50:59 +00:00
43ecc30f09
Move 2009 binutils ChangeLog to ChangeLog-2009.
2010-01-01 18:06:10 +00:00
2426c15ff8
Replace VexNDS, VexNDD and VexLWP with VexVVVV.
...
gas/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check vexvvvv instead
of vexnds and vexndd.
(build_modrm_byte): Check vexvvvv instead of vexnds, vexndd
and vexlwp.
opcodes/
2009-12-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and
VexLWP. Add VexVVVV.
* i386-opc.h (VexNDS): Removed.
(VexNDD): Likewise.
(VexLWP): Likewise.
(VEXXDS): New.
(VEXNDD): Likewise.
(VEXLWP): Likewise.
(VexVVVV): Likewise.
(i386_opcode_modifier): Remove vexnds, vexndd and vexlwp.
Add vexvvvv.
* i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with
VexVVVV=2 and VexLWP with VexVVVV=3.
* i386-tbl.h: Regenerated.
2009-12-19 18:36:27 +00:00
94ff3a50d8
Move Imm1 before Imm8.
...
2009-12-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (operand_types): Move Imm1 before Imm8.
2009-12-18 21:07:58 +00:00
ff4a8d2b93
PR binutils/10924
...
* config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination
register.
(do_mrs): Likewise.
(do_mul): Likewise.
* arm-dis.c: Add support for %<>ru and %<>rU formats to enforce
unique register numbers. Extend support for %<>R format to
thumb32 and coprocessor instructions.
* gas/arm/unpredictable.s: Add more unpredictable instructions.
* gas/arm/unpredictable.d: Add expected disassemblies.
2009-12-17 09:52:18 +00:00
2eb952a4d9
Remove ByteOkIntel.
...
gas/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Set i.suffix to 0 in
Intel syntax if size is ignored and b/l/w suffixes are
illegal.
(check_byte_reg): Remove byteokintel check.
opcodes/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove ByteOkIntel.
* i386-opc.h (ByteOkIntel): Removed.
(i386_opcode_modifier): Remove byteokintel.
* i386-opc.tbl: Remove ByteOkIntel.
* i386-tbl.h: Regenerated.
2009-12-16 20:08:32 +00:00
7f399153c6
Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode.
...
gas/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38,
vex0f3a, xop08, xop09 and xop0a with vexopcode.
opcodes/
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38,
Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode.
* i386-opc.h (Vex0F): Removed.
(Vex0F38): Likewise.
(Vex0F3A): Likewise.
(VexOpcode): New.
(VEX0F): Likewise.
(VEX0F38): Likewise.
(VEX0F3A): Likewise.
(XOP08): Defined as a macro.
(XOP09): Likewise.
(XOP0A): Likewise.
(i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08,
xop09 and xop0a. Add vexopcode.
* i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with
VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3,
XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5.
* i386-tbl.h: Regenerated.
2009-12-16 15:43:16 +00:00
25ac7f26dd
Fix a typo in ChangeLog.
2009-12-16 05:31:40 +00:00
8c43a48b28
Replace VEX2SOURCES with XOP2SOURCES.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Check XOP2SOURCES
instead VEX2SOURCES.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (VEX2SOURCES): Renamed to ...
(XOP2SOURCES): This.
2009-12-16 05:18:11 +00:00
8cd7925b45
Replace Vex2Sources and Vex3Sources with VexSources.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_operands): Check vexsources
instead of vex3sources.
(build_modrm_byte): Check vexsources instead of vex2sources
and vex3sources.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove Vex3Sources and
Vex2Sources. Add VexSources.
* i386-opc.h ()Vex2Sources: Removed.
(Vex3Sources): Likewise.
(VEX2SOURCES): New.
(VEX3SOURCES): Likewise.
(VexSources): Likewise.
(i386_opcode_modifier): Remove vex2sources and vex3sources.
Add vexsources.
* i386-opc.tbl: Replace Vex2Sources with VexSources=1 and
Vex3Sourceswith VexSources=2.
* i386-tbl.h: Regenerated.
2009-12-16 04:00:35 +00:00
1ef99a7be9
Remove VexW0 and VexW1. Add VexW.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1
with vexw.
(build_modrm_byte): Likewise.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add
VexW.
* i386-opc.h (VexW0): Removed.
(VexW1): Likewise.
(VEXW0): New.
(VEXW1): Likewise.
(VexW): Likewise.
(i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw.
* i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with
Vex=2.
* i386-init.h: Regenerated.
* i386-tbl.h: Likewise.
2009-12-16 02:10:45 +00:00
bcf2684fb0
Add VEX_W_3818_P_2_M_0.
...
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (VEX_W_3818_P_2_M_0): New.
(vex_w_table): Add VEX_W_3818_P_2_M_0.
(mod_table): Use VEX_W_3818_P_2_M_0.
2009-12-15 23:33:51 +00:00
a179a9fdaa
Reformat vex_w_table.
...
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (vex_w_table): Reformat.
2009-12-15 22:20:50 +00:00
53aa04a0be
Add VEX_W_382X_P_2_M_0.
...
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (VEX_W_382X_P_2_M_0): New.
(vex_w_table): Add VEX_W_382X_P_2_M_0.
(mod_table): Use VEX_W_382X_P_2_M_0.
2009-12-15 22:13:05 +00:00
efdb52b70e
Reformat vex_w_table.
...
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (vex_w_table): Reformat.
2009-12-15 21:37:51 +00:00
9e30b8e093
Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX.
...
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (USE_VEX_W_TABLE): New.
(VEX_W_TABLE): Likewise.
(VEX_W_XXX): Likewise.
(vex_w_table): Likewise.
(prefix_table): Use VEX_W_XXX.
(vex_table): Likewise.
(vex_len_table): Likewise.
(mod_table): Likewise.
(get_valid_dis386): Handle USE_VEX_W_TABLE.
* i386-opc.tbl: Add VexW0 to AVX instructions where the VEX.W bit
isn't used.
* i386-tbl.h: Regenerated.
2009-12-15 18:56:09 +00:00
e3c58833bf
Define VEX128 and VEX256.
...
gas/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_vex_prefix): Use VEX256.
opcodes/
2009-12-15 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.h (VEX128): New.
(VEX256): Likewise.
2009-12-15 16:36:59 +00:00
4c807e7262
Reformat vex_len_table.
...
2009-12-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (vex_len_table): Reformat.
2009-12-15 01:42:57 +00:00
976f1fde11
Rename MOD_VEX_51 to MOD_VEX_50.
...
2009-12-14 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (MOD_VEX_51): Renamed to ...
(MOD_VEX_50): This.
(vex_table): Updated.
(mod_table): Likewise.
2009-12-14 20:22:16 +00:00
ab8e2090b6
PR binutils/10924
...
* arm-dis.c (arm_opcodes): Specify %R in cases where using r15
results in unpredictable behaviour.
(print_insn_arm): Handle %R.
* gas/arm/unpredictable.s: New test case - checks the disassembly
of instructions with unpredictable behaviour.
* gas/arm/unpredictable.d: New file - expected disassembly.
2009-12-14 16:38:23 +00:00
759a05ce24
Set vex.w to 0 for VEX C5 prefix.
...
2009-12-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (get_valid_dis386): Set vex.w to 0 for VEX C5
prefix.
(print_insn): Don't set vex.w here.
2009-12-12 01:17:41 +00:00
5639ff8726
2009-12-11 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-dis.c (print_insn): Set vex.w to 0.
2009-12-12 00:13:11 +00:00
02e647f941
2009-12-11 Quentin Neill <quentin.neill@amd.com>
...
gas/testsuite/
* gas/i386/fma4.d: Add test cases.
* gas/i386/fma4.s: Add test cases.
* gas/i386/x86-64-fma4.d: Add test cases.
* gas/i386/x86-64-fma4.s: Add test cases.
opcodes/
* i386-dis.c (get_vex_imm8): Extend logic to apply in all
cases, to avoid fetching ahead for the immediate bytes when
OP_E_memory has already been called. Fix indentation.
2009-12-11 20:38:51 +00:00
91d6fa6a03
Add -Wshadow to the gcc command line options used when compiling the binutils.
...
Fix up all warnings generated by the addition of this switch.
2009-12-11 13:42:17 +00:00
07a28fab11
PR 10924
...
* arm-dis.c (print_insn_arm): Mark insns that use the PC in
post-indexed addressing as unpredictable.
2009-12-09 08:38:04 +00:00
eacc9c891d
Support fxsave64 and fxrstor64.
...
gas/testsuite/
2009-12-03 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel.
* gas/i386/rex.d: Updated for fxsave64.
* gas/i386/x86-64-fxsave-intel.d: New.
* gas/i386/x86-64-fxsave.d: Likewise.
* gas/i386/x86-64-fxsave.s: Likewise.
opcodes/
2009-12-03 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (FXSAVE_Fixup): New.
(FXSAVE): Likewise.
(mod_table): Use FXSAVE on fxsave and fxrstor.
* i386-opc.tbl: Add fxsave64 and fxrstor64.
* i386-tbl.h: Regenerated.
2009-12-04 07:51:41 +00:00
03ee1b7f8e
PR gas/11013
...
* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB
and QDSUB.
* gas/arm/arch7em.d: Update expected disassembly.
* gas/arm/thumb32.d: Likewise.
* config/tc-arm.c (do_t_simd2): New function.
(insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
2009-12-02 20:26:30 +00:00
ee9fd255b7
PR gas/11030
...
* m68k-opc.c (m68k_opcodes): Allow the STLDSR instruction on the
Coldfire ISA A+.
2009-11-30 14:45:30 +00:00
ccc5981b93
2009-11-17 Quentin Neill <quentin.neill@amd.com>
...
Sebastian Pop <sebastian.pop@amd.com>
gas/testsuite/
* gas/i386/x86-64-fma4.d: Add new patterns.
* gas/i386/x86-64-fma4.s: Same.
* gas/i386/x86-64-xop.d: Adjusted.
opcodes/
* i386-dis.c (get_vex_imm8): Increase bytes_before_imm when
decoding the second source operand from the immediate byte.
(OP_EX_VexW): Pass an extra integer to identify the second
and third source arguments.
2009-11-25 15:15:30 +00:00
18d0c96eb9
Allow lock on cmpxch16b.
...
gas/testsuite/
2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/lock-1.s: Add cmpxchg16b test.
* gas/i386/lock-1-intel.d: Updated.
* gas/i386/lock-1.d: Likewise.
opcodes/
2009-11-19 H.J. Lu <hongjiu.lu@intel.com>
* i386-opc.tbl: Add IsLockable to cmpxch16b.
* i386-tbl.h: Regenerated.
2009-11-19 15:26:42 +00:00
945ee43039
PR binutils/10924
...
* gas/arm/arch4t-eabi.d: Restore previous expected dissambly of
instructions using Immediate Offset addressing with an offset of
zero.
* gas/arm/arch4t.d: Likewise.
* gas/arm/arm7t.d: Likewise.
* gas/arm/xscale.d: Likewise.
* gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and
tst instructions.
PR binutils/10924
* arm-dis.c (print_insn_arm): Do not print an offset of zero when
decoding Immediaate Offset addressing.
2009-11-19 14:07:11 +00:00
41effecb2d
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
...
opcodes/
PR binutils/10973
* i386-dis.c (get_vex_imm8): Do not increment codep.
Avoid incrementing bytes_before_imm when OP_E_memory
has already forwarded the codep pointer.
(OP_EX_VexW): Increment codep to skip mod/rm byte.
gas/testsuite/
* gas/i386/x86-64-xop.d: Update patterns.
2009-11-19 07:08:39 +00:00
f0ae4a24b0
2009-11-18 Sebastian Pop <sebastian.pop@amd.com>
...
gas/
* config/tc-i386.c (cpu_arch): Remove cvt16.
(md_show_usage): Same.
* doc/c-i386.texi: Same.
gas/testsuite/
* gas/i386/cvt16.d: Removed.
* gas/i386/cvt16.s: Removed.
* gas/i386/x86-64-cvt16.d: Removed.
* gas/i386/x86-64-cvt16.s: Removed.
* gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests.
opcodes/
* i386-dis.c (VEX_LEN_XOP_08_A0): Removed.
(VEX_LEN_XOP_08_A1): Removed.
(xop_table): Remove entries for VEX_LEN_XOP_08_A0 and
VEX_LEN_XOP_08_A1.
(vex_len_table): Same.
* i386-gen.c (CPU_CVT16_FLAGS): Removed.
(cpu_flags): Remove field for CpuCVT16.
* i386-opc.h (CpuCVT16): Removed.
(i386_cpu_flags): Remove bitfield cpucvt16.
(i386-opc.tbl): Remove CVT16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2009-11-18 20:28:59 +00:00
5dd85c9970
2009-11-17 Sebastian Pop <sebastian.pop@amd.com>
...
Quentin Neill <quentin.neill@amd.com>
gas/
* config/tc-i386.c (cpu_arch): Added .xop and .cvt16.
(build_vex_prefix): Handle xop08.
(md_assemble): Don't special case the constant 3 for insns using MODRM.
(build_modrm_byte): Handle vex2sources.
(md_show_usage): Add xop and cvt16.
* doc/c-i386.texi: Document fma4, xop, and cvt16.
gas/testsuite/
* gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode.
Run x86-64-xop and x86-64-cvt16 in 64-bit mode.
* gas/i386/lwp.d: Update name of the testcase.
* gas/i386/x86-64-xop.d: New.
* gas/i386/x86-64-xop.s: New.
* gas/i386/xop.d: New.
* gas/i386/xop.s: New.
* gas/i386/cvt16.d: New.
* gas/i386/cvt16.s: New.
opcodes/
* i386-dis.c (OP_Vex_2src_1): New.
(OP_Vex_2src_2): New.
(Vex_2src_1): New.
(Vex_2src_2): New.
(XOP_08): Added.
(VEX_LEN_XOP_08_A0): Added.
(VEX_LEN_XOP_08_A1): Added.
(VEX_LEN_XOP_09_80): Added.
(VEX_LEN_XOP_09_81): Added.
(xop_table): Added an entry for XOP_08. Handle xop instructions.
(vex_len_table): Added entries for VEX_LEN_XOP_08_A0,
VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81.
(get_valid_dis386): Handle XOP_08.
(OP_Vex_2src): New.
* i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS.
(cpu_flags): Add CpuXOP and CpuCVT16.
(opcode_modifiers): Add XOP08, Vex2Sources.
* i386-opc.h (CpuXOP): Added.
(CpuCVT16): Added.
(i386_cpu_flags): Add cpuxop and cpucvt16.
(XOP08): Added.
(Vex2Sources): Added.
(i386_opcode_modifier): Add xop08, vex2sources.
* i386-opc.tbl: Add entries for XOP and CVT16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Regenerated.
2009-11-18 04:04:17 +00:00
aefd8a406c
* gas/arm/vfma1.d: Only run on ELF based targets.
...
PR binutils/10924
* gas/arm/arch4t-eabi.d: Update expected disassembly.
* gas/arm/arch4t.d: Likewise.
* gas/arm/archv6t2.d: Likewise.
* gas/arm/arm7t.d: Likewise.
* gas/arm/inst.d: Likewise.
* gas/arm/xscale.d: Likewise.
PR binutils/10924
* arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB
instruction variants. Add pattern for MRS variant that was being
confused with CMP.
(arm_decode_shift): Place error message in a comment.
(print_insn_arm): Note that writing back to the PC is
unpredictable.
Only print 'p' variants of cmp/cmn/teq/tst instructions if
decoding for pre-V6 architectures.
2009-11-17 17:20:26 +00:00
0bb027fd62
2009-11-17 Edward Nevill <edward.nevill@arm.com>
...
* arm-dis.c (print_insn_thumb32): Handle undefined instruction.
2009-11-17 10:43:09 +00:00
c7e770a030
opcodes/
...
* Makefile.am (stamp-xc16x): Use ../cpu/xc16x.cpu instead of
../cgen/cpu.
* Makefile.in: Regenerate.
cgen/
* cpu/xc16x.cpu: Delete, use copy in ../cpu.
* cpu/xc16x.opc: Ditto.
2009-11-14 20:04:58 +00:00
8b3f93e7a1
2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-dis.c (OP_E_extended): Removed.
2009-11-14 07:22:05 +00:00
2a70cca486
Check rex_ignored.
...
gas/testsuite/
2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/rex.s: Add a test for VEX insn.
* gas/i386/rex.d: Updated.
opcodes/
2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (print_insn): Check rex_ignored.
2009-11-13 23:13:48 +00:00
f16cd0d502
Rewrite prefix processing.
...
gas/testsuite/
2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run long-1, long-1-intel, x86-64-long-1,
and x86-64-long-1-intel.
* gas/i386/long-1-intel.d: New.
* gas/i386/long-1.d: Likewise.
* gas/i386/long-1.s: Likewise.
* gas/i386/x86-64-long-1-intel.d: Likewise.
* gas/i386/x86-64-long-1.d: Likewise.
* gas/i386/x86-64-long-1.s: Likewise.
* gas/i386/jump16.d: Updated for prefix processing.
* gas/i386/naked.d: Likewise.
* gas/i386/nops-1-core2.d: Likewise.
* gas/i386/nops-1-i686.d: Likewise.
* gas/i386/nops-3-i686.d: Likewise.
* gas/i386/nops-4-i686.d: Likewise.
* gas/i386/nops-5-i686.d: Likewise.
* gas/i386/nops-5.d: Likewise.
* gas/i386/prefix.d: Likewise.
* gas/i386/rep.d: Likewise.
* gas/i386/string-ok.d: Likewise.
* gas/i386/x86-64-addr32-intel.d: Likewise.
* gas/i386/x86-64-addr32.d: Likewise.
* gas/i386/x86-64-cbw-intel.d: Likewise.
* gas/i386/x86-64-cbw.d: Likewise.
* gas/i386/x86-64-io-intel.d: Likewise.
* gas/i386/x86-64-io-suffix.d: Likewise.
* gas/i386/x86-64-io.d: Likewise.
* gas/i386/x86-64-lwp.d: Likewise.
* gas/i386/x86-64-nops-1-core2.d: Likewise.
* gas/i386/x86-64-nops-1-nocona.d: Likewise.
* gas/i386/x86-64-nops-1.d: Likewise.
* gas/i386/x86-64-nops-2.d: Likewise.
* gas/i386/x86-64-nops-3.d: Likewise.
* gas/i386/x86-64-nops-4-core2.d: Likewise.
* gas/i386/x86-64-nops-4.d: Likewise.
* gas/i386/x86-64-nops-5-k8.d: Likewise.
* gas/i386/x86-64-nops-5.d: Likewise.
* gas/i386/x86-64-rep.d: Likewise.
* gas/i386/x86-64-stack-intel.d: Likewise.
* gas/i386/x86-64-stack-suffix.d: Likewise.
* gas/i386/x86-64-stack.d: Likewise.
ld/testsuite/
2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
* ld-x86-64/tlsbin.dd: Updated for prefix processing.
* ld-x86-64/tlsgdesc.dd: Likewise.
* ld-x86-64/tlsld1.dd: Likewise.
* ld-x86-64/tlspic.dd: Likewise.
opcodes/
2009-11-13 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (ckprefix): Updated to return 0 if number of
prefixes > 14 and record the last position for each prefix.
(lock_prefix): Removed.
(data_prefix): Likewise.
(addr_prefix): Likewise.
(repz_prefix): Likewise.
(repnz_prefix): Likewise.
(last_lock_prefix): New.
(last_repz_prefix): Likewise.
(last_repnz_prefix): Likewise.
(last_data_prefix): Likewise.
(last_addr_prefix): Likewise.
(last_rex_prefix): Likewise.
(last_seg_prefix): Likewise.
(MAX_CODE_LENGTH): Likewise.
(ADDR16_PREFIX): Likewise.
(ADDR32_PREFIX): Likewise.
(DATA16_PREFIX): Likewise.
(DATA32_PREFIX): Likewise.
(REP_PREFIX): Likewise.
(seg_prefix): Likewise.
(all_prefixes): Change size to MAX_CODE_LENGTH - 1.
(prefix_name): Handle ADDR16_PREFIX, ADDR32_PREFIX,
DATA16_PREFIX, DATA32_PREFIX and REP_PREFIX.
(get_valid_dis386): Updated.
(OP_C): Likewise.
(OP_Monitor): Likewise.
(REP_Fixup): Likewise.
(print_insn): Display all prefixes.
(putop): Set PREFIX_DATA on used_prefixes only if it is used.
(intel_operand_size): Likewise.
(OP_E_register): Likewise.
(OP_G): Likewise.
(OP_REG): Likewise.
(OP_IMREG): Likewise.
(OP_I): Likewise.
(OP_I64): Likewise.
(OP_sI): Likewise.
(CRC32_Fixup): Likewise.
(MOVBE_Fixup): Likewise.
(OP_E_memory): Set REFIX_DATA on used_prefixes when it is used
in 16bit mode.
(OP_J): Set REX_W used if it is used. Set PREFIX_DATA on
used_prefixes only if it is used.
2009-11-13 20:42:10 +00:00
20efc68957
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
...
* i386-opc.tbl: Remove IsLockable from add, adc, and, dec, inc,
or, sbb, sub, xor and xchg with register only operands.
* i386-tbl.h: Regenerated.
2009-11-12 19:15:18 +00:00
c32fa91d70
gas/
...
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (LOCKREP_PREFIX): Removed.
(REP_PREFIX): New.
(LOCK_PREFIX): Likewise.
(PREFIX_GROUP): Likewise.
(REX_PREFIX): Updated.
(MAX_PREFIXES): Likewise.
(add_prefix): Updated. Return enum PREFIX_GROUP.
(md_assemble): Check for lock without a lockable instruction.
(parse_insn): Updated.
(output_insn): Likewise.
gas/testsuite/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1,
x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1.
* gas/i386/lock-1-intel.d: New.
* gas/i386/lock-1.d: Likewise.
* gas/i386/lock-1.s: Likewise.
* gas/i386/lockbad-1.l: Likewise.
* gas/i386/lockbad-1.s: Likewise.
* gas/i386/x86-64-lock-1-intel.d: Likewise.
* gas/i386/x86-64-lock-1.d: Likewise.
* gas/i386/x86-64-lock-1.s: Likewise.
* gas/i386/x86-64-lockbad-1.l: Likewise.
* gas/i386/x86-64-lockbad-1.s: Likewise.
opcodes/
2009-11-12 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (opcode_modifiers): Add IsLockable.
* i386-opc.h (IsLockable): New.
(i386_opcode_modifier): Add islockable.
* i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr,
bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub,
xor, xadd and xchg.
* i386-tbl.h: Regenerated.
2009-11-12 18:57:14 +00:00
79862e4574
gas/testsuite/
...
* gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d,
gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions
and expanded PC-relative offsets.
opcodes/
* arm-dis.c (coprocessor_opcodes): Use %A instead of %C. Remove
generic coprocessor instructions for FPA loads and stores.
(print_insn_coprocessor): Remove %C support. Display address for
PC-relative offsets in %A.
2009-11-12 14:49:45 +00:00
f310f33d50
gas/testsuite/
...
2009-11-11 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/prefix.d: Swap order of ADDR and REP prefixes.
* gas/i386/rep.d: Likewise.
* gas/i386/x86-64-rep.d: Likewise.
opcodes/
2009-11-11 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (all_prefixes): New.
(ckprefix): Set all_prefixes.
(print_insn): Print all_prefixes instead of lock_prefix,
repz_prefix, repnz_prefix, addr_prefix and data_prefix.
2009-11-12 02:13:06 +00:00
c1e2689731
PR binutils/10924
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* arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro.
(print_insn_arm): Extend %s format control code to check for
unpredictable addressing modes. Add support for %S format control
code which suppresses this check.
(W_BIT, I_BIT, U_BIT, P_BIT): New macros.
(WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET,
PRE_BIT_SET): New macros.
(print_insn_coprocessor): Use the new macros instead of magic
constants.
(print_arm_address): Likewise.
(pirnt_insn_arm): Likewise.
(print_insn_thumb32): Likewise.
2009-11-11 09:44:45 +00:00
41327c9d6d
Updated Indonesian translation.
2009-11-11 09:36:08 +00:00
0d999f3337
* config/m68k-parse.h (enum m68k_register): Add ACR[4-7], RGPIOBAR.
...
* config/tc-m68k.c (mcf5206_ctrl): Fix whitespace.
(mcf52223_ctrl): Remove non-existent registers.
(mcf54418): Define.
(mcf54455): Remove MBAR.
(m68k_cpus): Add lines for MCF5441x family.
(m68k_ip, init_table): Handle RGPIOBAR, ACR[4-7].
* m68k-dis.c (print_insn_arg): Handle RGPIOBAR, ACR[4-7] and MBAR[01].
2009-11-10 18:05:24 +00:00
Doug Evans
Nick Clifton
Alan Modra
H.J. Lu
Sebastian Pop
Ramana Radhakrishnan
Daniel Jacobowitz
Maxim Kuvyrkov