gcc/libgcc/longlong.h

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1991-12-24 05:31:09 +01:00
/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
Free Software Foundation, Inc.
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This file is part of the GNU C Library.
The GNU C Library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
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License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
In addition to the permissions in the GNU Lesser General Public
License, the Free Software Foundation gives you unlimited
permission to link the compiled version of this file into
combinations with other programs, and to distribute those
combinations without any restriction coming from the use of this
file. (The Lesser General Public License restrictions do apply in
other respects; for example, they cover modification of the file,
and distribution when not linked into a combine executable.)
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The GNU C Library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
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You should have received a copy of the GNU Lesser General Public
License along with the GNU C Library; if not, write to the Free
Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
MA 02110-1301, USA. */
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/* You have to define the following before including this file:
UWtype -- An unsigned type, default type for operations (typically a "word")
UHWtype -- An unsigned type, at least half the size of UWtype.
UDWtype -- An unsigned type, at least twice as large a UWtype
W_TYPE_SIZE -- size in bits of UWtype
UQItype -- Unsigned 8 bit type.
SItype, USItype -- Signed and unsigned 32 bit types.
DItype, UDItype -- Signed and unsigned 64 bit types.
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On a 32 bit machine UWtype should typically be USItype;
on a 64 bit machine, UWtype should typically be UDItype. */
#define __BITS4 (W_TYPE_SIZE / 4)
#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
#ifndef W_TYPE_SIZE
#define W_TYPE_SIZE 32
#define UWtype USItype
#define UHWtype USItype
#define UDWtype UDItype
#endif
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/* Used in glibc only. */
#ifndef attribute_hidden
#define attribute_hidden
#endif
extern const UQItype __clz_tab[256] attribute_hidden;
/* Define auxiliary asm macros.
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1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
word product in HIGH_PROD and LOW_PROD.
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2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
UDWtype product. This is just a variant of umul_ppmm.
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3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
denominator) divides a UDWtype, composed by the UWtype integers
HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
than DENOMINATOR for correct operation. If, in addition, the most
significant bit of DENOMINATOR must be 1, then the pre-processor symbol
UDIV_NEEDS_NORMALIZATION is defined to 1.
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4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
denominator). Like udiv_qrnnd but the numbers are signed. The quotient
is rounded towards 0.
5) count_leading_zeros(count, x) counts the number of zero-bits from the
msb to the first nonzero bit in the UWtype X. This is the number of
steps X needs to be shifted left to set the msb. Undefined for X == 0,
unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
from the least significant end.
7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
high_addend_2, low_addend_2) adds two UWtype integers, composed by
HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
(i.e. carry out) is not stored anywhere, and is lost.
8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
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and is lost.
If any of these macros are left undefined for a particular CPU,
C macros are used. */
/* The CPUs come in alphabetical order below.
Please add support for more CPUs here, or improve the current support
for the CPUs below!
(E.g. WE32100, IBM360.) */
#if defined (__GNUC__) && !defined (NO_ASM)
/* We sometimes need to clobber "cc" with gcc2, but that would not be
understood by gcc1. Use cpp to avoid major code duplication. */
#if __GNUC__ < 2
#define __CLOBBER_CC
#define __AND_CLOBBER_CC
#else /* __GNUC__ >= 2 */
#define __CLOBBER_CC : "cc"
#define __AND_CLOBBER_CC , "cc"
#endif /* __GNUC__ < 2 */
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#if defined (__alpha) && W_TYPE_SIZE == 64
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
(ph) = __builtin_alpha_umulh (__m0, __m1); \
(pl) = __m0 * __m1; \
} while (0)
#define UMUL_TIME 46
#ifndef LONGLONG_STANDALONE
#define udiv_qrnnd(q, r, n1, n0, d) \
do { UDItype __r; \
(q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
(r) = __r; \
} while (0)
extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
#define UDIV_TIME 220
#endif /* LONGLONG_STANDALONE */
#ifdef __alpha_cix__
#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
#define COUNT_LEADING_ZEROS_0 64
#else
#define count_leading_zeros(COUNT,X) \
do { \
UDItype __xr = (X), __t, __a; \
__t = __builtin_alpha_cmpbge (0, __xr); \
__a = __clz_tab[__t ^ 0xff] - 1; \
__t = __builtin_alpha_extbl (__xr, __a); \
(COUNT) = 64 - (__clz_tab[__t] + __a*8); \
} while (0)
#define count_trailing_zeros(COUNT,X) \
do { \
UDItype __xr = (X), __t, __a; \
__t = __builtin_alpha_cmpbge (0, __xr); \
__t = ~__t & -~__t; \
__a = ((__t & 0xCC) != 0) * 2; \
__a += ((__t & 0xF0) != 0) * 4; \
__a += ((__t & 0xAA) != 0); \
__t = __builtin_alpha_extbl (__xr, __a); \
__a <<= 3; \
__t &= -__t; \
__a += ((__t & 0xCC) != 0) * 2; \
__a += ((__t & 0xF0) != 0) * 4; \
__a += ((__t & 0xAA) != 0); \
(COUNT) = __a; \
} while (0)
#endif /* __alpha_cix__ */
#endif /* __alpha */
#if defined (__arc__) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \
"rIJ" ((USItype) (bh)), \
"%r" ((USItype) (al)), \
"rIJ" ((USItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \
"rIJ" ((USItype) (bh)), \
"r" ((USItype) (al)), \
"rIJ" ((USItype) (bl)))
i * libgcc1-test.c, libgcc1.c, config/i386/perform.h: Delete file. * testsuite/gcc.dg/complete-port.c: New (revised version of libgcc1-test.c) * po/POTFILES.in: Remove libgcc1-test.c and libgcc1.c. * Makefile.in: Delete variables: OLDCC, CCLIBFLAGS, OLDAR, OLDAR_FLAGS, LIBGCC1, LIBGCC1_TEST, CROSS_LIBGCC1, LIB1FUNCS, and LIB1FUNCS_EXTRA. Delete rules: libgcc1-test, libgcc1-test.o. Clarify commentary now that libgcc1 no longer exists. * cross-make: Don't set LIBGCC1. * mklibgcc.in: Delete all code for building from libgcc1.c. Always honor LIB1ASMFUNCS if set. * crtstuff.c, floatlib.c, longlong.h, config/fp-bit.c, config/arc/lib1funcs.asm, config/arm/lib1funcs.asm, config/d30v/libgcc1.asm, config/fr30/lib1funcs.asm, config/h8300/lib1funcs.asm, config/i386/cygwin.asm, config/i386/uwin.asm, config/m68hc11/larith.asm, config/m68k/lb1sf68.asm, config/mcore/lib1.asm, config/mn10200/lib1funcs.asm, config/sh/lib1funcs.asm, config/sparc/lb1spc.asm, config/sparc/lb1spl.asm, config/v850/lib1funcs.asm, config/c4x/libgcc.S: Delete or update references to libgcc1 in commentary. * config/t-libc-ok, config/t-linux, config/t-linux-aout, config/t-netbsd, config/a29k/t-a29kbare, config/a29k/t-vx29k, config/alpha/t-interix, config/alpha/t-osf, config/alpha/t-vms, config/arc/t-arc, config/arm/t-arm-aout, config/arm/t-arm-coff, config/arm/t-arm-elf, config/arm/t-linux, config/arm/t-pe, config/arm/t-semi, config/arm/t-strongarm-coff, config/arm/t-strongarm-elf, config/arm/t-strongarm-pe, config/arm/t-xscale-coff, config/arm/t-xscale-elf, config/avr/t-avr, config/c4x/t-c4x, config/d30v/t-d30v, config/fr30/t-fr30, config/h8300/t-h8300, config/i386/t-beos, config/i386/t-cygwin, config/i386/t-i386elf, config/i386/t-interix, config/i386/t-netware, config/i386/t-next, config/i386/t-rtems-i386, config/i386/t-sol2, config/i960/t-960bare, config/i960/t-vxworks960, config/ia64/t-ia64, config/m32r/t-m32r, config/m68hc11/t-m68hc11-gas, config/m68k/t-lynx, config/m68k/t-m68kbare, config/m68k/t-m68kelf, config/m68k/t-mot3300-gald, config/m68k/t-mot3300-gas, config/m68k/t-next, config/m68k/t-vxworks68, config/m88k/t-bug, config/m88k/t-dgux, config/m88k/t-dgux-gas, config/m88k/t-dguxbcs, config/m88k/t-luna, config/m88k/t-luna-gas, config/m88k/t-m88k, config/m88k/t-m88k-gas, config/m88k/t-sysv4, config/mcore/t-mcore, config/mcore/t-mcore-pe, config/mips/t-bsd, config/mips/t-bsd-gas, config/mips/t-cross64, config/mips/t-ecoff, config/mips/t-elf, config/mips/t-iris6, config/mips/t-r3900, config/mips/t-svr3, config/mips/t-svr3-gas, config/mips/t-svr4, config/mips/t-svr4-gas, config/mips/t-ultrix, config/mn10200/t-mn10200, config/mn10300/t-mn10300, config/pa/t-linux, config/pa/t-linux64, config/pa/t-pa, config/pa/t-pa64, config/pa/t-pro, config/pdp11/t-pdp11, config/pj/t-pj, config/rs6000/t-aix43, config/rs6000/t-beos, config/rs6000/t-darwin, config/rs6000/t-newas, config/rs6000/t-ppccomm, config/rs6000/t-rs6000, config/sh/t-linux, config/sh/t-sh, config/sparc/t-chorus-elf, config/sparc/t-elf, config/sparc/t-sol2, config/sparc/t-sp86x, config/sparc/t-sparcbare, config/sparc/t-sparclite, config/sparc/t-splet, config/sparc/t-sunos41, config/sparc/t-vxsparc, config/sparc/t-vxsparc64, config/v850/t-v850: Don't set any of LIBGCC1, CROSS_LIBGCC1, or LIBGCC1_TEST. * config/alpha/alpha.h, config/i386/i386.h, config/i860/i860.h: Don't set FLOAT_VALUE_TYPE, FLOAT_ARG_TYPE, INTIFY, or FLOATIFY. * config/d30v/d30v.h: Don't mention LIBGCC_NEEDS_DOUBLE, FLOAT_VALUE_TYPE, FLOAT_ARG_TYPE, FLOATIFY, INTIFY, nongcc_SI_type, nongcc_word_type, or perform_* * config/i860/fx2800: Don't define perform_umodsi3 or perform_modsi3. * config/i386/386bsd.h, config/i386/beos-elf.h, config/i386/linux-aout.h, config/i386/linux-oldld.h, config/i386/linux.h, config/i386/mach.h, config/i386/netbsd.h, config/i386/openbsd.h, config/i386/osfrose.h, config/i386/rtemself.h: Don't include i386/perform.h. * config/a29k/t-a29k, config/arm/t-semiaof, config/i370/t-i370, config/i370/t-linux, config/i370/t-mvs, config/i370/t-oe, config/i386/t-djgpp, config/i386/t-i386bare, config/i386/t-vsta, config/ia64/t-hpux, config/mips/t-mips, config/mips/t-mips-gas, config/mips/t-osfrose, config/sparc/t-sp64, config/sparc/t-sunos40, config/vax/t-openbsd, config/vax/t-vax: Delete. * config.gcc: Remove references to deleted files. (arm-semi-aof): Use arm/t-semi for tmake_file. * gcc.texi, install.texi, invoke.texi, tm.texi: Delete or rewrite text which is no longer relevant now that libgcc1 no longer exists. * config/t-openbsd, config/alpha/t-interix, config/i386/t-interix: No need to set INSTALL_ASSERT_H. (Missed in previous sweep.) From-SVN: r42188
2001-05-17 05:16:18 +02:00
/* Call libgcc routine. */
#define umul_ppmm(w1, w0, u, v) \
do { \
DWunion __w; \
__w.ll = __umulsidi3 (u, v); \
w1 = __w.s.high; \
w0 = __w.s.low; \
} while (0)
#define __umulsidi3 __umulsidi3
UDItype __umulsidi3 (USItype, USItype);
#endif
backport: re PR target/12476 (ARM/THUMB thunk calls broken) Merge from csl-arm-branch. 2004-01-30 Paul Brook <paul@codesourcery.com> * aof.h (REGISTER_NAMES): Add vfp reg names (ADDITIONAL_REGISTER_NAMES): Ditto. * aout.h (REGISTER_NAMES): Ditto. (ADDITIONAL_REGISTER_NAMES): Ditto. * arm-protos.h: Update/Add Prototypes. * arm.c (init_fp_table): Rename from init_fpa_table. Update users. Only allow 0.0 for VFP. (fp_consts_inited): Rename from fpa_consts_inited. Update users. (values_fp): Rename from values_fpa. Update Users. (arm_const_double_rtx): Rename from const_double_rtx_ok_for_fpa. Update users. Only check valid constants for this hardware. (arm_float_rhs_operand): Rename from fpa_rhs_operand. Update Users. Only allow consts for FPA. (arm_float_add_operand): Rename from fpa_add_operand. Update users. Only allow consts for FPA. (use_return_insn): Check for saved VFP regs. (arm_legitimate_address_p): Handle VFP DFmode addressing. (arm_legitimize_address): Ditto. (arm_general_register_operand): New function. (vfp_mem_operand): New function. (vfp_compare_operand): New function. (vfp_secondary_reload_class): New function. (arm_float_compare_operand): New function. (vfp_print_multi): New function. (vfp_output_fstmx): New function. (vfp_emit_fstm): New function. (arm_output_epilogue): Output VPF reg restore code. (arm_expand_prologue): Output VFP reg save code. (arm_print_operand): Add 'P'. (arm_hard_regno_mode_ok): Return modes for VFP regs. (arm_regno_class): Return classes for VFP regs. (arm_compute_initial_elimination_offset): Include space for VFP regs. (arm_get_frame_size): Ditto. * arm.h (FIXED_REGISTERS): Add VFP regs. (CALL_USED_REGISTERS): Ditto. (CONDITIONAL_REGISTER_USAGE): Enable VFP regs. (FIRST_VFP_REGNUM): Define. (LAST_VFP_REGNUM): Define. (IS_VFP_REGNUM): Define. (FIRST_PSEUDO_REGISTER): Include VFP regs. (HARD_REGNO_NREGS): Handle VFP regs. (REG_ALLOC_ORDER): Add VFP regs. (enum reg_class): Add VFP_REGS. (REG_CLASS_NAMES): Ditto. (REG_CLASS_CONTENTS): Ditto. (CANNOT_CHANGE_MODE_CLASS) Handle VFP Regs. (REG_CLASS_FROM_LETTER): Add 'w'. (EXTRA_CONSTRAINT_ARM): Add 'U'. (EXTRA_MEMORY_CONSTRAINT): Define. (SECONDARY_OUTPUT_RELOAD_CLASS): Handle VFP regs. (SECONDARY_INPUT_RELOAD_CLASS): Ditto. (REGISTER_MOVE_COST): Ditto. (PREDICATE_CODES): Add arm_general_register_operand, arm_float_compare_operand and vfp_compare_operand. * arm.md (various): Rename as above. (divsf3): Enable when TARGET_VFP. (divdf3): Ditto. (movdfcc): Ditto. (sqrtsf2): Ditto. (sqrtdf2): Ditto. (arm_movdi): Disable when TARGET_VFP. (arm_movsi_insn): Ditto. (movsi): Only split with general regs. (cmpsf): Use arm_float_compare_operand. (push_fp_multi): Restrict to TARGET_FPA. (vfp.md): Include. * vfp.md: New file. * fpa.md (various): Rename as above. * doc/md.texi: Document ARM w and U constraints. 2004-01-15 Paul Brook <paul@codesourcery.com> * config.gcc: Add with_fpu. Allow with-float=softfp. * config/arm/arm.c (arm_override_options): Rename *-s to *s. Break out of loop when we find a float-abi. Fix typo. * config/arm/arm.h (OPTION_DEFAULT_SPECS): Add "fpu". Set -mfloat-abi=. * doc/install.texi: Document --with-fpu. 2003-01-14 Paul Brook <paul@codesourcery.com> * config.gcc (with_arch): Add armv6. * config/arm/arm.h: Rename TARGET_CPU_*_s to TARGET_CPU_*s. * config/arm/arm.c (arm_overrride_options): Ditto. 2004-01-08 Richard Earnshaw <rearnsha@arm.com> * arm.c (FL_ARCH3M): Renamed from FL_FAST_MULT. (FL_ARCH6): Renamed from FL_ARCH6J. (arm_arch3m): Renamed from arm_fast_multiply. (arm_arch6): Renamed from arm_arch6j. * arm.h: Update all uses of above. * arm-cores.def: Likewise. * arm.md: Likewise. * arm.h (CPP_CPU_ARCH_SPEC): Emit __ARM_ARCH_6J__ define for armV6j, not arm6j. Add entry for arch armv6. 2004-01-07 Richard Earnshaw <rearnsha@arm.com> * arm.c (arm_emit_extendsi): Delete. * arm-protos.h (arm_emit_extendsi): Delete. * arm.md (zero_extendhisi2): Also handle zero-extension of non-subregs. (zero_extendqisi2, extendhisi2, extendqisi2): Likewise. (thumb_zero_extendhisi2): Only match if not v6. (arm_zero_extendhisi2, thumb_zero_extendqisi2, arm_zero_extendqisi2) (thumb_extendhisi2, arm_extendhisi2, arm_extendqisi) (thumb_extendqisi2): Likewise. (thumb_zero_extendhisi2_v6, arm_zero_extendhisi2_v6): New patterns. (thumb_zero_extendqisi2_v6, arm_zero_extendqisi2_v6): New patterns. (thumb_extendhisi2_insn_v6, arm_extendhisi2_v6): New patterns. (thumb_extendqisi2_v6, arm_extendqisi_v6): New patterns. (arm_zero_extendhisi2_reg, arm_zero_extendqisi2_reg): Delete. (arm_extendhisi2_reg, arm_extendqisi2_reg): Delete. (arm_zero_extendhisi2addsi): Remove subreg. Add attributes. (arm_zero_extendqisi2addsi, arm_extendhisi2addsi): Likewise. (arm_extendqisi2addsi): Likewise. 2003-12-31 Mark Mitchell <mark@codesourcery.com> Revert this change: * config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG + REG addressing modes. * config/arm/arm.h (THUMB_LEGTITIMIZE_RELOAD_ADDRESS): Reload REG + REG addressing modes. 2003-12-30 Mark Mitchell <mark@codesourcery.com> * config/arm/arm.h (THUMB_LEGITIMATE_CONSTANT_P): Accept CONSTANT_P_RTX. 2003-30-12 Paul Brook <paul@codesourcery.com> * longlong.h: protect arm inlines with !defined (__thumb__) 2003-30-12 Paul Brook <paul@codesourcery.com> * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Always define __arm__. 2003-12-30 Nathan Sidwell <nathan@codesourcery.com> * builtins.c (expand_builtin_apply_args_1): Fix typo in previous change. 2003-12-29 Nathan Sidwell <nathan@codesourcery.com> * builtins.c (expand_builtin_apply_args_1): Add pretend args size to the virtual incoming args pointer for downward stacks. 2003-12-29 Paul Brook <paul@codesourcery.com> * config/arm/arm-cores.def: Add cost function. * config/arm/arm.c (arm_*_rtx_costs): New functions. (arm_rtx_costs): Remove (struct processors): Add rtx_costs field. (all_cores, all_architectures): Ditto. (arm_override_options): Set targetm.rtx_costs. (thumb_rtx_costs): New function. (arm_rtx_costs_1): Remove cases handled elsewhere. * config/arm/arm.h (processor_type): Add COSTS parameter. 2003-12-29 Nathan Sidwell <nathan@codesourcery.com> * config/arm/arm.md (generic_sched): arm926 has its own scheduler. (arm926ejs.md): Include it. * config/arm/arm926ejs.md: New pipeline description. 2003-12-24 Paul Brook <paul@codesourcery.com> * config/arm/arm.c (arm_arch6j): New variable. (arm_override_options): Set it. (arm_emit_extendsi): New function. * config/arm/arm-protos.h (arm_emit_extendsi): Add prototype. * config/arm/arm.h (arm_arch6j): Declare. * config/arm/arm.md: Add sign/zero extend insns. 2003-12-23 Paul Brook <paul@codesourcery.com> * config/arm/arm.c (all_architectures): Add armv6. * doc/invoke.texi: Document it. 2003-12-19 Paul Brook <paul@codesourcery.com> * config/arm/arm.md: Add load1 and load_byte "type" attrs. Modify insn patterns to match. * config/arm/arm-generic.md: Ditto. * config/arm/cirrus.md: Ditto. * config/arm/fpa.md: Ditto. * config/amm/iwmmxt.md: Ditto. * config/arm/arm1026ejs.md: Ditto. * config/arm/arm1135jfs.md: Ditto. Add insn_reservation and bypasses for 11_loadb. 2003-12-18 Nathan Sidwell <nathan@codesourcery.com> * config/arm/arm-protos.h (arm_no_early_alu_shift_value_dep): Declare. * config/arm/arm.c (arm_adjust_cost): Check shift cost for TYPE_ALU_SHIFT and TYPE_ALU_SHIFT_REG. (arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Correctly deal with conditional execution, parallels and single shift operations. (arm_no_early_alu_shift_value_dep): Define. * arm.md (attr type): Replace 'normal' with 'alu', 'alu_shift' and 'alu_shift_reg'. (attr core_cycles): Adjust. (*addsi3_carryin_shift, andsi_not_shiftsi_si, *arm_shiftsi3, *shiftsi3_compare0, *notsi_shiftsi, *notsi_shiftsi_compare0, *not_shiftsi_compare0_scratch, *cmpsi_shiftsi, *cmpsi_shiftsi_swp, *cmpsi_neg_shiftsi, *arith_shiftsi, *arith_shiftsi_compare0, *arith_shiftsi_compare0_scratch, *sub_shiftsi, *sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch, *if_shift_move, *if_move_shift, *if_shift_shift): Set type attribute appropriately. * config/arm/arm1026ejs.md (alu_op): Adjust. (alu_shift_op, alu_shift_reg_op): New. * config/arm/arm1136.md: Add better bypasses for early registers. Remove load[234] and store[234] bypasses. (11_alu_op): Adjust. (11_alu_shift_op, 11_alu_shift_reg_op): New. 2003-12-15 Nathan Sidwell <nathan@codesourcery.com> * config/arm/arm-protos.h (arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Declare. * config/arm/arm.c (arm_no_early_store_addr_dep, arm_no_early_alu_shift_dep, arm_no_early_mul_dep): Define. * config/arm/arm1026ejs.md: Add load-store bypass. * config/arm/arm1136jfs.md (11_alu_op): Take 2 cycles. Add bypasses between instructions. 2003-12-10 Paul Brook <paul@codesourcery.com> * config/arm/arm.c (arm_fpu_model): New variable. (arm_fload_abi): New variable. (target_fpe_name): Rename from target_fp_name. (target_fpu_name): New variable. (arm_is_cirrus): Remove. (fpu_desc): New struct. (all_fpus): Define. (pf_model_for_fpu): Define. (all_loat_abis): Define. (arm_override_options): Set fp arch flags based on -mfpu= and -float-abi=. (FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM. (LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM. (*): Use new TARGET_* flags. * config/arm/arm.h (TARGET_ANY_HARD_FLOAT): Remove. (TARGET_HARD_FLOAT): No longer implies TARGET_FPA. (TARGET_SOFT_FLOAT): Ditto. (TARGET_SOFT_FLOAT_ABI): New. (TARGET_MAVERICK): Rename from TARGET_CIRRUS. No longer implies TARGET_HARD_FLOAT. (TARGET_VFP): No longer implies TARGET_HARD_FLOAT. (TARGET_OPTIONS): Add -mfpu=. (FIRST_FPA_REGNUM): Rename from FIRST_ARM_FP_REGNUM. (LAST_FPA_REGNUM): Rename from LAST_ARM_FP_REGNUM. (arm_pf_model): Define. (arm_float_abi_type): Define. (fputype): Add FPUTYPE_VFP. Change SOFT_FPA->NONE * config/arm/arm.md: Use new TARGET_* flags. * config/arm/cirrus.md: Ditto. * config/arm/fpa.md: Ditto. * config/arm/elf.h (ASM_SPEC): Pass -mfloat-abi= and -mfpu=. * config/arm/semi.h (ASM_SPEC): Ditto. * config/arm/netbsd-elf.h (SUBTARGET_ASM_FLOAT_SPEC): Specify vfp. (FPUTYPE_DEFAULT): Set to VFP. * doc/invoke.texi: Document -mfpu= and -mfloat-abi=. 2003-11-22 Phil Edwards <phil@codesourcery.com> PR target/12476 * config/arm/arm.c (arm_output_mi_thunk): In Thumb mode, use 'bx' instead of 'b' to avoid branch range restrictions. Output the thunk immediately before the thunked-to function. * config/arm/arm.h (ARM_DECLARE_FUNCTION_NAME): Do not emit .thumb_func if a thunk is being generated. Emit .code 16 along with .thumb_func if a thunk is not being generated. 2003-11-15 Nicolas Pitre <nico@cam.org> * config/arm/arm.md (ashldi3, arm_ashldi3_1bit, ashrdi3, arm_ashrdi3_1bit, lshrdi3, arm_lshrdi3_1bit): New patterns. * config/arm/iwmmxt.md (ashrdi3_iwmmxt): Renamed from ashrdi3. (lshrdi3_iwmmxt): Renamed from lshrdi3. * config/arm/arm.c (IWMMXT_BUILTIN2): Renamed argument accordingly. 2003-11-12 Steve Woodford <scw@wasabisystems.com> Ian Lance Taylor <ian@wasabisystems.com> * config/arm/lib1funcs.asm (ARM_DIV_BODY, ARM_MOD_BODY): Add new code for __ARM_ARCH__ >= 5 && ! defined (__OPTIMIZE_SIZE__). 2003-11-05 Phil Edwards <phil@codesourcery.com> * config/arm/arm.md (insn): Add new V6 instruction names. (generic_sched): New attr. * config/arm/arm-generic.md: Use generic_sched here. * config/arm/arm1026ejs.md: Do not model fetch/issue/decode stages of pipeline. Adjust latency counts accordingly. * config/arm/arm1136jfs.md: New file. 2003-10-28 Mark Mitchell <mark@codesourcery.com> * config/arm/arm.h (processor_type): New enumeration type. (CPP_ARCH_DEFAULT_SPEC): Set appropriately for ARM 926EJ-S, ARM1026EJ-S, ARM1136J-S, and ARM1136JF-S processor cores. (CPP_CPU_ARCH_SPEC): Likewise. * config/arm/arm.c (arm_tune): New variable. (all_cores): Use cores.def. (all_architectures): Add representative processor. (arm_override_options): Restructure way in which tuning information is deduced. * arm.md: Update "insn" and "type" attributes throughout. (insn): New attribute. (type): Compute "mult" from "insn" attribute. Add load2, load3, load4 alternatives. (arm automaton): Move to arm-generic.md. * config/arm/arm-cores.def: New file. * config/arm/arm-generic.md: Likewise. * config/arm/arm1026ejs.md: Likewise. From-SVN: r77171
2004-02-03 15:45:44 +01:00
#if defined (__arm__) && !defined (__thumb__) && W_TYPE_SIZE == 32
1991-12-24 05:31:09 +01:00
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
1996-07-03 20:43:21 +02:00
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%r" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"%r" ((USItype) (al)), \
"rI" ((USItype) (bl)) __CLOBBER_CC)
1991-12-24 05:31:09 +01:00
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
1996-07-03 20:43:21 +02:00
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "r" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"r" ((USItype) (al)), \
"rI" ((USItype) (bl)) __CLOBBER_CC)
#define umul_ppmm(xh, xl, a, b) \
{register USItype __t0, __t1, __t2; \
__asm__ ("%@ Inlined umul_ppmm\n" \
" mov %2, %5, lsr #16\n" \
" mov %0, %6, lsr #16\n" \
" bic %3, %5, %2, lsl #16\n" \
" bic %4, %6, %0, lsl #16\n" \
" mul %1, %3, %4\n" \
" mul %4, %2, %4\n" \
" mul %3, %0, %3\n" \
" mul %0, %2, %0\n" \
" adds %3, %4, %3\n" \
" addcs %0, %0, #65536\n" \
" adds %1, %1, %3, lsl #16\n" \
" adc %0, %0, %3, lsr #16" \
1996-07-04 00:07:53 +02:00
: "=&r" ((USItype) (xh)), \
"=r" ((USItype) (xl)), \
"=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
1996-07-04 00:07:53 +02:00
: "r" ((USItype) (a)), \
"r" ((USItype) (b)) __CLOBBER_CC );}
#define UMUL_TIME 20
#define UDIV_TIME 100
1991-12-24 05:31:09 +01:00
#endif /* __arm__ */
#if defined(__arm__)
/* Let gcc decide how best to implement count_leading_zeros. */
#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
#define COUNT_LEADING_ZEROS_0 32
#endif
#if defined (__AVR__)
#if W_TYPE_SIZE == 16
#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
#define COUNT_LEADING_ZEROS_0 16
#endif /* W_TYPE_SIZE == 16 */
#if W_TYPE_SIZE == 32
#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
#define COUNT_LEADING_ZEROS_0 32
#endif /* W_TYPE_SIZE == 32 */
#if W_TYPE_SIZE == 64
#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzll (X))
#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzll (X))
#define COUNT_LEADING_ZEROS_0 64
#endif /* W_TYPE_SIZE == 64 */
#endif /* defined (__AVR__) */
#if defined (__CRIS__) && __CRIS_arch_version >= 3
#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
#if __CRIS_arch_version >= 8
#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
#endif
#endif /* __CRIS__ */
#if defined (__hppa) && W_TYPE_SIZE == 32
1991-12-24 05:31:09 +01:00
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%rM" ((USItype) (ah)), \
"rM" ((USItype) (bh)), \
"%rM" ((USItype) (al)), \
"rM" ((USItype) (bl)))
1991-12-24 05:31:09 +01:00
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "rM" ((USItype) (ah)), \
"rM" ((USItype) (bh)), \
"rM" ((USItype) (al)), \
"rM" ((USItype) (bl)))
#if defined (_PA_RISC1_1)
#define umul_ppmm(w1, w0, u, v) \
do { \
union \
{ \
UDItype __f; \
struct {USItype __w1, __w0;} __w1w0; \
} __t; \
__asm__ ("xmpyu %1,%2,%0" \
: "=x" (__t.__f) \
1996-07-04 00:07:53 +02:00
: "x" ((USItype) (u)), \
"x" ((USItype) (v))); \
(w1) = __t.__w1w0.__w1; \
(w0) = __t.__w1w0.__w0; \
} while (0)
#define UMUL_TIME 8
#else
#define UMUL_TIME 30
#endif
#define UDIV_TIME 40
#define count_leading_zeros(count, x) \
do { \
USItype __tmp; \
__asm__ ( \
"ldi 1,%0\n" \
" extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
" extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
" ldo 16(%0),%0 ; Yes. Perform add.\n" \
" extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
" extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
" ldo 8(%0),%0 ; Yes. Perform add.\n" \
" extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
" extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
" ldo 4(%0),%0 ; Yes. Perform add.\n" \
" extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
" extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
" ldo 2(%0),%0 ; Yes. Perform add.\n" \
" extru %1,30,1,%1 ; Extract bit 1.\n" \
" sub %0,%1,%0 ; Subtract it.\n" \
: "=r" (count), "=r" (__tmp) : "1" (x)); \
} while (0)
1991-12-24 05:31:09 +01:00
#endif
#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH. * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (s390_return_addr_rtx): Likewise. (s390_back_chain_rtx): Likewise. (s390_frame_area): Likewise. (s390_frame_info): Likewise. (s390_initial_elimination_offset): Likewise. (save_gprs): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. (s390_function_arg_advance): Likewise. (s390_function_arg): Likewise. (s390_va_start): Likewise. (s390_gimplify_va_arg): Likewise. (s390_function_profiler): Likewise. (s390_optimize_prologue): Likewise. (s390_rtx_costs): Likewise. (s390_secondary_reload): Likewise. (s390_promote_function_mode): Likewise. (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH. (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit registers available. (s390_unwind_word_mode): New function. (s390_function_value): Split 64 bit values into register pair if used as return value. (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for function call parameters. Handle parallels. (TARGET_SCALAR_MODE_SUPPORTED_P): New macro. (HARD_REGNO_CALL_PART_CLOBBERED): New macro. (DWARF_CIE_DATA_ALIGNMENT): New macro. (s390_expand_setmem): Remove unused variable src_addr. * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to deal with 64 bit registers. * gcc/config/s390/s390.h: Define __zarch__ predefined macro. Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (UNITS_PER_LONG): New macro. * libjava/include/s390-signal.h: Define extended ucontext structure containing the upper halfs of the 64 bit registers. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r158257
2010-04-13 11:04:31 +02:00
#if !defined (__zarch__)
#define smul_ppmm(xh, xl, m0, m1) \
do { \
union {DItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__asm__ ("lr %N0,%1\n\tmr %0,%2" \
: "=&r" (__x.__ll) \
: "r" (m0), "r" (m1)); \
(xh) = __x.__i.__h; (xl) = __x.__i.__l; \
} while (0)
#define sdiv_qrnnd(q, r, n1, n0, d) \
do { \
union {DItype __ll; \
struct {USItype __h, __l;} __i; \
} __x; \
__x.__i.__h = n1; __x.__i.__l = n0; \
__asm__ ("dr %0,%2" \
: "=r" (__x.__ll) \
: "0" (__x.__ll), "r" (d)); \
(q) = __x.__i.__l; (r) = __x.__i.__h; \
} while (0)
s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH. * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (s390_return_addr_rtx): Likewise. (s390_back_chain_rtx): Likewise. (s390_frame_area): Likewise. (s390_frame_info): Likewise. (s390_initial_elimination_offset): Likewise. (save_gprs): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. (s390_function_arg_advance): Likewise. (s390_function_arg): Likewise. (s390_va_start): Likewise. (s390_gimplify_va_arg): Likewise. (s390_function_profiler): Likewise. (s390_optimize_prologue): Likewise. (s390_rtx_costs): Likewise. (s390_secondary_reload): Likewise. (s390_promote_function_mode): Likewise. (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH. (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit registers available. (s390_unwind_word_mode): New function. (s390_function_value): Split 64 bit values into register pair if used as return value. (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for function call parameters. Handle parallels. (TARGET_SCALAR_MODE_SUPPORTED_P): New macro. (HARD_REGNO_CALL_PART_CLOBBERED): New macro. (DWARF_CIE_DATA_ALIGNMENT): New macro. (s390_expand_setmem): Remove unused variable src_addr. * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to deal with 64 bit registers. * gcc/config/s390/s390.h: Define __zarch__ predefined macro. Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (UNITS_PER_LONG): New macro. * libjava/include/s390-signal.h: Define extended ucontext structure containing the upper halfs of the 64 bit registers. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r158257
2010-04-13 11:04:31 +02:00
#else
#define smul_ppmm(xh, xl, m0, m1) \
do { \
register SItype __r0 __asm__ ("0"); \
register SItype __r1 __asm__ ("1") = (m0); \
s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH. * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (s390_return_addr_rtx): Likewise. (s390_back_chain_rtx): Likewise. (s390_frame_area): Likewise. (s390_frame_info): Likewise. (s390_initial_elimination_offset): Likewise. (save_gprs): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. (s390_function_arg_advance): Likewise. (s390_function_arg): Likewise. (s390_va_start): Likewise. (s390_gimplify_va_arg): Likewise. (s390_function_profiler): Likewise. (s390_optimize_prologue): Likewise. (s390_rtx_costs): Likewise. (s390_secondary_reload): Likewise. (s390_promote_function_mode): Likewise. (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH. (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit registers available. (s390_unwind_word_mode): New function. (s390_function_value): Split 64 bit values into register pair if used as return value. (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for function call parameters. Handle parallels. (TARGET_SCALAR_MODE_SUPPORTED_P): New macro. (HARD_REGNO_CALL_PART_CLOBBERED): New macro. (DWARF_CIE_DATA_ALIGNMENT): New macro. (s390_expand_setmem): Remove unused variable src_addr. * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to deal with 64 bit registers. * gcc/config/s390/s390.h: Define __zarch__ predefined macro. Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (UNITS_PER_LONG): New macro. * libjava/include/s390-signal.h: Define extended ucontext structure containing the upper halfs of the 64 bit registers. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r158257
2010-04-13 11:04:31 +02:00
\
__asm__ ("mr\t%%r0,%3" \
: "=r" (__r0), "=r" (__r1) \
: "r" (__r1), "r" (m1)); \
(xh) = __r0; (xl) = __r1; \
s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH. * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (s390_return_addr_rtx): Likewise. (s390_back_chain_rtx): Likewise. (s390_frame_area): Likewise. (s390_frame_info): Likewise. (s390_initial_elimination_offset): Likewise. (save_gprs): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. (s390_function_arg_advance): Likewise. (s390_function_arg): Likewise. (s390_va_start): Likewise. (s390_gimplify_va_arg): Likewise. (s390_function_profiler): Likewise. (s390_optimize_prologue): Likewise. (s390_rtx_costs): Likewise. (s390_secondary_reload): Likewise. (s390_promote_function_mode): Likewise. (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH. (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit registers available. (s390_unwind_word_mode): New function. (s390_function_value): Split 64 bit values into register pair if used as return value. (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for function call parameters. Handle parallels. (TARGET_SCALAR_MODE_SUPPORTED_P): New macro. (HARD_REGNO_CALL_PART_CLOBBERED): New macro. (DWARF_CIE_DATA_ALIGNMENT): New macro. (s390_expand_setmem): Remove unused variable src_addr. * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to deal with 64 bit registers. * gcc/config/s390/s390.h: Define __zarch__ predefined macro. Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (UNITS_PER_LONG): New macro. * libjava/include/s390-signal.h: Define extended ucontext structure containing the upper halfs of the 64 bit registers. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r158257
2010-04-13 11:04:31 +02:00
} while (0)
s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH. * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (s390_return_addr_rtx): Likewise. (s390_back_chain_rtx): Likewise. (s390_frame_area): Likewise. (s390_frame_info): Likewise. (s390_initial_elimination_offset): Likewise. (save_gprs): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. (s390_function_arg_advance): Likewise. (s390_function_arg): Likewise. (s390_va_start): Likewise. (s390_gimplify_va_arg): Likewise. (s390_function_profiler): Likewise. (s390_optimize_prologue): Likewise. (s390_rtx_costs): Likewise. (s390_secondary_reload): Likewise. (s390_promote_function_mode): Likewise. (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH. (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit registers available. (s390_unwind_word_mode): New function. (s390_function_value): Split 64 bit values into register pair if used as return value. (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for function call parameters. Handle parallels. (TARGET_SCALAR_MODE_SUPPORTED_P): New macro. (HARD_REGNO_CALL_PART_CLOBBERED): New macro. (DWARF_CIE_DATA_ALIGNMENT): New macro. (s390_expand_setmem): Remove unused variable src_addr. * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to deal with 64 bit registers. * gcc/config/s390/s390.h: Define __zarch__ predefined macro. Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (UNITS_PER_LONG): New macro. * libjava/include/s390-signal.h: Define extended ucontext structure containing the upper halfs of the 64 bit registers. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r158257
2010-04-13 11:04:31 +02:00
#define sdiv_qrnnd(q, r, n1, n0, d) \
do { \
register SItype __r0 __asm__ ("0") = (n1); \
register SItype __r1 __asm__ ("1") = (n0); \
s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH. * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (s390_return_addr_rtx): Likewise. (s390_back_chain_rtx): Likewise. (s390_frame_area): Likewise. (s390_frame_info): Likewise. (s390_initial_elimination_offset): Likewise. (save_gprs): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. (s390_function_arg_advance): Likewise. (s390_function_arg): Likewise. (s390_va_start): Likewise. (s390_gimplify_va_arg): Likewise. (s390_function_profiler): Likewise. (s390_optimize_prologue): Likewise. (s390_rtx_costs): Likewise. (s390_secondary_reload): Likewise. (s390_promote_function_mode): Likewise. (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH. (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit registers available. (s390_unwind_word_mode): New function. (s390_function_value): Split 64 bit values into register pair if used as return value. (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for function call parameters. Handle parallels. (TARGET_SCALAR_MODE_SUPPORTED_P): New macro. (HARD_REGNO_CALL_PART_CLOBBERED): New macro. (DWARF_CIE_DATA_ALIGNMENT): New macro. (s390_expand_setmem): Remove unused variable src_addr. * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to deal with 64 bit registers. * gcc/config/s390/s390.h: Define __zarch__ predefined macro. Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (UNITS_PER_LONG): New macro. * libjava/include/s390-signal.h: Define extended ucontext structure containing the upper halfs of the 64 bit registers. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r158257
2010-04-13 11:04:31 +02:00
\
__asm__ ("dr\t%%r0,%4" \
: "=r" (__r0), "=r" (__r1) \
: "r" (__r0), "r" (__r1), "r" (d)); \
(q) = __r1; (r) = __r0; \
s390.md: Replace TARGET_64BIT with TARGET_ZARCH. 2010-04-13 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> Ulrich Weigand <Ulrich.Weigand@de.ibm.com> * gcc/config/s390/s390.md: Replace TARGET_64BIT with TARGET_ZARCH. * gcc/config/s390/s390.c: Replace UNTIS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (s390_return_addr_rtx): Likewise. (s390_back_chain_rtx): Likewise. (s390_frame_area): Likewise. (s390_frame_info): Likewise. (s390_initial_elimination_offset): Likewise. (save_gprs): Likewise. (s390_emit_prologue): Likewise. (s390_emit_epilogue): Likewise. (s390_function_arg_advance): Likewise. (s390_function_arg): Likewise. (s390_va_start): Likewise. (s390_gimplify_va_arg): Likewise. (s390_function_profiler): Likewise. (s390_optimize_prologue): Likewise. (s390_rtx_costs): Likewise. (s390_secondary_reload): Likewise. (s390_promote_function_mode): Likewise. (s390_hard_regno_mode_ok): Replace TARGET_64BIT with TARGET_ZARCH. (s390_scalar_mode_supported_p): Disallow TImode if no 64 bit registers available. (s390_unwind_word_mode): New function. (s390_function_value): Split 64 bit values into register pair if used as return value. (s390_call_saved_register_used): Don't use HARD_REGNO_NREGS for function call parameters. Handle parallels. (TARGET_SCALAR_MODE_SUPPORTED_P): New macro. (HARD_REGNO_CALL_PART_CLOBBERED): New macro. (DWARF_CIE_DATA_ALIGNMENT): New macro. (s390_expand_setmem): Remove unused variable src_addr. * gcc/longlong.h: Make smul_ppmm and sdiv_qrnnd inline asms to deal with 64 bit registers. * gcc/config/s390/s390.h: Define __zarch__ predefined macro. Replace UNITS_PER_WORD with UNITS_PER_LONG where it is ABI relevant. (UNITS_PER_LONG): New macro. * libjava/include/s390-signal.h: Define extended ucontext structure containing the upper halfs of the 64 bit registers. Co-Authored-By: Ulrich Weigand <uweigand@de.ibm.com> From-SVN: r158257
2010-04-13 11:04:31 +02:00
} while (0)
#endif /* __zarch__ */
#endif
#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
1991-12-24 05:31:09 +01:00
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
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: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
1991-12-24 05:31:09 +01:00
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
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: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"1" ((USItype) (al)), \
"g" ((USItype) (bl)))
1991-12-24 05:31:09 +01:00
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mul{l} %3" \
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: "=a" ((USItype) (w0)), \
"=d" ((USItype) (w1)) \
: "%0" ((USItype) (u)), \
"rm" ((USItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, dv) \
__asm__ ("div{l} %4" \
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: "=a" ((USItype) (q)), \
"=d" ((USItype) (r)) \
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
"rm" ((USItype) (dv)))
#define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
#define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
#define UMUL_TIME 40
#define UDIV_TIME 40
1991-12-24 05:31:09 +01:00
#endif /* 80x86 */
#if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
: "=r" ((UDItype) (sh)), \
"=&r" ((UDItype) (sl)) \
: "%0" ((UDItype) (ah)), \
"rme" ((UDItype) (bh)), \
"%1" ((UDItype) (al)), \
"rme" ((UDItype) (bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
: "=r" ((UDItype) (sh)), \
"=&r" ((UDItype) (sl)) \
: "0" ((UDItype) (ah)), \
"rme" ((UDItype) (bh)), \
"1" ((UDItype) (al)), \
"rme" ((UDItype) (bl)))
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mul{q} %3" \
: "=a" ((UDItype) (w0)), \
"=d" ((UDItype) (w1)) \
: "%0" ((UDItype) (u)), \
"rm" ((UDItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, dv) \
__asm__ ("div{q} %4" \
: "=a" ((UDItype) (q)), \
"=d" ((UDItype) (r)) \
: "0" ((UDItype) (n0)), \
"1" ((UDItype) (n1)), \
"rm" ((UDItype) (dv)))
#define count_leading_zeros(count, x) ((count) = __builtin_clzll (x))
#define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x))
#define UMUL_TIME 40
#define UDIV_TIME 40
#endif /* x86_64 */
#if defined (__i960__) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \
({union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __xx; \
__asm__ ("emul %2,%1,%0" \
: "=d" (__xx.__ll) \
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: "%dI" ((USItype) (u)), \
"dI" ((USItype) (v))); \
(w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
#define __umulsidi3(u, v) \
({UDItype __w; \
__asm__ ("emul %2,%1,%0" \
: "=d" (__w) \
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: "%dI" ((USItype) (u)), \
"dI" ((USItype) (v))); \
__w; })
#endif /* __i960__ */
1991-12-24 05:31:09 +01:00
longlong.h (sub_ddmmss): New for ia64. gcc/ 2009-02-12 Uros Bizjak <ubizjak@gmail.com> * longlong.h (sub_ddmmss): New for ia64. Ported from GMP 4.2. (umul_ppmm): Likewise. (count_leading_zeros): Likewise. (count_trailing_zeros): Likewise. (UMUL_TIME): Likewise. 2009-02-12 H.J. Lu <hongjiu.lu@intel.com> * config.gcc: Add ia64/t-fprules-softfp soft-fp/t-softfp to tmake_file for ia64*-*-linux*. * config/ia64/ia64.c (ia64_soft_fp_init_libfuncs): New. (ia64_expand_compare): Use HPUX library for TFmode only for HPUX. (ia64_builtins): Add IA64_BUILTIN_COPYSIGNQ, IA64_BUILTIN_FABSQ and IA64_BUILTIN_INFQ. (ia64_init_builtins): Initialize __builtin_infq, __builtin_fabsq and __builtin_copysignq if not HPUX. (ia64_expand_builtin): Handle IA64_BUILTIN_COPYSIGNQ, IA64_BUILTIN_FABSQ and IA64_BUILTIN_INFQ. * config/ia64/lib1funcs.asm (__divtf3): Define only if SHARED is defined. (__fixtfti): Likewise. (__fixunstfti): Likewise. (__floattitf): Likewise. * config/ia64/libgcc-glibc.ver: New. * config/ia64/t-fprules-softfp: Likewise. * config/ia64/sfp-machine.h: Likewise. * config/ia64/linux.h (LIBGCC2_HAS_TF_MODE): New. (LIBGCC2_TF_CEXT): Likewise. (TF_SIZE): Likewise. (TARGET_INIT_LIBFUNCS): Likewise. * config/ia64/t-glibc: Add $(srcdir)/config/ia64/libgcc-glibc.ver to SHLIB_MAPFILES. libgcc/ 2009-02-12 H.J. Lu <hongjiu.lu@intel.com> * config.host: Add ia64/t-fprules-softfp ia64/t-softfp-compat to tmake_file for ia64*-*-linux*. * Makefile.in (gen-hide-list): Ignore .*_compat and .*@.*. * config/ia64/__divxf3.asm: New. * config/ia64/_fixtfdi.asm: Likewise. * config/ia64/_fixunstfdi.asm: Likewise. * config/ia64/_floatditf.asm: Likewise. * config/ia64/t-fprules-softfp: Likewise. * config/ia64/t-softfp-compat: Likewise. * config/ia64/tf-signs.c: Likewise. From-SVN: r144130
2009-02-12 17:30:53 +01:00
#if defined (__ia64) && W_TYPE_SIZE == 64
/* This form encourages gcc (pre-release 3.4 at least) to emit predicated
"sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic
code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
register, which takes an extra cycle. */
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
UWtype __x; \
__x = (al) - (bl); \
if ((al) < (bl)) \
(sh) = (ah) - (bh) - 1; \
else \
(sh) = (ah) - (bh); \
(sl) = __x; \
} while (0)
/* Do both product parts in assembly, since that gives better code with
all gcc versions. Some callers will just use the upper part, and in
that situation we waste an instruction, but not any cycles. */
#define umul_ppmm(ph, pl, m0, m1) \
__asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
: "=&f" (ph), "=f" (pl) \
: "f" (m0), "f" (m1))
#define count_leading_zeros(count, x) \
do { \
UWtype _x = (x), _y, _a, _c; \
__asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
__asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
_c = (_a - 1) << 3; \
_x >>= _c; \
if (_x >= 1 << 4) \
_x >>= 4, _c += 4; \
if (_x >= 1 << 2) \
_x >>= 2, _c += 2; \
_c += _x >> 1; \
(count) = W_TYPE_SIZE - 1 - _c; \
} while (0)
/* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
based, and we don't need a special case for x==0 here */
#define count_trailing_zeros(count, x) \
do { \
UWtype __ctz_x = (x); \
__asm__ ("popcnt %0 = %1" \
: "=r" (count) \
: "r" ((__ctz_x-1) & ~__ctz_x)); \
} while (0)
#define UMUL_TIME 14
#endif
#if defined (__M32R__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \
__asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
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: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
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"r" ((USItype) (bh)), \
"1" ((USItype) (al)), \
1997-03-24 22:11:18 +01:00
"r" ((USItype) (bl)) \
: "cbit")
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
/* The cmp clears the condition bit. */ \
__asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
1997-03-24 22:11:18 +01:00
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"1" ((USItype) (al)), \
"r" ((USItype) (bl)) \
: "cbit")
#endif /* __M32R__ */
#if defined (__mc68000__) && W_TYPE_SIZE == 32
1991-12-24 05:31:09 +01:00
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
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: "=d" ((USItype) (sh)), \
"=&d" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"d" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
1991-12-24 05:31:09 +01:00
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
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: "=d" ((USItype) (sh)), \
"=&d" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
"d" ((USItype) (bh)), \
"1" ((USItype) (al)), \
"g" ((USItype) (bl)))
/* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
#if (defined (__mc68020__) && !defined (__mc68060__))
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#define umul_ppmm(w1, w0, u, v) \
__asm__ ("mulu%.l %3,%1:%0" \
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: "=d" ((USItype) (w0)), \
"=d" ((USItype) (w1)) \
: "%0" ((USItype) (u)), \
"dmi" ((USItype) (v)))
#define UMUL_TIME 45
1991-12-24 05:31:09 +01:00
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divu%.l %4,%1:%0" \
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: "=d" ((USItype) (q)), \
"=d" ((USItype) (r)) \
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
"dmi" ((USItype) (d)))
#define UDIV_TIME 90
#define sdiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("divs%.l %4,%1:%0" \
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: "=d" ((USItype) (q)), \
"=d" ((USItype) (r)) \
: "0" ((USItype) (n0)), \
"1" ((USItype) (n1)), \
"dmi" ((USItype) (d)))
#elif defined (__mcoldfire__) /* not mc68020 */
#define umul_ppmm(xh, xl, a, b) \
__asm__ ("| Inlined umul_ppmm\n" \
" move%.l %2,%/d0\n" \
" move%.l %3,%/d1\n" \
" move%.l %/d0,%/d2\n" \
" swap %/d0\n" \
" move%.l %/d1,%/d3\n" \
" swap %/d1\n" \
" move%.w %/d2,%/d4\n" \
" mulu %/d3,%/d4\n" \
" mulu %/d1,%/d2\n" \
" mulu %/d0,%/d3\n" \
" mulu %/d0,%/d1\n" \
" move%.l %/d4,%/d0\n" \
" clr%.w %/d0\n" \
" swap %/d0\n" \
" add%.l %/d0,%/d2\n" \
" add%.l %/d3,%/d2\n" \
" jcc 1f\n" \
" add%.l %#65536,%/d1\n" \
"1: swap %/d2\n" \
" moveq %#0,%/d0\n" \
" move%.w %/d2,%/d0\n" \
" move%.w %/d4,%/d2\n" \
" move%.l %/d2,%1\n" \
" add%.l %/d1,%/d0\n" \
" move%.l %/d0,%0" \
: "=g" ((USItype) (xh)), \
"=g" ((USItype) (xl)) \
: "g" ((USItype) (a)), \
"g" ((USItype) (b)) \
: "d0", "d1", "d2", "d3", "d4")
#define UMUL_TIME 100
#define UDIV_TIME 400
#else /* not ColdFire */
/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
1991-12-24 05:31:09 +01:00
#define umul_ppmm(xh, xl, a, b) \
__asm__ ("| Inlined umul_ppmm\n" \
" move%.l %2,%/d0\n" \
" move%.l %3,%/d1\n" \
" move%.l %/d0,%/d2\n" \
" swap %/d0\n" \
" move%.l %/d1,%/d3\n" \
" swap %/d1\n" \
" move%.w %/d2,%/d4\n" \
" mulu %/d3,%/d4\n" \
" mulu %/d1,%/d2\n" \
" mulu %/d0,%/d3\n" \
" mulu %/d0,%/d1\n" \
" move%.l %/d4,%/d0\n" \
" eor%.w %/d0,%/d0\n" \
" swap %/d0\n" \
" add%.l %/d0,%/d2\n" \
" add%.l %/d3,%/d2\n" \
" jcc 1f\n" \
" add%.l %#65536,%/d1\n" \
"1: swap %/d2\n" \
" moveq %#0,%/d0\n" \
" move%.w %/d2,%/d0\n" \
" move%.w %/d4,%/d2\n" \
" move%.l %/d2,%1\n" \
" add%.l %/d1,%/d0\n" \
" move%.l %/d0,%0" \
1996-07-04 00:07:53 +02:00
: "=g" ((USItype) (xh)), \
"=g" ((USItype) (xl)) \
: "g" ((USItype) (a)), \
"g" ((USItype) (b)) \
: "d0", "d1", "d2", "d3", "d4")
#define UMUL_TIME 100
#define UDIV_TIME 400
1991-12-24 05:31:09 +01:00
#endif /* not mc68020 */
/* The '020, '030, '040 and '060 have bitfield insns.
cpu32 disguises as a 68020, but lacks them. */
#if defined (__mc68020__) && !defined (__mcpu32__)
#define count_leading_zeros(count, x) \
__asm__ ("bfffo %1{%b2:%b2},%0" \
: "=d" ((USItype) (count)) \
: "od" ((USItype) (x)), "n" (0))
/* Some ColdFire architectures have a ff1 instruction supported via
__builtin_clz. */
#elif defined (__mcfisaaplus__) || defined (__mcfisac__)
#define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
#define COUNT_LEADING_ZEROS_0 32
#endif
1991-12-24 05:31:09 +01:00
#endif /* mc68000 */
#if defined (__m88000__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
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: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%rJ" ((USItype) (ah)), \
"rJ" ((USItype) (bh)), \
"%rJ" ((USItype) (al)), \
"rJ" ((USItype) (bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
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: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "rJ" ((USItype) (ah)), \
"rJ" ((USItype) (bh)), \
"rJ" ((USItype) (al)), \
"rJ" ((USItype) (bl)))
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#define count_leading_zeros(count, x) \
do { \
USItype __cbtmp; \
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__asm__ ("ff1 %0,%1" \
: "=r" (__cbtmp) \
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: "r" ((USItype) (x))); \
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(count) = __cbtmp ^ 31; \
} while (0)
#define COUNT_LEADING_ZEROS_0 63 /* sic */
#if defined (__mc88110__)
#define umul_ppmm(wh, wl, u, v) \
do { \
union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __xx; \
__asm__ ("mulu.d %0,%1,%2" \
: "=r" (__xx.__ll) \
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: "r" ((USItype) (u)), \
"r" ((USItype) (v))); \
(wh) = __xx.__i.__h; \
(wl) = __xx.__i.__l; \
} while (0)
#define udiv_qrnnd(q, r, n1, n0, d) \
({union {UDItype __ll; \
struct {USItype __h, __l;} __i; \
} __xx; \
USItype __q; \
__xx.__i.__h = (n1); __xx.__i.__l = (n0); \
__asm__ ("divu.d %0,%1,%2" \
: "=r" (__q) \
: "r" (__xx.__ll), \
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"r" ((USItype) (d))); \
(r) = (n0) - __q * (d); (q) = __q; })
#define UMUL_TIME 5
#define UDIV_TIME 25
#else
#define UMUL_TIME 17
#define UDIV_TIME 150
#endif /* __mc88110__ */
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#endif /* __m88000__ */
#if defined (__mn10300__)
# if defined (__AM33__)
# define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
# define umul_ppmm(w1, w0, u, v) \
asm("mulu %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
# define smul_ppmm(w1, w0, u, v) \
asm("mul %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
# else
# define umul_ppmm(w1, w0, u, v) \
asm("nop; nop; mulu %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
# define smul_ppmm(w1, w0, u, v) \
asm("nop; nop; mul %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
# endif
# define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
DWunion __s, __a, __b; \
__a.s.low = (al); __a.s.high = (ah); \
__b.s.low = (bl); __b.s.high = (bh); \
__s.ll = __a.ll + __b.ll; \
(sl) = __s.s.low; (sh) = __s.s.high; \
} while (0)
# define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
DWunion __s, __a, __b; \
__a.s.low = (al); __a.s.high = (ah); \
__b.s.low = (bl); __b.s.high = (bh); \
__s.ll = __a.ll - __b.ll; \
(sl) = __s.s.low; (sh) = __s.s.high; \
} while (0)
# define udiv_qrnnd(q, r, nh, nl, d) \
asm("divu %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
# define sdiv_qrnnd(q, r, nh, nl, d) \
asm("div %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
# define UMUL_TIME 3
# define UDIV_TIME 38
#endif
#if defined (__mips__) && W_TYPE_SIZE == 32
md.texi: Synchronize with later constraints.md change. gcc/ * doc/md.texi: Synchronize with later constraints.md change. * longlong.h (umul_ppmm): Replace the MIPS asm implementation with a C implementation. * config/mips/mips.c (mips_legitimize_move): Remove MFHI and MFLO handling. (mips_subword): Assume TImode for CONST_INTs if TARGET_64BIT. (mips_split_doubleword_move): Use special MTHI and MFHI instructions when moving to and from MD_REGNUM. (mips_output_move): Don't handle moves from GPRs to HI_REGNUM. Handle moves from LO_REGNUM to GPRs using MFLO, MACC or DMACC. Handle byte and halfword moves. (mips_hard_regno_mode_ok_p): Handle MD_REGS and DSP_ACC_REGS separately. * config/mips/constraints.md (h): Turn into NO_REGS. (l, x): Update documentation. * config/mips/mips.md (UNSPEC_MFHILO): Delete. (UNSPEC_MFHI, UNSPEC_MTHI, UNSPEC_SET_HILO): New. (UNSPEC_TLS_LDM, UNSPEC_TLS_GET_TP): Renumber. (HILO): New mode iterator. (MOVE128): Add TI. (any_div): New code iterator. (u): Extend code attribute to div and udiv. (*add<mode>3_mips16, *movdi_64bit_mips16, *movsi_mips16): Use d_operand in the splitters. Remove redundant CONST_INT checks. (mulsi3_mult3, mul<mode>3_internal, mul<mode>3_r4000, *mul_acc_si) (*macc, *msac, *msac_using_macc, *macc2, *msac2, *mul_sub_si) (*muls): Remove "=h" clobbers. Adjust peephole2s and define_splits accordingly, using normal moves instead of unspecs to move LO into a GPR. Use d_operand and lo_operand instead of *_REG_P checks. (<u>mulsidi3): Handle expansion in C code. (<u>mulsidi3_32bit_internal): Rename to... (<u>mulsidi3_32bit): ...this. (<u>mulsidi3_32bit_r4000): Fix insn separator. (*<u>mulsidi3_64bit): Rename to... (<u>mulsidi3_64bit): ...this. Combine DImode "=h" and "=l" clobbers into a TImode "=x" clobber. In the split, use an UNSPEC_SET_HILO to set LO and HI to the multiplication result. Use a normal move for MFLO and an unspec for MFHI. (*<u>mulsidi3_64bit_parts): Replace with... (<u>mulsidi3_64bit_hilo): ...this new instruction. (<su>mulsi3_highpart): Extend to TARGET_FIX_R4000. (<su>mulsi3_highpart_internal): Turn into a define_insn_and_split and extend it to TARGET_FIX_R4000. Store the destination in a GPR instead of HI. Split the instruction into a separate multiplication and MFHI if !TARGET_FIX_R4000. (<su>muldi3_highpart): Likewise. (<su>mulsi3_highpart_mulhi_internal): Remove the first alternative and the "=h" clobber. (*<su>mulsi3_highpart_neg_mulhi_internal): Likewise. (<u>mulditi3): New expander. (<u>mulditi3_internal, <u>mulditi3_r4000): New patterns. (madsi): Remove "=h" clobber. (divmod<mode>4, udivmod<mode>4): Turn into define_insn_and_splits. Force the modulus result to be a GPR and split the instruction into a division followed by an MFHI after reload. (<u>divmod<GPR:mode>4_hilo_<HILO:mode>): New instruction. (*lea_high64): Use d_operand in the define_peephole2. Likewise the MIPS16 HIGH define_split. (*movdi_32bit, *movdi_gp32_fp64, *movdi_32bit_mips16): Change type of acc<->gpr moves to "multi". (*movdi_64bit): Replace the single "x" alternative with alternatives for moving into and out of "a". (*movhi_internal, *movqi_internal): Likewise. Use mips_output_move. (*movsi_internal): Extend the "d<-A" alternative to "d<-a". (*movdi_64bit_mips16, *movsi_mips16): Add d<-a alternatives. Use d_operand in the splitters. Remove redundant CONST_INT checks. (*movhi_mips16, *movqi_mips16): Likewise. Use mips_output_move. (movti): New expander. (*movti, *movti_mips16): New insns. (mfhilo_<mode>, *mfhilo_<mode>, *mfhilo_<mode>_macc): Delete. (mfhi<GPR:mode>_<HILO:mode>): New pattern. (mthi<GPR:mode>_<HILO:mode>): Likewise. * config/mips/predicates.md (fpr_operand): Delete. (d_operand): New predicate. gcc/testsuite/ * gcc.dg/torture/mips-hilo-1.c: Delete. * gcc.target/mips/pr35232.c: Likewise. * gcc.target/mips/fix-vr4130-1.c: Use modulus to create an mfhi. * gcc.target/mips/fix-vr4130-3.c: Likewise. * gcc.target/mips/int-moves-1.c: New test. * gcc.target/mips/int-moves-2.c: Likewise. * gcc.target/mips/fix-r4000-1.c: Likewise. * gcc.target/mips/fix-r4000-2.c: Likewise. * gcc.target/mips/fix-r4000-3.c: Likewise. * gcc.target/mips/fix-r4000-4.c: Likewise. * gcc.target/mips/fix-r4000-5.c: Likewise. * gcc.target/mips/fix-r4000-6.c: Likewise. * gcc.target/mips/fix-r4000-7.c: Likewise. * gcc.target/mips/fix-r4000-8.c: Likewise. * gcc.target/mips/fix-r4000-9.c: Likewise. * gcc.target/mips/fix-r4000-10.c: Likewise. * gcc.target/mips/fix-r4000-11.c: Likewise. * gcc.target/mips/fix-r4000-12.c: Likewise. * gcc.target/mips/timode-1.c: Likewise. * gcc.target/mips/timode-2.c: Likewise. From-SVN: r136600
2008-06-09 22:45:56 +02:00
#define umul_ppmm(w1, w0, u, v) \
do { \
UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
(w1) = (USItype) (__x >> 32); \
(w0) = (USItype) (__x); \
} while (0)
#define UMUL_TIME 10
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#define UDIV_TIME 100
#if (__mips == 32 || __mips == 64) && ! __mips16
#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
#define COUNT_LEADING_ZEROS_0 32
#endif
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#endif /* __mips__ */
#if defined (__ns32000__) && W_TYPE_SIZE == 32
#define umul_ppmm(w1, w0, u, v) \
({union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __xx; \
__asm__ ("meid %2,%0" \
: "=g" (__xx.__ll) \
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: "%0" ((USItype) (u)), \
"g" ((USItype) (v))); \
(w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
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#define __umulsidi3(u, v) \
({UDItype __w; \
__asm__ ("meid %2,%0" \
: "=g" (__w) \
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: "%0" ((USItype) (u)), \
"g" ((USItype) (v))); \
__w; })
#define udiv_qrnnd(q, r, n1, n0, d) \
({union {UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __xx; \
__xx.__i.__h = (n1); __xx.__i.__l = (n0); \
__asm__ ("deid %2,%0" \
: "=g" (__xx.__ll) \
: "0" (__xx.__ll), \
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"g" ((USItype) (d))); \
(r) = __xx.__i.__l; (q) = __xx.__i.__h; })
#define count_trailing_zeros(count,x) \
do { \
__asm__ ("ffsd %2,%0" \
: "=r" ((USItype) (count)) \
: "0" ((USItype) 0), \
"r" ((USItype) (x))); \
} while (0)
1991-12-24 05:31:09 +01:00
#endif /* __ns32000__ */
/* FIXME: We should test _IBMR2 here when we add assembly support for the
system vendor compilers.
FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
enough, since that hits ARM and m68k too. */
#if (defined (_ARCH_PPC) /* AIX */ \
|| defined (_ARCH_PWR) /* AIX */ \
|| defined (_ARCH_COM) /* AIX */ \
|| defined (__powerpc__) /* gcc */ \
|| defined (__POWERPC__) /* BEOS */ \
|| defined (__ppc__) /* Darwin */ \
|| (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
|| (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
&& CPU_FAMILY == PPC) \
) && W_TYPE_SIZE == 32
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else \
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)
#define count_leading_zeros(count, x) \
__asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 32
#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
|| defined (__ppc__) \
|| (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
|| (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
&& CPU_FAMILY == PPC)
#define umul_ppmm(ph, pl, m0, m1) \
do { \
USItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define UMUL_TIME 15
#define smul_ppmm(ph, pl, m0, m1) \
do { \
SItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define SMUL_TIME 14
#define UDIV_TIME 120
#elif defined (_ARCH_PWR)
#define UMUL_TIME 8
#define smul_ppmm(xh, xl, m0, m1) \
__asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
#define SMUL_TIME 4
#define sdiv_qrnnd(q, r, nh, nl, d) \
__asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
#define UDIV_TIME 100
#endif
#endif /* 32-bit POWER architecture variants. */
/* We should test _IBMR2 here when we add assembly support for the system
vendor compilers. */
#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
else \
__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
: "=r" (sh), "=&r" (sl) \
: "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
} while (0)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
if (__builtin_constant_p (ah) && (ah) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
: "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
else \
__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
: "=r" (sh), "=&r" (sl) \
: "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
} while (0)
#define count_leading_zeros(count, x) \
__asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
#define COUNT_LEADING_ZEROS_0 64
#define umul_ppmm(ph, pl, m0, m1) \
do { \
UDItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define UMUL_TIME 15
#define smul_ppmm(ph, pl, m0, m1) \
do { \
DItype __m0 = (m0), __m1 = (m1); \
__asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
(pl) = __m0 * __m1; \
} while (0)
#define SMUL_TIME 14 /* ??? */
#define UDIV_TIME 120 /* ??? */
#endif /* 64-bit PowerPC. */
#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("a %1,%5\n\tae %0,%3" \
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: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"r" ((USItype) (bl)))
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("s %1,%5\n\tse %0,%3" \
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: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
"r" ((USItype) (bh)), \
"1" ((USItype) (al)), \
"r" ((USItype) (bl)))
1991-12-24 05:31:09 +01:00
#define umul_ppmm(ph, pl, m0, m1) \
do { \
USItype __m0 = (m0), __m1 = (m1); \
1991-12-24 05:31:09 +01:00
__asm__ ( \
"s r2,r2\n" \
" mts r10,%2\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" m r2,%3\n" \
" cas %0,r2,r0\n" \
" mfs r10,%1" \
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: "=r" ((USItype) (ph)), \
"=r" ((USItype) (pl)) \
: "%r" (__m0), \
"r" (__m1) \
: "r2"); \
(ph) += ((((SItype) __m0 >> 31) & __m1) \
+ (((SItype) __m1 >> 31) & __m0)); \
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} while (0)
#define UMUL_TIME 20
#define UDIV_TIME 200
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#define count_leading_zeros(count, x) \
do { \
if ((x) >= 0x10000) \
__asm__ ("clz %0,%1" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (count)) \
: "r" ((USItype) (x) >> 16)); \
1991-12-24 05:31:09 +01:00
else \
{ \
__asm__ ("clz %0,%1" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (count)) \
: "r" ((USItype) (x))); \
1991-12-24 05:31:09 +01:00
(count) += 16; \
} \
} while (0)
#endif
#if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
#ifndef __sh1__
#define umul_ppmm(w1, w0, u, v) \
__asm__ ( \
"dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
: "=r<" ((USItype)(w1)), \
"=r<" ((USItype)(w0)) \
: "r" ((USItype)(u)), \
"r" ((USItype)(v)) \
: "macl", "mach")
#define UMUL_TIME 5
#endif
/* This is the same algorithm as __udiv_qrnnd_c. */
#define UDIV_NEEDS_NORMALIZATION 1
#define udiv_qrnnd(q, r, n1, n0, d) \
do { \
extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
__attribute__ ((visibility ("hidden"))); \
/* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
__asm__ ( \
"mov%M4 %4,r5\n" \
" swap.w %3,r4\n" \
" swap.w r5,r6\n" \
" jsr @%5\n" \
" shll16 r6\n" \
" swap.w r4,r4\n" \
" jsr @%5\n" \
" swap.w r1,%0\n" \
" or r1,%0" \
: "=r" (q), "=&z" (r) \
: "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
: "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
} while (0)
#define UDIV_TIME 80
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("clrt;subc %5,%1; subc %4,%0" \
: "=r" (sh), "=r" (sl) \
: "0" (ah), "1" (al), "r" (bh), "r" (bl) : "t")
#endif /* __sh__ */
Contribute sh64-elf. 2002-02-09 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (TARGET_CANNOT_MODIFY_JUMPS_P): Define to... (sh_cannot_modify_jumps_p): New function. 2002-02-05 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (TARGET_MS_BITFIELD_LAYOUT_P): Define to... (sh_ms_bitfield_layout_p): New function. 2002-02-04 Alexandre Oliva <aoliva@redhat.com> Zack Weinberg <zack@codesourcery.com> * config/sh/sh.h (TRAMPOLINE_ADJUST_ADDRESS): Use expand_simple_binop instead of expand_binop. 2002-02-03 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (OVERRIDE_OPTIONS) [! TARGET_SH5]: Disable use of .quad and .uaquad. * config/sh/sh.c (TARGET_ASM_UNALIGNED_DI_OP, TARGET_ASM_ALIGNED_DI_OP): Add comment pointing to the above. 2002-01-24 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (movdi_const, movdi_const_32bit, movdi_const_16bit): Make sure all CONSTs have modes. (sym2PIC): Ditto, but by adjusting all callers. * config/sh/sh.c (calc_live_regs) [TARGET_SHCOMPACT]: Set pr_live if the prologue calls the SHmedia argument decoder or register saver. 2002-01-24 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (TARGET_ASM_UNALIGNED_DI_OP): Define. (TARGET_ASM_ALIGNED_DI_OP): Likewise. (sh_expand_epilogue): Don't emit USE of return target register. (prepare_move_operands): Legitimize DImode PIC addresses. (sh_media_register_for_return): Skip tr0, used to initialize the PIC register. (sh_expand_prologue): Remove explicit USE of return register. (nonpic_symbol_mentioned_p): PC is non-PIC. Don't recurse in CONST_DOUBLEs. UNSPEC_GOTPLT is PIC. * config/sh/sh.h (ASM_OUTPUT_DOUBLE_INT): Removed, obsolete. (OVERRIDE_OPTIONS): Don't disable PIC on SH5. (EXTRA_CONSTRAINT_S): Use MOVI_SHORI_BASE_OPERAND_P instead of EXTRA_CONSTRAINT_T. (GOT_ENTRY_P, GOTPLT_ENTRY_P, GOTOFF_P, PIC_ADDR_P): New. (MOVI_SHORI_BASE_OPERAND_P): New. (NON_PIC_REFERENCE_P, PIC_REFERENCE_P): New. (EXTRA_CONSTRAINT_T): Define in terms of them. (OUTPUT_ADDR_CONST_EXTRA): Handle UNSPEC_GOTPLT. * config/sh/sh.md (movsi_media, movsi_media_nofpu, movdi_media, movdi_media_nofpu): Add SIBCALL_REGS class to alternatives supporting TARGET_REGS. (UNSPEC_GOTPLT): New constant. (movdi split): Move incrementing of LABEL_NUSES... (movdi_const, movdi_const_32bit): Here. Use MOVI_SHORI_BASE_OPERAND_P instead of EXTRA_CONSTRAINT_T. (movdi_const_16bit): New. (call, call_value) [flag_pic]: Use GOTPLT. (call_pop, call_value_pop): New expands. (call_pop_compact, call_pop_rettramp): New insns. (call_value_pop_compact, call_value_pop_rettramp): New insns. (sibcall) [flag_pic]: Use GOT. (builtint_setjmp_receiver): Remove bogus, unused expand. (GOTaddr2picreg): Implement for SHcompact and SHmedia. (*pt, *ptb, ptrel): New insns. (sym2GOT): Handle DImode GOT. (sym2GOTPLT, symGOTPLT2reg): New expands. (sym2PIC): New expand. (shcompact_return_tramp): Use GOTPLT to return trampoline. (shcompact_return_tramp_i): Use return register explicitly. * config/sh/sh.h (OVERRIDE_OPTIONS) [TARGET_SHMEDIA]: Don't disable flag_reorder_blocks. 2002-01-19 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (sibcall_compact): Reorder return, uses and clobbers, for clarity. (sibcall_epilogue) [TARGET_SHCOMPACT]: Mark saving and restoring of r0 in macl as MAYBE_DEAD. 2002-01-18 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (LONG_DOUBLE_TYPE_SIZE): Define. * config/sh/sh.md (movv4sf_i, movv16sf_i): Fix uses of alter_subreg all over. (jump) [TARGET_SHMEDIA]: FAIL to create new jumps after reload, instead of emitting instructions that would require reloading. (casesi_load_media): Add missing modes. 2001-11-09 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (sh_expand_prologue): Mark the PIC register as used if the argument decoder is called. 2001-08-28 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (udivsi3, divsi3): Load libcall symbol name in Pmode, then extend it to DImode if necessary. 2001-08-28 Stephen Clarke <Stephen.Clarke@st.com> * config/sh/sh.h (LEGITIMATE_CONSTANT_P): Don't accept DFmode constants in FPU-enabled SHmedia, let them be loaded from memory. 2001-08-28 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (cmpeqdi_media, cmpgtdi_media, cmpgtudi_media): Adjust whitespace in assembly output templates. 2001-08-28 Stephen Clarke <Stephen.Clarke@st.com> * config/sh/sh.md (movdicc_false, movdicc_true, movdicc): Adjust mode of if_then_else. 2001-08-04 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh64.h (CPP_DEFAULT_CPU_SPEC): Override definition in sh.h. 2001-07-26 Andrew Haley <aph@cambridge.redhat.com> Joern Rennecke <amylaar@redhat.com> * config/sh/sh64.h (CPP_DEFAULT_CPU_SPEC): New. (SUBTARGET_CPP_PTR_SPEC): New. (SUBTARGET_CPP_SPEC): Remove. 2001-07-06 Chandrakala Chavva <cchavva@redhat.com> * config/sh/sh.md (movsf_media_nofpu+1, movdf_media_nofpu+1): Fix typo in previous checkin. 2001-07-11 Chandrakala Chavva <cchavva@redhat.com> * config/sh/sh.h (MODES_TIEABLE_P): Fix redact indentations. 2001-07-10 Chandrakala Chavva <cchavva@cygnus.com> Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (MODES_TIEABLE_P): Don't tie modes wider than what single FP register can hold for SHmedia target. 2001-07-06 Chandrakala Chavva <cchavva@redhat.com> Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (movsf_media_nofpu+1, movdf_media_nofpu+1): Do not split into SUBREG. 2001-06-14 Alexandre Oliva <aoliva@redhat.com> * config/sh/ushmedia.h, config/sh/sshmedia.h: Updated signatures and added new functions as specified in SH5 ABI r9. 2001-06-04 Alexandre Oliva <aoliva@redhat.com> * config/sh/lib1funcs.asm (GCC_nested_trampoline): Align to an 8-byte boundary. 2001-06-03 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (dump_table): Add const0_rtx in calls of gen_consttable_4 and gen_consttable_8. Emit multiple labels and consttable_window_ends. 2001-06-03 Graham Stott <grahams@redhat,com> * config/sh/sh.md (movdi split): Remove unused variable last_insn. 2001-05-16 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (print_operand): Handle floating-point pair, vector and matrix registers. * config/sh/sh.h (REGISTER_MOVE_COST): Take floating-pointer vector modes into account. * config/sh/sh.md (movv2sf): Split move between registers into movdf. (movv4sf, movv16sf): Introduce insns that get split only after reload. * config/sh/shmedia.h: Fix Copyright dates. * config/sh/ushmedia.h: Likewise. Move loop counter declarations into conditionals that uses them. (sh_media_FVADD_S, sh_media_FVSUB_S): Fix off-by-one error in loop boundary. * config/sh/sshmedia.h: Fix Copyright dates. (sh_media_PUTCFG): Fix constraints. 2001-05-12 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (TARGET_PTRMEMFUNC_VBIT_LOCATION): Define to ptrmemfunc_vbit_in_delta for SH5. 2001-05-08 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (TARGET_SWITCHES): Document -m5-*. * invoke.texi: Likewise. 2001-04-14 Alexandre Oliva <aoliva@redhat.com> * config/sh/lib1funcs.asm (GCC_push_shmedia_regs, GCC_push_shmedia_regs_nofpu, GCC_pop_shmedia_regs, GCC_pop_shmedia_regs_nofpu): New global symbols. * config/sh/t-sh64 (LIB1ASMFUNCS): Add them. * config/sh/sh.h (SHMEDIA_REGS_STACK_ADJUST): New macro. * config/sh/sh.c (calc_live_regs): Account for PR's saving in compact function with nonlocal labels. (sh_expand_prologue) [SHcompact]: Push SHmedia regs if needed. (sh_expand_epilogue) [SHcompact]: Pop them when appropriate. (initial_elimination_offset): Account for their stack space. * config/sh/sh.md (shmedia_save_restore_regs_compact): New insn. * config/sh/sh.md (movsi_media, movsi_media_nofpu, movqi_media, movhi_media, movdi_media, movdi_media_nofpu, movdf_media, movdf_media_nofpu, movsf_media, movsf_media_nofpu): Require at least one of the operands to be a register. (movv2sf): Likewise. Renamed to movv2sf_i. (movdi, movdf, movv2sf, movv4sf, movv16sf, movsf): prepare_move_operands() before emitting SHmedia insns. 2001-04-03 Alexandre Oliva <aoliva@redhat.com> * config/sh/crti.asm (init, fini) [__SH5__ && ! __SHMEDIA__]: Don't save nor initialize r12. Don't mis-align the stack. Pad the code with a nop. * config/sh/crti.asm: Don't restore r12. Don't mis-align the stack. 2001-03-13 Alexandre Oliva <aoliva@redhat.com> * gcc/longlong.h (__umulsidi3, count_leading_zeros) [__SHMEDIA__]: Implement. 2001-03-11 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md: Set latency of `pt' closer to reality. (movsi_media, movsi_media_nofpu, movdi_media, movdi_media_nofpu, movdf_media, movdf_media_nofpu, movsf_media, movsf_media_nofpu): Set move, load and store type attributes. * config/sh/sh.c (sh_loop_align) [TARGET_SH5]: Set to 3. * config/sh/sh.h (OVERRIDE_OPTIONS) [TARGET_SH5]: Disable profiling. * config/sh/sh.h (PROMOTE_MODE): Sign-extend SImode to DImode. * config/sh/sh-protos.h (sh_media_register_for_return): Declare. * config/sh/sh.c (sh_media_register_for_return): New function. (sh_expand_prologue) [TARGET_SHMEDIA]: Copy r18 to an available branch-target register. (sh_expand_epilogue) [TARGET_SHMEDIA]: Explicitly USE it. * config/sh/sh.md (return_media_i): Use any call-clobbered branch-target register. (return_media): If r18 wasn't copied in the prologue, copy it here. * config/sh/sh.h (CONDITIONAL_REGISTER_USAGE) [TARGET_SHMEDIA]: Clear class FP0_REGS. * config/sh/sh64.h (LINK_SPEC): Removed incorrect default copied from elf.h. 2001-03-08 DJ Delorie <dj@redhat.com> * config/sh/sh.h (OVERRIDE_OPTIONS): Disable relaxing for SHMEDIA. 2001-02-09 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (sibcall_compact): Set fp_mode to single. 2001-02-07 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (INT_ASM_OP) [SHMEDIA64]: Use `.quad'. 2001-02-03 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (INIT_CUMULATIVE_ARGS): Compute size of BLKmode return value correctly for call_cookie. 2001-02-01 Alexandre Oliva <aoliva@redhat.com> * config/sh/crt1.asm (start): Modified so as to call ___setup_argv_and_call_main. 2001-01-26 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (FUNCTION_ARG_ADVANCE): Don't count stack_regs in SHmedia mode. 2001-01-20 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (STRIP_DATALABEL_ENCODING): New macro. (STRIP_NAME_ENCODING): Use it. (ASM_OUTPUT_LABELREF): Likewise. Don't call assemble_name(). 2001-01-19 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (sgeu) [! SHMEDIA]: Fix invocation of prepare_scc_operands(). * config/sh/sh.h (SH_DATALABEL_ENCODING): Change to "#"... (DATALABEL_SYMNAME_P): ... so that we don't need memcmp here. 2001-01-17 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (STRIP_NAME_ENCODING): Strip leading `*'. 2001-01-13 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (shcompact_incoming_args): Use R0_REG. * config/sh/sh.md (R7_REG, R8_REG, R9_REG): Define as constants, used in shcompact_incoming_args. * config/sh/sh.c (sh_expand_epilogue): Fix thinko in previous change. * config/sh/crt1.asm (start) [SH5]: Switch to single-precision mode. * config/sh/lib1funcs.asm (sdivsi3_i4, udivsi3_i4, set_fpscr): Adjust accordingly. * config/sh/sh.c (sh_expand_prologue, sh_expand_epilogue): Simplify. Adjust. Add sanity check. * config/sh/sh.h (TARGET_SWITCHES) [5-compact]: Set FPU_SINGLE_BIT. * config/sh/sh.md (udivsi3_i4_single, divsi3_i4_single): Match TARGET_SHCOMPACT. (udivsi3, divsi3): Use them. (force_mode_for_call): New insn. (call, call_value, sibcall_value): Emit it before SHcompact calls. 2001-01-11 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (call, call_value, sibcall): Make sure the call cookie is non-NULL before taking its value. 2001-01-10 Alexandre Oliva <aoliva@redhat.com> * config.gcc (sh64): Set target_requires_64bit_host_wide_int. 2001-01-09 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (shcompact_incoming_args): Set argument memory block. * config/sh/sh.h (STATIC_CHAIN_REGNUM) [SH5]: Use r1. * config/sh/sh.c (sh_expand_prologue) [SH5]: Use r0 as temporary for stack adjusts. Use MACL and MACH to pass arguments to shcompact_incoming_args. * config/sh/sh.md (shcompact_incoming_args): Adjust. Don't clobber r1. * config/sh/lib1funcs.asm (shcompact_incoming_args): Likewise. (nested_trampoline): Load static chain address into r1. * config/sh/sh.md (movdi_media splits): Fix sign-extension. 2001-01-07 Alexandre Oliva <aoliva@redhat.com * config/sh/sh.c (fpul_operand) [SHMEDIA]: Just call fp_arith_reg_operand(). 2001-01-06 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (casesi): Sign-extend the first two operands, and use signed compares for them. * config/sh/sh.c (dump_table): Don't emit 8-byte constants after 4-byte ones. Instead, inter-leave them, maintaining the 8-byte ones properly aligned. (find_barrier): Account for extra alignment needed for 8-byte wide constants. (machine_dependent_reorg): Require a label for the second 4-byte constant after an 8-byte one. * config/sh/lib1funcs.asm (sdivsi3): Fix typo in yesterday's change. 2001-01-05 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (machine_dependent_reorg) [SHCOMPACT]: Reset last_float when switching float modes. * config/sh/sh.md (movdf) [SH5]: Don't use stack-pointer auto-increment for general-purpose registers. * config/sh/lib1funcs.asm (sdivsi3) [SHMEDIA]: Sign-extend the result. * config/sh/sh.c (sh_expand_prologue) [SH5]: Use r1 as temporary for stack adjust. * config/sh/sh.c (sh_builtin_saveregs): Support using all registers for varargs. 2001-01-01 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (FUNCTION_ARG_ADVANCE): Simplify. * config/sh/sh.h (CALL_COOKIE_STACKSEQ, CALL_COOKIE_STACKSEQ_SHIFT, CALL_COOKIE_STACKSEQ_GET): New macros. (CALL_COOKIE_INT_REG_SHIFT): Adjust. (FUNCTION_ARG_ADVANCE): Use SHCOMPACT_FORCE_ON_STACK. Adjust call_cookie accordingly. (FUNCTION_ARG): Test SHCOMPACT_FORCE_ON_STACK. (SHCOMPACT_BYREF): Likewise. (SHCOMPACT_FORCE_ON_STACK): New macro. * config/sh/sh.c (sh_expand_prologue): Use new call_cookie format. (sh_builtin_saveregs): Likewise. * config/sh/lib1funcs.asm (shcompact_call_trampoline, shcompact_incoming_args): Use new shift values. Support sequences of consecutive and non-consecutive pushes/pops. * config/sh/sh.md (return): Don't explicitly use PR_REG. 2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com> * config/sh/sh.h (TEXT_SECTION): Define. * config/sh/elf.h (ASM_FILE_START): Output TEXT_SECTION_ASM_OP. 2001-01-05 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (INIT_CUMULATIVE_LIBCALL_ARGS): New macro. * config/sh/sh.h (BASE_RETURN_VALUE_REG): Use FP regs for return values on FPU-enabled SHmedia. (FUNCTION_VALUE_REGNO_P): Mark FIRST_FP_RET_REG as used on FPU-enabled SHmedia. (INIT_CUMULATIVE_ARGS): Set up return trampoline only if value is returned in a non-FP reg and is not returned by reference. * config/sh/sh.md (shcompact_return_tramp_i): Change type to jump_ind. 2000-01-04 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (SH_MIN_ALIGN_FOR_CALLEE_COPY): New. (FUNCTION_ARG_CALLEE_COPIES): Require argument to be quad-aligned to be passed by callee-copy reference. 2001-01-03 Alexandre Oliva <aoliva@redhat.com> * config/sh/elf.h (MAX_WCHAR_TYPE_SIZE): Define. * config/sh/sh64.h (MAX_WCHAR_TYPE_SIZE): Undefine. 2001-01-02 Alexandre Oliva <aoliva@redhat.com> * config/sh/lib1funcs.asm (shcompact_call_trampoline): Fix error in copying low-numbered FP regs to r7 and r8. * config/sh/sh.h (FUNCTION_ARG_ADVANCE): Don't request copying of FP regs to general-purpose regs only if the copy was passed on the stack. * config/sh/lib1funcs.asm (shcompact_call_trampoline): Fix typo in copying FP reg to r9. * config/sh/sh.h (FUNCTION_ARG_ADVANCE): Use trampoline to copy FP regs to general-purpose regs only in outgoing calls. * config/sh/sh.md (movdf_media, movsf_media): Revert incorrect change from 2000-10-30. Adjust for 64-bit (or 32-bit) HOST_WIDE_INT. * config/sh/sh.h (struct sh_args): Document all fields. (FUNCTION_OK_FOR_SIBCALL): Functions that receive arguments passed partially on the stack should not consider making sibcalls. * config/sh/sh.h (FUNCTION_ARG_ADVANCE): Add byref regs to stack_regs only for incoming calls. When passing FP args, make sure there are FP regs available before modifying call_cookie. (SHCOMPACT_BYREF): Pass double args in general-purpose registers by reference. 2000-12-30 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (FUNCTION_OK_FOR_SIBCALL) [SHCOMPACT]: Don't attempt to generate sibcalls if the caller got any arguments by reference. * config/sh/lib1funcs.asm (set_fpscr) [SH5]: Default to double. * config/sh/sh.c (dump_table) [SHCOMPACT]: Align DImode and DFmode to 8-byte boundaries. * config/sh/sh.md (shcompact_preserve_incoming_args): New insn. * config/sh/sh.h (CALL_COOKIE_INT_REG_GET): New macro. * config/sh/sh.c (sh_expand_prologue): Preserve args that will be stored in the stack. * config/sh/lib1funcs.asm (ct_main_table, ia_main_table): Arrange for the offsets to have the ISA bit set. (shcompact_call_trampoline): Document. Swap r0 and r1, to match invocation. Use beq instead of bgt to mark end of sequence of loads. (shcompact_incoming_args): Fix store of r2. Use beq instead of bgt to mark end of sequence of stores. * config/sh/sh.c (arith_operand): Don't check whether CONST_OK_FOR_J for now. * config/sh/sh.md (movdf_media, movsf_media): Use HOST_WIDE_INT instead of long for conversion. 2000-12-29 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.c (print_operand_address): Convert INTVAL to int before passing it to fprintf. 2000-12-28 Alexandre Oliva <aoliva@redhat.com> * config/sh/crt1.asm (start): Reset SR.FD, to enable the FP unit. Call set_fpscr before reading/writing SR. * config/sh/crt1.asm (start): Set SR.SZ and SR.PR, but not SR.FR. Call set_fpscr. * config/sh/lib1funcs.asm: Add `.align 2' directives before SHmedia code. (FMOVD_WORKS): Define on SH5 with FPU. (set_fpscr): Define on SH5. Remove separate _fpscr_values setting. * config/sh/t-sh64 (LIB1ASMFUNCS): Add _set_fpscr instead of _fpscr_values. 2000-12-28 Hans-Peter Nilsson <hpn@cygnus.com> * config/sh/lib1funcs.asm (ct_main_table): Align contents to even address. (ia_main_table): Ditto. 2000-12-27 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.h (MAX_WCHAR_TYPE_SIZE): Don't define. * config/sh/sh64.h (WCHAR_TYPE, WCHAR_TYPE_SIZE): Reinstate the definitions from sh.h. * config/sh/sh.h (PTRDIFF_TYPE): Define as conditional on TARGET_SH5. (SUBTARGET_CPP_SPEC): Arrange for __PTRDIFF_TYPE__ to be defined. * config/sh/elf.h (PTRDIFF_TYPE): Likewise. * config/sh/sh64.h (SUBTARGET_CPP_SPEC): Likewise. 2000-12-26 Alexandre Oliva <aoliva@redhat.com> * config/sh/sh.md (movdi_media split): Don't add REG_LABEL notes. Increment LABEL_NUSES. From-SVN: r49630
2002-02-09 04:08:08 +01:00
#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
#define count_leading_zeros(count, x) \
do \
{ \
UDItype x_ = (USItype)(x); \
SItype c_; \
\
__asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
(count) = c_ - 31; \
} \
while (0)
#define COUNT_LEADING_ZEROS_0 32
#endif
#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
&& W_TYPE_SIZE == 32
1991-12-24 05:31:09 +01:00
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "%rJ" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"%rJ" ((USItype) (al)), \
"rI" ((USItype) (bl)) \
__CLOBBER_CC)
1991-12-24 05:31:09 +01:00
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (sh)), \
"=&r" ((USItype) (sl)) \
: "rJ" ((USItype) (ah)), \
"rI" ((USItype) (bh)), \
"rJ" ((USItype) (al)), \
"rI" ((USItype) (bl)) \
__CLOBBER_CC)
#if defined (__sparc_v8__)
1991-12-24 05:31:09 +01:00
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (w1)), \
"=r" ((USItype) (w0)) \
: "r" ((USItype) (u)), \
"r" ((USItype) (v)))
#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1991-12-24 05:31:09 +01:00
__asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
: "=&r" ((USItype) (__q)), \
"=&r" ((USItype) (__r)) \
: "r" ((USItype) (__n1)), \
"r" ((USItype) (__n0)), \
"r" ((USItype) (__d)))
1991-12-24 05:31:09 +01:00
#else
#if defined (__sparclite__)
/* This has hardware multiply but not divide. It also has two additional
instructions scan (ffs from high bit) and divscc. */
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("umul %2,%3,%1;rd %%y,%0" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (w1)), \
"=r" ((USItype) (w0)) \
: "r" ((USItype) (u)), \
"r" ((USItype) (v)))
#define udiv_qrnnd(q, r, n1, n0, d) \
__asm__ ("! Inlined udiv_qrnnd\n" \
" wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
" tst %%g0\n" \
" divscc %3,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%%g1\n" \
" divscc %%g1,%4,%0\n" \
" rd %%y,%1\n" \
" bl,a 1f\n" \
" add %1,%4,%1\n" \
"1: ! End of inline udiv_qrnnd" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (q)), \
"=r" ((USItype) (r)) \
: "r" ((USItype) (n1)), \
"r" ((USItype) (n0)), \
"rI" ((USItype) (d)) \
: "g1" __AND_CLOBBER_CC)
#define UDIV_TIME 37
#define count_leading_zeros(count, x) \
do { \
__asm__ ("scan %1,1,%0" \
: "=r" ((USItype) (count)) \
: "r" ((USItype) (x))); \
} while (0)
/* Early sparclites return 63 for an argument of 0, but they warn that future
implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
undefined. */
#else
1991-12-24 05:31:09 +01:00
/* SPARC without integer multiplication and divide instructions.
(i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
#define umul_ppmm(w1, w0, u, v) \
__asm__ ("! Inlined umul_ppmm\n" \
" wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
" sra %3,31,%%o5 ! Don't move this insn\n" \
" and %2,%%o5,%%o5 ! Don't move this insn\n" \
" andcc %%g0,0,%%g1 ! Don't move this insn\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,%3,%%g1\n" \
" mulscc %%g1,0,%%g1\n" \
" add %%g1,%%o5,%0\n" \
" rd %%y,%1" \
1996-07-04 00:07:53 +02:00
: "=r" ((USItype) (w1)), \
"=r" ((USItype) (w0)) \
: "%rI" ((USItype) (u)), \
"r" ((USItype) (v)) \
: "g1", "o5" __AND_CLOBBER_CC)
1991-12-24 05:31:09 +01:00
#define UMUL_TIME 39 /* 39 instructions */
/* It's quite necessary to add this much assembler for the sparc.
The default udiv_qrnnd (in C) is more than 10 times slower! */
#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
__asm__ ("! Inlined udiv_qrnnd\n" \
" mov 32,%%g1\n" \
" subcc %1,%2,%%g0\n" \
"1: bcs 5f\n" \
" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
" sub %1,%2,%1 ! this kills msb of n\n" \
" addx %1,%1,%1 ! so this can't give carry\n" \
" subcc %%g1,1,%%g1\n" \
"2: bne 1b\n" \
" subcc %1,%2,%%g0\n" \
" bcs 3f\n" \
" addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
" b 3f\n" \
" sub %1,%2,%1 ! this kills msb of n\n" \
"4: sub %1,%2,%1\n" \
"5: addxcc %1,%1,%1\n" \
" bcc 2b\n" \
" subcc %%g1,1,%%g1\n" \
"! Got carry from n. Subtract next step to cancel this carry.\n" \
" bne 4b\n" \
" addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
" sub %1,%2,%1\n" \
"3: xnor %0,0,%0\n" \
" ! End of inline udiv_qrnnd" \
: "=&r" ((USItype) (__q)), \
"=&r" ((USItype) (__r)) \
: "r" ((USItype) (__d)), \
"1" ((USItype) (__n1)), \
"0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
#define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
#endif /* __sparclite__ */
#endif /* __sparc_v8__ */
#endif /* sparc32 */
1991-12-24 05:31:09 +01:00
#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
&& W_TYPE_SIZE == 64
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addcc %r4,%5,%1\n\t" \
"add %r2,%3,%0\n\t" \
"bcs,a,pn %%xcc, 1f\n\t" \
"add %0, 1, %0\n" \
"1:" \
: "=r" ((UDItype)(sh)), \
"=&r" ((UDItype)(sl)) \
: "%rJ" ((UDItype)(ah)), \
"rI" ((UDItype)(bh)), \
"%rJ" ((UDItype)(al)), \
"rI" ((UDItype)(bl)) \
__CLOBBER_CC)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subcc %r4,%5,%1\n\t" \
"sub %r2,%3,%0\n\t" \
"bcs,a,pn %%xcc, 1f\n\t" \
"sub %0, 1, %0\n\t" \
"1:" \
: "=r" ((UDItype)(sh)), \
"=&r" ((UDItype)(sl)) \
: "rJ" ((UDItype)(ah)), \
"rI" ((UDItype)(bh)), \
"rJ" ((UDItype)(al)), \
"rI" ((UDItype)(bl)) \
__CLOBBER_CC)
#define umul_ppmm(wh, wl, u, v) \
do { \
UDItype tmp1, tmp2, tmp3, tmp4; \
__asm__ __volatile__ ( \
"srl %7,0,%3\n\t" \
"mulx %3,%6,%1\n\t" \
"srlx %6,32,%2\n\t" \
"mulx %2,%3,%4\n\t" \
"sllx %4,32,%5\n\t" \
"srl %6,0,%3\n\t" \
"sub %1,%5,%5\n\t" \
"srlx %5,32,%5\n\t" \
"addcc %4,%5,%4\n\t" \
"srlx %7,32,%5\n\t" \
"mulx %3,%5,%3\n\t" \
"mulx %2,%5,%5\n\t" \
"sethi %%hi(0x80000000),%2\n\t" \
"addcc %4,%3,%4\n\t" \
"srlx %4,32,%4\n\t" \
"add %2,%2,%2\n\t" \
"movcc %%xcc,%%g0,%2\n\t" \
"addcc %5,%4,%5\n\t" \
"sllx %3,32,%3\n\t" \
"add %1,%3,%1\n\t" \
"add %5,%2,%0" \
: "=r" ((UDItype)(wh)), \
"=&r" ((UDItype)(wl)), \
"=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
: "r" ((UDItype)(u)), \
"r" ((UDItype)(v)) \
__CLOBBER_CC); \
} while (0)
#define UMUL_TIME 96
#define UDIV_TIME 230
#endif /* sparc64 */
#if defined (__vax__) && W_TYPE_SIZE == 32
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
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: "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \
: "%0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"%1" ((USItype) (al)), \
"g" ((USItype) (bl)))
1991-12-24 05:31:09 +01:00
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1996-07-04 00:07:53 +02:00
: "=g" ((USItype) (sh)), \
"=&g" ((USItype) (sl)) \
: "0" ((USItype) (ah)), \
"g" ((USItype) (bh)), \
"1" ((USItype) (al)), \
"g" ((USItype) (bl)))
1991-12-24 05:31:09 +01:00
#define umul_ppmm(xh, xl, m0, m1) \
do { \
union { \
UDItype __ll; \
struct {USItype __l, __h;} __i; \
} __xx; \
USItype __m0 = (m0), __m1 = (m1); \
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__asm__ ("emul %1,%2,$0,%0" \
: "=r" (__xx.__ll) \
: "g" (__m0), \
"g" (__m1)); \
(xh) = __xx.__i.__h; \
(xl) = __xx.__i.__l; \
(xh) += ((((SItype) __m0 >> 31) & __m1) \
+ (((SItype) __m1 >> 31) & __m0)); \
1991-12-24 05:31:09 +01:00
} while (0)
#define sdiv_qrnnd(q, r, n1, n0, d) \
do { \
union {DItype __ll; \
struct {SItype __l, __h;} __i; \
} __xx; \
__xx.__i.__h = n1; __xx.__i.__l = n0; \
__asm__ ("ediv %3,%2,%0,%1" \
: "=g" (q), "=g" (r) \
: "g" (__xx.__ll), "g" (d)); \
} while (0)
1991-12-24 05:31:09 +01:00
#endif /* __vax__ */
invoke.texi (C6X Options): New section. gcc/ * doc/invoke.texi (C6X Options): New section. * doc/md.texi (TI C6X family): New section. * config.gcc: Handle tic6x, in particular tic6x-*-elf and tic6x-*-uclinux. * longlong.h (add_ssaaaa, __umulsidi3, umul_ppmm, count_leading_zeros, count_trailing_zeros, UMUL_TIME, UDIV_TIME): Provide C6X definitions. * config/c6x/c6x.md: New file. * config/c6x/constraints.md: New file. * config/c6x/predicates.md: New file. * config/c6x/c6x-sched.md.in: New file. * config/c6x/c6x-sched.md: New file. * config/c6x/gensched.sh: New file. * config/c6x/c6x-mult.md.in: New file. * config/c6x/genmult.sh: New file. * config/c6x/c6x-mult.md: New file. * config/c6x/sync.md: New file. * config/c6x/c6x-protos.h: New file. * config/c6x/sfp-machine.h: New file. * config/c6x/c6x.c: New file. * config/c6x/c6x.h: New file. * config/c6x/crti.s: New file. * config/c6x/crtn.s: New file. * config/c6x/lib1funcs.asm: New file. * config/c6x/c6x-modes.def: New file. * config/c6x/genopt.sh: New file. * config/c6x/c6x.opt: New file. * config/c6x/c6x-tables.opt: New file. * config/c6x/c6x-opts.h: New file. * config/c6x/c6x-isas.def: New file. * config/c6x/elf.h: New file. * config/c6x/elf-common.h: New file. * config/c6x/uclinux-elf.h: New file. * config/c6x/t-c6x: New file. * config/c6x/t-c6x-elf: New file. * config/c6x/t-c6x-uclinux: New file. * config/c6x/t-c6x-softfp: New file. * config/c6x/gtd.c: New file. * config/c6x/gtf.c: New file. * config/c6x/ltd.c: New file. * config/c6x/ltf.c: New file. * config/c6x/ged.c: New file. * config/c6x/gef.c: New file. * config/c6x/led.c: New file. * config/c6x/lef.c: New file. * config/c6x/eqd.c: New file. * config/c6x/eqf.c: New file. * config/c6x/libgcc-c6xeabi.ver: New file. contrib/ * gcc_update: Add C6X generated files. * contrib/config-list.mk: Add c6x-elf and c6x-uclinux. libgcc/ * config.host: Handle tic6x-*-*. * config/c6x/c6x-abi.h: New file. From-SVN: r176308
2011-07-15 11:36:40 +02:00
#ifdef _TMS320C6X
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do \
{ \
UDItype __ll; \
__asm__ ("addu .l1 %1, %2, %0" \
: "=a" (__ll) : "a" (al), "a" (bl)); \
(sl) = (USItype)__ll; \
(sh) = ((USItype)(__ll >> 32)) + (ah) + (bh); \
} \
while (0)
#ifdef _TMS320C6400_PLUS
#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
#define umul_ppmm(w1, w0, u, v) \
do { \
UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
(w1) = (USItype) (__x >> 32); \
(w0) = (USItype) (__x); \
} while (0)
#endif /* _TMS320C6400_PLUS */
#define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
#ifdef _TMS320C6400
#define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
#endif
#define UMUL_TIME 4
#define UDIV_TIME 40
#endif /* _TMS320C6X */
#if defined (__xtensa__) && W_TYPE_SIZE == 32
/* This code is not Xtensa-configuration-specific, so rely on the compiler
to expand builtin functions depending on what configuration features
are available. This avoids library calls when the operation can be
performed in-line. */
#define umul_ppmm(w1, w0, u, v) \
do { \
DWunion __w; \
__w.ll = __builtin_umulsidi3 (u, v); \
w1 = __w.s.high; \
w0 = __w.s.low; \
} while (0)
#define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
#define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
#define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
#endif /* __xtensa__ */
#if defined xstormy16
extern UHItype __stormy16_count_leading_zeros (UHItype);
#define count_leading_zeros(count, x) \
do \
{ \
UHItype size; \
\
/* We assume that W_TYPE_SIZE is a multiple of 16... */ \
for ((count) = 0, size = W_TYPE_SIZE; size; size -= 16) \
{ \
UHItype c; \
\
c = __clzhi2 ((x) >> (size - 16)); \
(count) += c; \
if (c != 16) \
break; \
} \
} \
while (0)
#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
#endif
#if defined (__z8000__) && W_TYPE_SIZE == 16
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
__asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
: "=r" ((unsigned int)(sh)), \
"=&r" ((unsigned int)(sl)) \
: "%0" ((unsigned int)(ah)), \
"r" ((unsigned int)(bh)), \
"%1" ((unsigned int)(al)), \
"rQR" ((unsigned int)(bl)))
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
__asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
: "=r" ((unsigned int)(sh)), \
"=&r" ((unsigned int)(sl)) \
: "0" ((unsigned int)(ah)), \
"r" ((unsigned int)(bh)), \
"1" ((unsigned int)(al)), \
"rQR" ((unsigned int)(bl)))
#define umul_ppmm(xh, xl, m0, m1) \
do { \
union {long int __ll; \
struct {unsigned int __h, __l;} __i; \
} __xx; \
unsigned int __m0 = (m0), __m1 = (m1); \
__asm__ ("mult %S0,%H3" \
: "=r" (__xx.__i.__h), \
"=r" (__xx.__i.__l) \
: "%1" (__m0), \
"rQR" (__m1)); \
(xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
(xh) += ((((signed int) __m0 >> 15) & __m1) \
+ (((signed int) __m1 >> 15) & __m0)); \
} while (0)
#endif /* __z8000__ */
1991-12-24 05:31:09 +01:00
#endif /* __GNUC__ */
/* If this machine has no inline assembler, use C macros. */
#if !defined (add_ssaaaa)
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
do { \
UWtype __x; \
1991-12-24 05:31:09 +01:00
__x = (al) + (bl); \
(sh) = (ah) + (bh) + (__x < (al)); \
(sl) = __x; \
} while (0)
#endif
#if !defined (sub_ddmmss)
#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
do { \
UWtype __x; \
1991-12-24 05:31:09 +01:00
__x = (al) - (bl); \
(sh) = (ah) - (bh) - (__x > (al)); \
(sl) = __x; \
} while (0)
#endif
/* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
smul_ppmm. */
#if !defined (umul_ppmm) && defined (smul_ppmm)
#define umul_ppmm(w1, w0, u, v) \
do { \
UWtype __w1; \
UWtype __xm0 = (u), __xm1 = (v); \
smul_ppmm (__w1, w0, __xm0, __xm1); \
(w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
+ (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
} while (0)
#endif
/* If we still don't have umul_ppmm, define it using plain C. */
1991-12-24 05:31:09 +01:00
#if !defined (umul_ppmm)
#define umul_ppmm(w1, w0, u, v) \
do { \
UWtype __x0, __x1, __x2, __x3; \
UHWtype __ul, __vl, __uh, __vh; \
1991-12-24 05:31:09 +01:00
\
__ul = __ll_lowpart (u); \
__uh = __ll_highpart (u); \
__vl = __ll_lowpart (v); \
__vh = __ll_highpart (v); \
\
__x0 = (UWtype) __ul * __vl; \
__x1 = (UWtype) __ul * __vh; \
__x2 = (UWtype) __uh * __vl; \
__x3 = (UWtype) __uh * __vh; \
1991-12-24 05:31:09 +01:00
\
__x1 += __ll_highpart (__x0);/* this can't give carry */ \
__x1 += __x2; /* but this indeed can */ \
if (__x1 < __x2) /* did we get it? */ \
__x3 += __ll_B; /* yes, add it in the proper pos. */ \
1991-12-24 05:31:09 +01:00
\
(w1) = __x3 + __ll_highpart (__x1); \
(w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
} while (0)
#endif
#if !defined (__umulsidi3)
#define __umulsidi3(u, v) \
({DWunion __w; \
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umul_ppmm (__w.s.high, __w.s.low, u, v); \
__w.ll; })
#endif
/* Define this unconditionally, so it can be used for debugging. */
#define __udiv_qrnnd_c(q, r, n1, n0, d) \
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do { \
UWtype __d1, __d0, __q1, __q0; \
UWtype __r1, __r0, __m; \
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__d1 = __ll_highpart (d); \
__d0 = __ll_lowpart (d); \
\
__r1 = (n1) % __d1; \
__q1 = (n1) / __d1; \
__m = (UWtype) __q1 * __d0; \
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__r1 = __r1 * __ll_B | __ll_highpart (n0); \
if (__r1 < __m) \
{ \
__q1--, __r1 += (d); \
if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
if (__r1 < __m) \
__q1--, __r1 += (d); \
} \
__r1 -= __m; \
\
__r0 = __r1 % __d1; \
__q0 = __r1 / __d1; \
__m = (UWtype) __q0 * __d0; \
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__r0 = __r0 * __ll_B | __ll_lowpart (n0); \
if (__r0 < __m) \
{ \
__q0--, __r0 += (d); \
if (__r0 >= (d)) \
if (__r0 < __m) \
__q0--, __r0 += (d); \
} \
__r0 -= __m; \
\
(q) = (UWtype) __q1 * __ll_B | __q0; \
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(r) = __r0; \
} while (0)
/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
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__udiv_w_sdiv (defined in libgcc or elsewhere). */
#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
#define udiv_qrnnd(q, r, nh, nl, d) \
do { \
USItype __r; \
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(q) = __udiv_w_sdiv (&__r, nh, nl, d); \
(r) = __r; \
} while (0)
#endif
/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
#if !defined (udiv_qrnnd)
#define UDIV_NEEDS_NORMALIZATION 1
#define udiv_qrnnd __udiv_qrnnd_c
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#endif
#if !defined (count_leading_zeros)
#define count_leading_zeros(count, x) \
do { \
UWtype __xr = (x); \
UWtype __a; \
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\
if (W_TYPE_SIZE <= 32) \
{ \
__a = __xr < ((UWtype)1<<2*__BITS4) \
? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
: (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
} \
else \
{ \
for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
if (((__xr >> __a) & 0xff) != 0) \
break; \
} \
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\
(count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
} while (0)
#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
#endif
#if !defined (count_trailing_zeros)
/* Define count_trailing_zeros using count_leading_zeros. The latter might be
defined in asm, but if it is not, the C version above is good enough. */
#define count_trailing_zeros(count, x) \
do { \
UWtype __ctz_x = (x); \
UWtype __ctz_c; \
count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
(count) = W_TYPE_SIZE - 1 - __ctz_c; \
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} while (0)
#endif
#ifndef UDIV_NEEDS_NORMALIZATION
#define UDIV_NEEDS_NORMALIZATION 0
#endif