Commit Graph

132756 Commits

Author SHA1 Message Date
GCC Administrator
051695352c Daily bump.
From-SVN: r215257
2014-09-15 00:16:54 +00:00
James Clarke
9c250803ad re PR target/61407 (Build errors on latest OS X 10.10 Yosemite with Xcode 6 on GCC 4.8.3)
PR target/61407

	* config/darwin-c.c (version_as_macro): Added extra 0 for OS X 10.10
	and above.
	* config/darwin-driver.c (darwin_find_version_from_kernel): Removed
	kernel version check to avoid incrementing it after every major OS X
	release.
	(darwin_default_min_version): Avoid static memory buffer.

	* gcc.dg/darwin-minversion-1.c: Fixed formatting
	* gcc.dg/darwin-minversion-2.c: Fixed formatting
	* gcc.dg/darwin-minversion-3.c: Fixed formatting
	* gcc.dg/darwin-minversion-4.c: Added test for OS X 10.10

Co-Authored-By: Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>

From-SVN: r215251
2014-09-14 08:05:43 +00:00
GCC Administrator
1a09cece35 Daily bump.
From-SVN: r215250
2014-09-14 00:16:43 +00:00
François-Xavier Coudert
a3b854b637 Fix mistake in commit 215237
From-SVN: r215242
2014-09-13 19:00:28 +00:00
Jan Hubicka
f83fba1eb0 tree.c (need_assembler_name_p): Store C++ type mangling only for aggregates.
* tree.c (need_assembler_name_p): Store C++ type mangling only
	for aggregates.

From-SVN: r215238
2014-09-13 16:12:20 +00:00
Francois-Xavier Coudert
3e89572920 * MAINTAINERS: Move myself to reviewers (Fortran).
From-SVN: r215237
2014-09-13 12:52:23 +00:00
Tobias Burnus
772e797a3f re PR fortran/63252 (tree_class_check_failed)
2014-09-13  Tobias Burnus  <burnus@net-b.de>

        PR fortran/63252
        * trans-decl.c (gfc_build_builtin_function_decls): Fix
        caf_unlock declaration.

From-SVN: r215236
2014-09-13 10:33:32 +02:00
Marek Polacek
05f30b866f re PR c++/60862 (bad location in invalid conversion error)
PR c++/60862
	* parser.c (cp_parser_postfix_expression) <case CPP_OPEN_PAREN>: Set
	location of a call expression.

	* g++.dg/diagnostic/pr60862.C: New test.

From-SVN: r215235
2014-09-13 07:54:40 +00:00
Marek Polacek
8909b58efa tree.c (protected_set_expr_location): Don't check whether T is non-null here.
* tree.c (protected_set_expr_location): Don't check whether T is
	non-null here.

From-SVN: r215234
2014-09-13 05:59:47 +00:00
GCC Administrator
401119e83a Daily bump.
From-SVN: r215233
2014-09-13 00:16:25 +00:00
DJ Delorie
862edcd15d msp430.md (extendhipsi2): Use 20-bit form of RLAM/RRAM.
* config/msp430/msp430.md (extendhipsi2): Use 20-bit form of RLAM/RRAM.
(extend_and_shift1_hipsi2): Likewise.
(extend_and_shift2_hipsi2): Likewise.

From-SVN: r215229
2014-09-12 14:13:39 -04:00
Jason Merrill
4ee28eb7ce re PR c++/63201 (Full specialization of a member variable template of a class template does not work)
PR c++/63201
	* decl.c (start_decl): Handle specialization of member variable
	template.
	* pt.c (check_explicit_specialization): Adjust error.

From-SVN: r215226
2014-09-12 10:39:25 -04:00
Jonathan Wakely
b6f866946b deque (__gnu_debug::deque): Make base class C++11 allocator aware.
* include/debug/deque (__gnu_debug::deque): Make base class C++11
	allocator aware.

From-SVN: r215223
2014-09-12 15:06:50 +01:00
David Malcolm
a5d567ec32 params 2 and 3 of reg_set_between_p
gcc/ChangeLog:
	* config/alpha/alpha.c (alpha_ra_ever_killed): Replace NULL_RTX
	with NULL when dealing with an insn.
	* config/sh/sh.c (sh_reorg): Strengthen local "last_float_move"
	from rtx to rtx_insn *.
	* rtl.h (reg_set_between_p): Strengthen params 2 and 3 from
	const_rtx to const rtx_insn *.
	* rtlanal.c (reg_set_between_p): Likewise, removing a checked cast.

From-SVN: r215222
2014-09-12 14:04:35 +00:00
Jonathan Wakely
bc5022d011 re PR libstdc++/59603 (std::random_shuffle tries to swap element with itself)
PR libstdc++/59603
	* include/bits/stl_algo.h (random_shuffle): Prevent self-swapping.
	* testsuite/25_algorithms/random_shuffle/59603.cc: New.

From-SVN: r215219
2014-09-12 14:30:35 +01:00
Trevor Saunders
139c9e3b9b fix ChangeLog typo
From-SVN: r215218
2014-09-12 12:36:37 +00:00
Trevor Saunders
4b49af1535 fix assert in hash_table pch routines
gcc/ChangeLog:

2014-09-12  Trevor Saunders  <tsaunders@mozilla.com>

	* hash-table.h (gt_pch_nx): don't call gt_pch_note_object within an
	assert.

From-SVN: r215216
2014-09-12 12:30:29 +00:00
Joseph Myers
8cc4b7a26d Remove LIBGCC2_HAS_?F_MODE target macros.
This patch removes the LIBGCC2_HAS_{SF,DF,XF,TF}_MODE target macros,
replacing them by predefines with -fbuilding-libgcc, together with a
target hook that can influence those predefines when needed.

The new default is that a floating-point mode is supported in libgcc
if (a) it passes the scalar_mode_supported_p hook (otherwise it's not
plausible for it to be supported in libgcc) and (b) it's one of those
four modes (since those are the modes for which libgcc hardcodes the
possibility of support).  The target hook can override the default
choice (in either direction) for modes that pass
scalar_mode_supported_p (although overriding in the direction of
returning true when the default would return false only makes sense if
all relevant functions are specially defined in libgcc for that
particular target).

The previous default settings depended on various settings such as
LIBGCC2_LONG_DOUBLE_TYPE_SIZE, as well as targets defining the above
target macros if the default wasn't correct.

The default scalar_mode_supported_p only declares a floating-point
mode to be supported if it matches one of float / double / long
double.  This means that in most cases where a mode is only supported
conditionally in libgcc (TFmode only supported if it's the mode of
long double, most commonly), the default gets things right.  Overrides
were needed in the following cases:

* SFmode would always have been supported in libgcc (the condition was
  BITS_PER_UNIT == 8, true for all current targets), but pdp11
  defaults to 64-bit float, and in that case SFmode would fail
  scalar_mode_supported_p.  I don't know if libgcc actually built for
  pdp11 (and the port may well no longer be being used), but this
  patch adds a scalar_mode_supported_p hook to it to ensure SFmode is
  treated as supported.

* Certain i386 and ia64 targets need the new hook to match the
  existing cases for when XFmode or TFmode support is present in
  libgcc.  For i386, the hook can always declare XFmode to be
  supported - the cases where it's not are the cases where long double
  is TFmode, in which case XFmode fails scalar_mode_supported_p[*] -
  but TFmode support needs to be conditional.  (And of the targets not
  defining LIBGCC2_HAS_TF_MODE before this patch, some defined
  LONG_DOUBLE_TYPE_SIZE to 64, so ensuring LIBGCC2_HAS_TF_MODE would
  always be false, while others did not define it, so allowing it to
  be true in the -mlong-double-128 case.  This patch matches that
  logic, although I suspect all the latter targets would have been
  broken if you tried to enable -mlong-double-128 by default, for lack
  of the soft-fp TFmode support in libgcc, which is separately
  configured.)

  [*] I don't know if it's deliberate not to support __float80 at all
  with -mlong-double-128.

In order to implement the default version of the new hook,
insn-modes.h was made to contain macros such as HAVE_TFmode for each
machine mode, so the default hook can contain conditionals on whether
XFmode and TFmode exist (to match the hardcoding of a list of modes in
libgcc).  This is also used in fortran/trans-types.c; previously it
had a conditional on defined(LIBGCC2_HAS_TF_MODE) (a bit dubious,
since it ignored the value of the macro), which is replaced by testing
defined(HAVE_TFmode), in conjunction with requiring
targetm.libgcc_floating_mode_supported_p.

(Fortran is testing something stronger than that hook: not only is
libgcc support required, but also libm or equivalent.  Thus, it has a
test for ENABLE_LIBQUADMATH_SUPPORT in the case that the mode is
TFmode and that's not the same as any of the three standard types.
The old and new tests are intended to accept exactly the same set of
modes for all targets.)

Apart from the four target macros eliminated by this patch, it gets us
closer to eliminating LIBGCC2_LONG_DOUBLE_TYPE_SIZE as well, though a
few more places using that macro need changing first.

Bootstrapped with no regressions on x86_64-unknown-linux-gnu; also
built cc1 for crosses to ia64-elf and pdp11-none as a minimal test of
changes for those targets.

gcc:
	* target.def (libgcc_floating_mode_supported_p): New hook.
	* targhooks.c (default_libgcc_floating_mode_supported_p): New
	function.
	* targhooks.h (default_libgcc_floating_mode_supported_p): Declare.
	* doc/tm.texi.in (LIBGCC2_HAS_DF_MODE, LIBGCC2_HAS_XF_MODE)
	(LIBGCC2_HAS_TF_MODE): Remove.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): New @hook.
	* doc/tm.texi: Regenerate.
	* genmodes.c (emit_insn_modes_h): Define HAVE_%smode for each
	machine mode.
	* system.h (LIBGCC2_HAS_SF_MODE, LIBGCC2_HAS_DF_MODE)
	(LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE): Poison.
	* config/i386/cygming.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/darwin.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/djgpp.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/dragonfly.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/freebsd.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/gnu-user-common.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/i386-interix.h (IX86_NO_LIBGCC_TFMODE): Define.
	* config/i386/i386.c (ix86_libgcc_floating_mode_supported_p): New
	function.
	(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
	* config/i386/i386elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/lynx.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/netbsd-elf.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/netbsd64.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/nto.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/openbsd.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/i386/openbsdelf.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/rtemself.h (IX86_NO_LIBGCC_TFMODE): Define.
	* config/i386/sol2.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/i386/vx-common.h (IX86_MAYBE_NO_LIBGCC_TFMODE): Define.
	* config/ia64/elf.h (IA64_NO_LIBGCC_TFMODE): Define.
	* config/ia64/freebsd.h (IA64_NO_LIBGCC_TFMODE): Define.
	* config/ia64/hpux.h (LIBGCC2_HAS_XF_MODE, LIBGCC2_HAS_TF_MODE):
	Remove.
	* config/ia64/ia64.c (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P):
	New macro.
	(ia64_libgcc_floating_mode_supported_p): New function.
	* config/ia64/linux.h (LIBGCC2_HAS_TF_MODE): Remove.
	* config/ia64/vms.h (IA64_NO_LIBGCC_XFMODE)
	(IA64_NO_LIBGCC_TFMODE): Define.
	* config/msp430/msp430.h (LIBGCC2_HAS_DF_MODE): Remove.
	* config/pdp11/pdp11.c (TARGET_SCALAR_MODE_SUPPORTED_P): New
	macro.
	(pdp11_scalar_mode_supported_p): New function.
	* config/rl78/rl78.h (LIBGCC2_HAS_DF_MODE): Remove.
	* config/rx/rx.h (LIBGCC2_HAS_DF_MODE): Remove.

gcc/c-family:
	* c-cppbuiltin.c (c_cpp_builtins): Define __LIBGCC_HAS_%s_MODE__
	macros for floating-point modes.

gcc/fortran:
	* trans-types.c (gfc_init_kinds): Check
	targetm.libgcc_floating_mode_supported_p for floating-point
	modes.  Check HAVE_TFmode instead of LIBGCC2_HAS_TF_MODE.

libgcc:
	* libgcc2.h (LIBGCC2_HAS_SF_MODE): Define using
	__LIBGCC_HAS_SF_MODE__.
	(LIBGCC2_HAS_DF_MODE): Define using __LIBGCC_HAS_DF_MODE__.
	(LIBGCC2_HAS_XF_MODE): Define using __LIBGCC_HAS_XF_MODE__.
	(LIBGCC2_HAS_TF_MODE): Define using __LIBGCC_HAS_TF_MODE__.
	* config/libbid/bid_gcc_intrinsics.h
	(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Do not define.
	(LIBGCC2_HAS_XF_MODE): Define using __LIBGCC_HAS_XF_MODE__.
	(LIBGCC2_HAS_TF_MODE): Define using __LIBGCC_HAS_TF_MODE__.
	* fixed-bit.h (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Do not define.
	(LIBGCC2_HAS_SF_MODE): Define using __LIBGCC_HAS_SF_MODE__.
	(LIBGCC2_HAS_DF_MODE): Define using __LIBGCC_HAS_DF_MODE__.

From-SVN: r215215
2014-09-12 13:05:18 +01:00
Richard Biener
2813904b11 re PR middle-end/63237 (error: invalid operand in unary operation)
2014-09-12  Richard Biener  <rguenther@suse.de>

	PR middle-end/63237
	* gimple-fold.c (get_maxval_strlen): Gimplify string length.

	* g++.dg/torture/pr63237.C: New testcase.

From-SVN: r215212
2014-09-12 11:06:49 +00:00
Marc Glisse
d9a72d17e6 tree.c (integer_each_onep): New function.
2014-09-12  Marc Glisse  <marc.glisse@inria.fr>

gcc/
	* tree.c (integer_each_onep): New function.
	* tree.h (integer_each_onep): Declare it.
	* fold-const.c (fold_binary_loc): Use it for ~A + 1 to -A and
	-A - 1 to ~A.  Disable (X & 1) ^ 1, (X ^ 1) & 1 and ~X & 1 to
	(X & 1) == 0 for vector and complex.
gcc/testsuite/
	* gcc.dg/vec-andxor1.c: New file.

From-SVN: r215209
2014-09-12 10:42:47 +00:00
Wilco Dijkstra
e4a9c55ade [AArch64] Add regmove_costs for Cortex-A57 and A53
2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c: (cortexa57_regmove_cost): New cost table for
  A57.
  (cortexa53_regmove_cost): New cost table for A53.  Increase GP2FP/FP2GP cost
  to spilling from integer to FP registers.

From-SVN: r215208
2014-09-12 09:46:25 +00:00
Wilco Dijkstra
20b32e50e2 [AArch64] Fix cost for Q register moves
2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Fix Q register
  move handling.
  (generic_regmove_cost): Undo raised FP2FP move cost as Q register moves are
  now handled correctly.

From-SVN: r215207
2014-09-12 09:42:42 +00:00
Wilco Dijkstra
3be0766211 [AArch64] Add cost handling of CALLER_SAVE_REGS and POINTER_REGS
2014-09-12  Wilco Dijkstra  <wdijkstr@arm.com>

  * gcc/config/aarch64/aarch64.c (aarch64_register_move_cost): Add cost handling
  of CALLER_SAVE_REGS and POINTER_REGS.

From-SVN: r215206
2014-09-12 09:39:42 +00:00
Wilco Dijkstra
e533e26c0a [Ree] Ensure inserted copy don't change the number of hard registers
2014-09-12  Wilco Dijkstra  <wilco.dijkstra@arm.com>

  gcc/
    * ree.c (combine_reaching_defs): Ensure inserted copy don't change the
    number of hard registers.

From-SVN: r215205
2014-09-12 09:29:16 +00:00
Alexander Ivchenko
6ead0238de AVX-512. Extend vpternlog, valign, vrotate insns.
gcc/
	* config/i386/sse.md
	(define_mode_iterator VI48_AVX512VL): New.
	(define_expand "<avx512>_vternlog<mode>_maskz"): Rename from
	"avx512f_vternlog<mode>_maskz" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode><sd_maskz_name>"): Rename
	from "avx512f_vternlog<mode><sd_maskz_name>" and update mode iterator.
	(define_insn "<avx512>_vternlog<mode>_mask"): Rename from
	"avx512f_vternlog<mode>_mask" and update mode iterator.
	(define_insn "<mask_codefor><avx512>_align<mode><mask_name>"): Rename
	from "<mask_codefor>avx512f_align<mode><mask_name>" and update mode
	iterator.
	(define_insn "<avx512>_<rotate>v<mode><mask_name>"): Rename from
	"avx512f_<rotate>v<mode><mask_name>" and update mode iterator.
	(define_insn "<avx512>_<rotate><mode><mask_name>"): Rename from
	"avx512f_<rotate><mode><mask_name>" and update mode iterator.
	(define_insn "clz<mode>2<mask_name>"): Use VI48_AVX512VL mode iterator.
	(define_insn "<mask_codefor>conflict<mode><mask_name>"): Ditto.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215203
2014-09-12 07:38:47 +00:00
Alexander Ivchenko
575d952c5d AVX-512. Extend max/min insn patterns.
gcc/
	* config/i386/sse.md (VI128_256): Delete.
	(define_mode_iterator VI124_256): New.
	(define_mode_iterator VI124_256_AVX512F_AVX512BW): Ditto.
	(define_expand "<code><mode>3<mask_name><round_name>"): Delete.
	(define_expand "<code><VI124_256_AVX512F_AVX512BW:mode>3"): New.
	(define_insn "*avx2_<code><VI124_256:mode>3"): Rename from
	"*avx2_<code><mode>3<mask_name><round_name>" and update mode iterator.
	(define_expand "<code><VI48_AVX512VL:mode>3_mask"): New.
	(define_insn "*avx512bw_<code><VI48_AVX512VL:mode>3<mask_name>"): Ditto.
	(define_insn "<mask_codefor><code><mode>3<mask_name>"): Update mode
	iterator.
	(define_expand "<code><VI8_AVX2:mode>3"): Update pettern generation
	in presence of AVX-512.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215202
2014-09-12 07:36:59 +00:00
Alexander Ivchenko
be746da138 AVX-512. Extend gather insn patterns.
gcc/
	* config/i386/sse.md
	(define_expand "<avx512>_gathersi<mode>"): Rename from
	"avx512f_gathersi<mode>".
	(define_insn "*avx512f_gathersi<mode>"): Use VI48F.
	(define_insn "*avx512f_gathersi<mode>_2"): Ditto.
	(define_expand "<avx512>_gatherdi<mode>"): Rename from
	"avx512f_gatherdi<mode>".
	(define_insn "*avx512f_gatherdi<mode>"): Use VI48F.
	(define_insn "*avx512f_gatherdi<mode>_2"): Use VI48F, add 128/256-bit
	wide versions.
	(define_expand "<avx512>_scattersi<mode>"): Rename from
	"avx512f_scattersi<mode>".
	(define_insn "*avx512f_scattersi<mode>"): Use VI48F.
	(define_expand "<avx512>_scatterdi<mode>"): Rename from
	"avx512f_scatterdi<mode>".
	(define_insn "*avx512f_scatterdi<mode>"): Use VI48F.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215201
2014-09-12 07:34:31 +00:00
Richard Sandiford
19c708dc83 ira.h (ira_finish_once): Delete.
gcc/
	* ira.h (ira_finish_once): Delete.
	* ira-int.h (target_ira_int::~target_ira_int): Declare.
	(target_ira_int::free_ira_costs): Likewise.
	(target_ira_int::free_register_move_costs): Likewise.
	(ira_finish_costs_once): Delete.
	* ira.c (free_register_move_costs): Replace with...
	(target_ira_int::free_register_move_costs): ...this new function.
	(target_ira_int::~target_ira_int): Define.
	(ira_init): Call free_register_move_costs as a member function rather
	than a global function.
	(ira_finish_once): Delete.
	* ira-costs.c (free_ira_costs): Replace with...
	(target_ira_int::free_ira_costs): ...this new function.
	(ira_init_costs): Call free_ira_costs as a member function rather
	than a global function.
	(ira_finish_costs_once): Delete.
	* target-globals.c (target_globals::~target_globals): Call the
	target_ira_int destructor.
	* toplev.c: Include lra.h.
	(finalize): Call lra_finish_once rather than ira_finish_once.

From-SVN: r215200
2014-09-12 07:27:10 +00:00
GCC Administrator
44fc1b7b63 Daily bump.
From-SVN: r215199
2014-09-12 00:16:51 +00:00
Jan Hubicka
1ee85ee19b common.opt (flto-odr-type-merging): New flag.
* common.opt (flto-odr-type-merging): New flag.
	* ipa-deivrt.c (hash_type_name): Use ODR names for hasing if availale.
	(types_same_for_odr): Likewise.
	(odr_subtypes_equivalent_p): Likewise.
	(add_type_duplicate): Do not walk type variants.
	(register_odr_type): New function.
	* ipa-utils.h (register_odr_type): Declare.
	(odr_type_p): New function.
	* langhooks.c (lhd_set_decl_assembler_name): Do not compute
	TYPE_DECLs
	* doc/invoke.texi (-flto-odr-type-merging): Document.
	* tree.c (need_assembler_name_p): Compute ODR names when asked
	for it.
	* tree.h (DECL_ASSEMBLER_NAME): Update comment.

	* lto.c (lto_read_decls): Register ODR types.

From-SVN: r215196
2014-09-11 23:16:42 +00:00
H.J. Lu
bc9132dee6 Also turn off OPTION_MASK_ABI_X32 for -m16
PR target/63228
	* config/i386/i386.c (ix86_option_override_internal): Also turn
	off OPTION_MASK_ABI_X32 for -m16.

From-SVN: r215194
2014-09-11 15:18:06 -07:00
Segher Boessenkool
7043e9680c rs6000.md (rs6000_mftb_<mode>): Use mode iterator GPR instead of P.
2014-09-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/rs6000.md (rs6000_mftb_<mode>): Use mode iterator
	GPR instead of P.

From-SVN: r215193
2014-09-11 23:50:31 +02:00
Marc Glisse
179b5a554c re PR target/58757 (Advertise the lack of denormal support on alpha without -mieee)
2014-09-11  Marc Glisse  <marc.glisse@inria.fr>

	PR target/58757
gcc/c-family/
	* c-cppbuiltin.c (builtin_define_float_constants): Correct
	__*_DENORM_MIN__ without denormals.
gcc/
	* ginclude/float.h (FLT_TRUE_MIN, DBL_TRUE_MIN, LDBL_TRUE_MIN):
	Directly forward to __*_DENORM_MIN__.
gcc/testsuite/
	* gcc.dg/c11-true_min-1.c: New testcase.

From-SVN: r215191
2014-09-11 20:55:37 +00:00
David Malcolm
a827d9b194 Introduce LABEL_REF_LABEL
gcc/ChangeLog:
2014-09-11  David Malcolm  <dmalcolm@redhat.com>

	* rtl.h (LABEL_REF_LABEL): New macro.

	* alias.c (rtx_equal_for_memref_p): Use LABEL_REF_LABEL in place
	of XEXP (, 0), where we know that we have a LABEL_REF.
	* cfgbuild.c (make_edges): Likewise.
	(purge_dead_tablejump_edges): Likewise.
	* cfgexpand.c (convert_debug_memory_address): Likewise.
	* cfgrtl.c (patch_jump_insn): Likewise.
	* combine.c (distribute_notes): Likewise.
	* cse.c (hash_rtx_cb): Likewise.
	(exp_equiv_p): Likewise.
	(fold_rtx): Likewise.
	(check_for_label_ref): Likewise.
	* cselib.c (rtx_equal_for_cselib_1): Likewise.
	(cselib_hash_rtx): Likewise.
	* emit-rtl.c (mark_label_nuses): Likewise.
	* explow.c (convert_memory_address_addr_space): Likewise.
	* final.c (output_asm_label): Likewise.
	(output_addr_const): Likewise.
	* gcse.c (add_label_notes): Likewise.
	* genconfig.c (walk_insn_part): Likewise.
	* genrecog.c (validate_pattern): Likewise.
	* ifcvt.c (cond_exec_get_condition): Likewise.
	(noce_emit_store_flag): Likewise.
	(noce_get_alt_condition): Likewise.
	(noce_get_condition): Likewise.
	* jump.c (maybe_propagate_label_ref): Likewise.
	(mark_jump_label_1): Likewise.
	(redirect_exp_1): Likewise.
	(rtx_renumbered_equal_p): Likewise.
	* lra-constraints.c (operands_match_p): Likewise.
	* reload.c (operands_match_p): Likewise.
	(find_reloads): Likewise.
	* reload1.c (set_label_offsets): Likewise.
	* reorg.c (get_branch_condition): Likewise.
	* rtl.c (rtx_equal_p_cb): Likewise.
	(rtx_equal_p): Likewise.
	* rtlanal.c (reg_mentioned_p): Likewise.
	(rtx_referenced_p): Likewise.
	(get_condition): Likewise.
	* sched-vis.c (print_value): Likewise.
	* varasm.c (const_hash_1): Likewise.
	(compare_constant): Likewise.
	(const_rtx_hash_1): Likewise.
	(output_constant_pool_1): Likewise.

From-SVN: r215190
2014-09-11 20:47:39 +00:00
Segher Boessenkool
e4fb6f093c htm.md (tabort, [...]): Use xor instead of minus.
2014-09-11  Segher Boessenkool  <segher@kernel.crashing.org>

	* config/rs6000/htm.md (tabort, tabortdc, tabortdci, tabortwc,
	tabortwci, tbegin, tcheck, tend, trechkpt, treclaim, tsr): Use xor
	instead of minus.
	* config/rs6000/vector.md (cr6_test_for_zero_reverse,
	cr6_test_for_lt_reverse): Ditto.

From-SVN: r215187
2014-09-11 20:29:50 +02:00
Paolo Carlini
450bfd7d5c re PR c++/61489 (Wrong warning with -Wmissing-field-initializers.)
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* doc/invoke.texi ([-Wmissing-field-initializers]): Update.

/cp
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* typeck2.c (process_init_constructor_record): Do not warn about
	missing field initializer if EMPTY_CONSTRUCTOR_P (init).

/testsuite
2014-09-11  Paolo Carlini  <paolo.carlini@oracle.com>

	PR c++/61489
	* g++.dg/warn/Wmissing-field-initializers-1.C: New.
	* g++.old-deja/g++.other/warn5.C: Adjust.

From-SVN: r215186
2014-09-11 18:08:24 +00:00
Alan Lawrence
bc138f7bee [AArch64] Simplify vreinterpret for float64x1_t using casts.
* config/aarch64/aarch64-builtins.c (aarch64_types_unop_su_qualifiers,
	TYPES_REINTERP_SU, aarch64_types_unop_sp_qualifiers, TYPE_REINTERP_SP,
	aarch64_types_unop_us_qualifiers, TYPES_REINTERP_US,
	aarch64_types_unop_ps_qualifiers, TYPES_REINTERP_PS, BUILTIN_VD):
	Delete.

	(aarch64_fold_builtin): Remove all reinterpret cases.

	* config/aarch64/aarch64-protos.h (aarch64_simd_reinterpret): Delete.

	* config/aarch64/aarch64-simd-builtins.def (reinterpret*) : Delete.

	* config/aarch64/aarch64-simd.md (aarch64_reinterpretv8qi<mode>,
	aarch64_reinterpretv4hi<mode>, aarch64_reinterpretv2si<mode>,
	aarch64_reinterpretv2sf<mode>, aarch64_reinterpretdi<mode>,
	aarch64_reinterpretv1df<mode>, aarch64_reinterpretv16qi<mode>,
	aarch64_reinterpretv8hi<mode>, aarch64_reinterpretv4si<mode>,
	aarch64_reinterpretv4sf<mode>, aarch64_reinterpretv2di<mode>,
	aarch64_reinterpretv2df<mode>): Delete.

	* config/aarch64/aarch64.c (aarch64_simd_reinterpret): Delete.

	* config/aarch64/arm_neon.h (vreinterpret_p8_f64,
	vreinterpret_p16_f64, vreinterpret_f32_f64, vreinterpret_f64_f32,
	vreinterpret_f64_p8, vreinterpret_f64_p16, vreinterpret_f64_s8,
	vreinterpret_f64_s16, vreinterpret_f64_s32, vreinterpret_f64_u8,
	vreinterpret_f64_u16, vreinterpret_f64_u32, vreinterpret_s64_f64,
	vreinterpret_u64_f64, vreinterpret_s8_f64, vreinterpret_s16_f64,
	vreinterpret_s32_f64, vreinterpret_u8_f64, vreinterpret_u16_f64,
	vreinterpret_u32_f64): Use cast.

	* config/aarch64/iterators.md (VD_RE): Delete.

From-SVN: r215180
2014-09-11 16:16:24 +00:00
Alan Lawrence
fdaddc1b0b [AArch64] Replace temporary inline assembler for vset_lane
* config/aarch64/arm_neon.h (aarch64_vset_lane_any): New (*2).
	(vset_lane_f32, vset_lane_f64, vset_lane_p8, vset_lane_p16,
	vset_lane_s8, vset_lane_s16, vset_lane_s32, vset_lane_s64,
	vset_lane_u8, vset_lane_u16, vset_lane_u32, vset_lane_u64,
	vsetq_lane_f32, vsetq_lane_f64, vsetq_lane_p8, vsetq_lane_p16,
	vsetq_lane_s8, vsetq_lane_s16, vsetq_lane_s32, vsetq_lane_s64,
	vsetq_lane_u8, vsetq_lane_u16, vsetq_lane_u32, vsetq_lane_u64):
	Replace inline assembler with __aarch64_vset_lane_any.

From-SVN: r215179
2014-09-11 15:34:11 +00:00
Alan Lawrence
8acf549a44 [AArch64 Testsuite] Add execution test of vset(q?)_lane intrinsics.
* gcc.target/aarch64/vset_lane_1.c: New test.

From-SVN: r215177
2014-09-11 14:49:23 +00:00
James Greenhalgh
dd57b790a4 [AArch64] Cheap fix for argument types of vmull_high_lane_{us}{16,32}
gcc/

	* config/aarch64/arm_neon.h (vmull_high_lane_s16): Fix argument
	types.
	(vmull_high_lane_s32): Likewise.
	(vmull_high_lane_u16): Likewise.
	(vmull_high_lane_u32): Likewise.

From-SVN: r215176
2014-09-11 14:39:41 +00:00
Jason Merrill
c9e8561ef6 re PR c++/63139 (Class-scope typedef overwrites typedef of previously defined class)
PR c++/63139
	* pt.c (tsubst_pack_expansion): Simplify substitution into T....
	(tsubst): Don't throw away PACK_EXPANSION_EXTRA_ARGS.

From-SVN: r215171
2014-09-11 09:50:27 -04:00
Jason Merrill
89632536fc re PR c++/58678 (pykde4-4.11.2 link error (devirtualization too trigger happy))
PR c++/58678
	* ipa-devirt.c (ipa_devirt): Don't check DECL_COMDAT.

From-SVN: r215168
2014-09-11 08:12:28 -04:00
Jonathan Wakely
8aed2f2f63 re PR libstdc++/63219 (Superfluous template parameter in match_result::format overload)
PR libstdc++/63219
	* include/bits/regex.h (match_results::format): Remove stray template
	parameter.
	* include/bits/regex_compiler.h (_RegexTranslator::_RegexTranslator):
	Remove parameter name to avoid -Wunused-parameter warning.
	* include/bits/regex_executor.h (_State_info::_State_info): Reorder
	mem-initializers to avoid -Wreorder warning.
	* include/bits/regex_executor.tcc (_Executor::_M_word_boundary):
	Remove parameter name to avoid -Wunused-parameter warning.
	* include/bits/regex_scanner.tcc (_Scanner::_M_advance): Add braces
	to avoid -Wempty-body warning when not in debug mode.

From-SVN: r215160
2014-09-11 11:01:20 +01:00
Bernd Schmidt
21a16932df Fix declarations in some tests.
* gcc.dg/compat/struct-by-value-13_main.c (struct_by_value_13_x):
	Fix declaration.
	* gcc.dg/compat/struct-by-value-16a_main.c (struct_by_value_16a_x):
	Fix declaration.
	* gcc.dg/compat/struct-by-value-17a_main.c (struct_by_value_17a_x):
	Fix declaration.
	* gcc.dg/compat/struct-by-value-18a_main.c (struct_by_value_18a_x):
	Fix declaration.

From-SVN: r215158
2014-09-11 09:07:23 +00:00
Jakub Jelinek
1138382be4 linux64.S: Emit .note.GNU-stack even when POWERPC64 is not defined.
* src/powerpc/linux64.S: Emit .note.GNU-stack even when
	POWERPC64 is not defined.
	* src/powerpc/linux64_closure.S: Likewise.  Also test _CALL_ELF == 2.

From-SVN: r215155
2014-09-11 11:03:49 +02:00
Georg-Johann Lay
ea3f2b240f re PR target/63223 ([avr] Make jumptables work with -Wl,--section-start,.text=)
gcc/
	PR target/63223
	* config/avr/avr.md (*tablejump.3byte-pc): New insn.
	(*tablejump): Restrict to !AVR_HAVE_EIJMP_EICALL.  Add void clobber.
	(casesi): Expand to *tablejump.3byte-pc if AVR_HAVE_EIJMP_EICALL.
libgcc/
	PR target/63223
	* config/avr/libgcc.S (__tablejump2__): Rewrite to use RAMPZ, ELPM
	and R24 as needed.  Make work for all devices and .text locations.
	(__do_global_ctors, __do_global_dtors): Use word addresses.
	(__tablejump__, __tablejump_elpm__): Remove functions.
	* t-avr (LIB1ASMFUNCS): Remove _tablejump, _tablejump_elpm.
	Add _tablejump2.
	(XICALL, XIJMP): New macros.

From-SVN: r215152
2014-09-11 08:08:17 +00:00
Alexander Ivchenko
c883e5fb6a AVX-512. Add vperm[it]2 insns support.
gcc/
	* config/i386/sse.md
	(define_expand "<avx512>_vpermi2var<VI48F:mode>3_maskz"): Rename from
	"avx512f_vpermi2var<mode>3_maskz" and update mode iterator.
	(define_expand "<avx512>_vpermi2var<VI2_AVX512VL:mode>3_maskz"):
	New.
	(define_insn "<avx512>_vpermi2var<VI48F:mode>3<sd_maskz_name>"): Rename
	from "avx512f_vpermi2var<mode>3<sd_maskz_name>" and update mode
	iterator.
	(define_insn "<avx512>_vpermi2var<VI2_AVX512VL:mode>3<sd_maskz_name>"):
	New.
	(define_insn "<avx512>_vpermi2var<VI48F:mode>3_mask"): Rename from
	"avx512f_vpermi2var<mode>3_mask" and update mode iterator.
	(define_insn "<avx512>_vpermi2var<VI2_AVX512VL:mode>3_mask"): New.
	(define_expand "<avx512>_vpermt2var<VI48F:mode>3_maskz"): Rename from
	"avx512f_vpermt2var<mode>3_maskz" and update mode iterator.
	(define_expand "<avx512>_vpermt2var<VI2_AVX512VL:mode>3_maskz"): New.
	(define_insn "<avx512>_vpermt2var<VI48F:mode>3<sd_maskz_name>"): Rename
	from "avx512f_vpermt2var<mode>3<sd_maskz_name>" and update mode
	iterator.
	(define_insn "<avx512>_vpermt2var<VI2_AVX512VL:mode>3<sd_maskz_name>"):
	New.
	(define_insn "<avx512>_vpermt2var<VI48F:mode>3_mask"): Rename from
	"avx512f_vpermt2var<mode>3_mask" and update mode iterator.
	(define_insn "<avx512>_vpermt2var<VI2_AVX512VL:mode>3_mask"): New.


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215151
2014-09-11 06:52:30 +00:00
Jan Hubicka
7c46e07ba4 varpool.c (varpool_node::ctor_useable_for_folding_p): Do not try to access removed nodes.
* varpool.c (varpool_node::ctor_useable_for_folding_p): Do not try
	to access removed nodes.

From-SVN: r215150
2014-09-11 06:48:23 +00:00
Jan Hubicka
412c4af7f1 re PR middle-end/63186 (Undefined .L* symbols because of fnsplit)
PR tree-optimization/63186
	* ipa-split.c (test_nonssa_use): Skip nonforced labels.
	(mark_nonssa_use): Likewise.
	(verify_non_ssa_vars): Verify all header blocks for label
	definitions.

	* gcc.dg/pr63186.c: New testcase.

From-SVN: r215149
2014-09-11 06:46:23 +00:00
Alexander Ivchenko
cf92ae7f06 AVX-512. Extend vpermvar insn patterns.
gcc/
	* config/i386/sse.md
	(define_mode_attr avx2_avx512): Rename from avx2_avx512bw.
	(define_mode_iterator VI48F_256_512): Extend to AVX-512VL.
	(define_insn "<avx2_avx512>_permvar<mode><mask_name>"): Rename from
	"<avx2_avx512f>_permvar<mode><mask_name>".
	(define_insn "<avx512>_permvar<mode><mask_name>"): New.
	(define_insn "<avx2_avx512>_ashrv<VI48_AVX512F_AVX512VL:mode><mask_name>"):
	Rename from "<avx2_avx512f>_ashrv<mode><mask_name>".
	(define_insn "<avx2_avx512>_ashrv<VI2_AVX512VL:mode><mask_name>"):
	Ditto.
	(define_insn "<avx2_avx512>_<shift_insn>v<VI48_AVX512F:mode><mask_name>"):
	Rename from "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>".
	(define_insn "<avx2_avx512>_<shift_insn>v<VI2_AVX512VL:mode><mask_name>"):
	Rename from "<avx2_avx512bw>_<shift_insn>v<mode><mask_name>".


Co-Authored-By: Andrey Turetskiy <andrey.turetskiy@intel.com>
Co-Authored-By: Anna Tikhonova <anna.tikhonova@intel.com>
Co-Authored-By: Ilya Tocar <ilya.tocar@intel.com>
Co-Authored-By: Ilya Verbin <ilya.verbin@intel.com>
Co-Authored-By: Kirill Yukhin <kirill.yukhin@intel.com>
Co-Authored-By: Maxim Kuznetsov <maxim.kuznetsov@intel.com>
Co-Authored-By: Michael Zolotukhin <michael.v.zolotukhin@intel.com>

From-SVN: r215148
2014-09-11 06:42:29 +00:00