Commit Graph

145964 Commits

Author SHA1 Message Date
Jonathan Wakely
068b220e52 Add dg-require-atomic-builtins to test
PR libstdc++/71081
	* testsuite/experimental/memory_resource/1.cc: Require atomics.

From-SVN: r236177
2016-05-12 15:08:45 +01:00
Richard Biener
1ef33ef304 re PR tree-optimization/71059 (gcc ICE at -O3 on valid code on x86_64-linux-gnu in "vn_nary_op_insert_into")
2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71059
	* tree-ssa-pre.c (phi_translate_1): Fully fold translated
	nary before looking up or entering the expression into the VN
	hashes.
	* tree-ssa-sccvn.c (vn_nary_build_or_lookup): Fix comment typo.
	Make sure to re-use NARYs without result as inserted by
	phi-translation.

	* gcc.dg/torture/pr71059.c: New testcase.

From-SVN: r236175
2016-05-12 13:46:26 +00:00
Richard Biener
763baff6f5 re PR middle-end/71062 (r235622 and restrict pointers)
2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71062
	* tree-ssa-alias.h (struct pt_solution): Add vars_contains_restrict
	field.
	* tree-ssa-structalias.c (set_uids_in_ptset): Set vars_contains_restrict
	if the var is a restrict tag.
	* tree-ssa-alias.c (ptrs_compare_unequal): If vars_contains_restrict
	do not disambiguate pointers against it.
	(dump_points_to_solution): Re-structure and adjust for new
	vars_contains_restrict flag.
	* gimple-pretty-print.c (pp_points_to_solution): Likewise.

	* gcc.dg/torture/pr71062.c: New testcase.

From-SVN: r236174
2016-05-12 13:05:13 +00:00
Martin Liska
cf48d8c4dc Document ASAN_OPTIONS="halt_on_error" env variable.
* doc/invoke.texi: Explain connection between -fsanitize-recover=address
	and ASAN_OPTIONS="halt_on_error=1".

From-SVN: r236172
2016-05-12 12:36:16 +00:00
Ilya Enkovich
c4ec12434d re PR tree-optimization/71006 (ICE: verify_gimple failed (error: type mismatch in conditional expression) w/ -O1 -ftree-loop-vectorize)
gcc/

	PR tree-optimization/71006
	* tree-vect-loop.c (vect_determine_vectorization_factor): Don't
	consider COND_EXPR as a mask producer.

gcc/testsuite/

	PR tree-optimization/71006
	* gcc.dg/pr71006.c: New test.

From-SVN: r236171
2016-05-12 11:27:49 +00:00
Marek Polacek
a5fbf76d42 re PR driver/71063 (ICE: Segmentation fault with --help="^")
PR driver/71063
	* opts.c (common_handle_option): Detect missing argument for --help^.

	* gcc.dg/opts-7.c: New test.

From-SVN: r236170
2016-05-12 10:59:11 +00:00
Kyrylo Tkachov
5acc47a40d [ARM] PR target/70830: Avoid POP-{reglist}^ when returning from interrupt handlers
PR target/70830
	* config/arm/arm.c (arm_output_multireg_pop): Avoid POP instruction
	when popping the PC and within an interrupt handler routine.
	Add missing tab to output of "ldmfd".
	(output_return_instruction): Output LDMFD with SP update rather
	than POP when returning from interrupt handler.

	* gcc.target/arm/interrupt-1.c: Change dg-compile to dg-assemble.
	Add -save-temps to dg-options.
	Scan for ldmfd rather than pop instruction.
	* gcc.target/arm/interrupt-2.c: Likewise.
	* gcc.target/arm/pr70830.c: New test.

From-SVN: r236169
2016-05-12 09:56:46 +00:00
Jakub Jelinek
3cd638421e i386.md (isa): Add x64_avx512dq, enable if TARGET_64BIT && TARGET_AVX512DQ.
* config/i386/i386.md (isa): Add x64_avx512dq, enable if
	TARGET_64BIT && TARGET_AVX512DQ.
	* config/i386/sse.md (*vec_extract<mode>): Add avx512bw alternatives.
	(*vec_extract<PEXTR_MODE12:mode>_zext): Add avx512bw alternative.
	(*vec_extract<ssevecmodelower>_0, *vec_extractv4si_0_zext,
	*vec_extractv2di_0_sse): Use v constraint instead of x constraint.
	(*vec_extractv4si): Add avx512dq and avx512bw alternatives.
	(*vec_extractv4si_zext): Add avx512dq alternative.
	(*vec_extractv2di_1): Add x64_avx512dq and avx512bw alternatives,
	use v instead of x constraint in other alternatives where possible.

	* gcc.target/i386/avx512bw-vpextr-1.c: New test.
	* gcc.target/i386/avx512dq-vpextr-1.c: New test.

From-SVN: r236167
2016-05-12 10:35:20 +02:00
Jakub Jelinek
0247b635c7 sse.md (sse2_loadld): Use v instead of x constraint in alternatives 0,1,4.
* config/i386/sse.md (sse2_loadld): Use v instead of x
	constraint in alternatives 0,1,4.

From-SVN: r236166
2016-05-12 10:34:38 +02:00
Jakub Jelinek
c05d08f6fa sse.md (pinsr_evex_isa): New mode attr.
* config/i386/sse.md (pinsr_evex_isa): New mode attr.
	(<sse2p4_1>_pinsr<ssemodesuffix>): Add 2 alternatives with
	v constraints instead of x and <pinsr_evex_isa> isa attribute.

	* gcc.target/i386/avx512bw-vpinsr-1.c: New test.
	* gcc.target/i386/avx512dq-vpinsr-1.c: New test.
	* gcc.target/i386/avx512vl-vpinsr-1.c: New test.

From-SVN: r236165
2016-05-12 10:34:11 +02:00
Jakub Jelinek
bc27ffae1b re PR target/71019 (AVX512BW instructions emitted even without AVX512BW)
PR target/71019
	* config/i386/sse.md (<sse2_avx2>_packssdw<mask_name>,
	<sse4_1_avx2>_packusdw<mask_name>): Make sure EVEX encoded insn
	is not emitted unless TARGET_AVX512BW.
	(<sse2_avx2>_packuswb<mask_name>, <sse2_avx2>_packsswb<mask_name>):
	Likewise.  For TARGET_AVX512BW, use "=v" constraint instead of "=x"
	for the result operand.

	* gcc.target/i386/avx512vl-pack-1.c: New test.
	* gcc.target/i386/avx512vl-pack-2.c: New test.
	* gcc.target/i386/avx512bw-pack-2.c: New test.

From-SVN: r236163
2016-05-12 10:33:14 +02:00
Jakub Jelinek
515d7412ea sse.md (*vec_setv4sf_sse4_1, [...]): Use v constraint instead of x in avx alternatives.
* config/i386/sse.md (*vec_setv4sf_sse4_1, sse4_1_insertps): Use v
	constraint instead of x in avx alternatives.  Use maybe_evex instead
	of vex prefix.

	* gcc.target/i386/avx512vl-vinsertps-1.c: New test.

From-SVN: r236162
2016-05-12 10:32:31 +02:00
Jakub Jelinek
40bd4bf95e constraints.md (Yv): New constraint.
* config/i386/constraints.md (Yv): New constraint.
	* config/i386/i386.h (VALID_AVX512VL_128_REG_MODE): Allow
	TFmode and V1TImode in xmm16+ registers for TARGET_AVX512VL.
	* config/i386/i386.md (avx512fvecmode): New mode attr.
	(*pushtf): Use v constraint instead of x.
	(*movtf_internal): Likewise.  For TARGET_AVX512VL and
	xmm16+ registers, use vmovdqu64 or vmovdqa64 instructions.
	(*absneg<mode>2): Use Yv constraint instead of x constraint.
	(*absnegtf2_sse): Likewise.
	(copysign<mode>3_const, copysign<mode>3_var): Likewise.
	* config/i386/sse.md (*andnot<mode>3): Add avx512vl and
	avx512f alternatives.
	(*andnottf3, *<code><mode>3, *<code>tf3): Likewise.

	* gcc.target/i386/avx512dq-abs-copysign-1.c: New test.
	* gcc.target/i386/avx512vl-abs-copysign-1.c: New test.
	* gcc.target/i386/avx512vl-abs-copysign-2.c: New test.

From-SVN: r236161
2016-05-12 10:30:25 +02:00
Richard Biener
eb09cdcb1a re PR tree-optimization/71060 (Compiler reports "loop vectorized" but actually it was not)
2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71060
	* tree-data-ref.c (initialize_data_dependence_relation): Do not
	require exact match of DR_BASE_OBJECT but only matching address and
	type.

From-SVN: r236159
2016-05-12 07:29:33 +00:00
Richard Biener
44ab146a72 re PR tree-optimization/70986 (ICE on valid code at -O3 on x86_64-linux-gnu in combine_blocks, at tree-if-conv.c:2219)
2016-05-12  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/70986
	* cfganal.c: Include cfgloop.h.
	(dfs_find_deadend): Prefer to take edges exiting loops.

	* gcc.dg/torture/pr70986-1.c: New testcase.
	* gcc.dg/torture/pr70986-2.c: Likewise.
	* gcc.dg/torture/pr70986-3.c: Likewise.

From-SVN: r236158
2016-05-12 07:18:58 +00:00
GCC Administrator
b5aa474d1e Daily bump.
From-SVN: r236152
2016-05-12 00:16:18 +00:00
Bill Schmidt
20947198f9 pr70963.c: Require at least power8 at both compile and run time.
2016-05-11  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* gcc.target/powerpc/pr70963.c: Require at least power8 at both
	compile and run time.

From-SVN: r236146
2016-05-11 21:38:40 +00:00
Mikhail Maltsev
d6e83a8dec PR43651: add warning for duplicate qualifier
gcc/c/

	PR c/43651
	* c-decl.c (declspecs_add_qual): Warn when -Wduplicate-decl-specifier
	is enabled.
	* c-errors.c (pedwarn_c90): Return true if warned.
	* c-tree.h (pedwarn_c90): Change return type to bool.
	(enum c_declspec_word): Add new enumerator cdw_atomic.

gcc/

	PR c/43651
	* doc/invoke.texi (Wduplicate-decl-specifier): Document new option.

gcc/testsuite/

	PR c/43651
	* gcc.dg/Wduplicate-decl-specifier-c11.c: New test.
	* gcc.dg/Wduplicate-decl-specifier.c: Likewise.

gcc/c-family/

	PR c/43651
	* c.opt (Wduplicate-decl-specifier): New option.

From-SVN: r236142
2016-05-11 20:23:37 +00:00
Uros Bizjak
51e67ea376 sse-13.c: Add dg-add-options bind_pic_locally directive.
* gcc.target/i386/sse-13.c: Add dg-add-options bind_pic_locally
	directive.
	* gcc.target/i386/pr66746.c: Ditto.

From-SVN: r236140
2016-05-11 21:16:58 +02:00
Uros Bizjak
a730a6d925 i386.c (legitimize_pic_address): Use copy_to_suggested_reg instead of gen_movsi.
* config/i386/i386.c (legitimize_pic_address): Use
	copy_to_suggested_reg instead of gen_movsi.

From-SVN: r236138
2016-05-11 21:11:00 +02:00
Michael Meissner
3fd2b0075e predicates.md (quad_memory_operand): Move most of the code into quad_address_p and call it to share code with...
[gcc]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/predicates.md (quad_memory_operand): Move most of
	the code into quad_address_p and call it to share code with
	vsx_quad_dform_memory_operand.
	(vsx_quad_dform_memory_operand): New predicate for ISA 3.0 vector
	d-form support.
	* config/rs6000/rs6000.opt (-mlra): Switch to being an option mask
	bit instead of being a separate word.  Split -mpower9-dform into
	two switches, -mpower9-dform-scalar and -mpower9-dform-vector.
	* config/rs6000/rs6000.c (RELOAD_REG_QUAD_OFFSET): New addr_mask
	for the register class supporting 128-bit quad word memory
	offsets.
	(mode_supports_vsx_dform_quad): Helper function to return if the
	register class uses quad word memory offsets.
	(rs6000_debug_addr_mask): Add support for quad word memory
	offsets.
	(rs6000_debug_reg_global): Always print if we are using LRA or
	not.
	(rs6000_setup_reg_addr_masks): If ISA 3.0 vector d-form
	instructions are enabled, set up the appropriate addr_masks for
	128-bit types.
	(rs6000_init_hard_regno_mode_ok): wb constraint is now based on
	-mpower9-dform-scalar, instead of -mpower9-dform.
	(rs6000_option_override_internal): Split -mpower9-dform into two
	switches, -mpower9-dform-scalar and -mpower9-dform-vector.  The
	-mpower9-dform switch sets or clears both.  If we are not using
	the LRA register allocator, do not enable -mpower9-dform-vector by
	default.  If we are using LRA, enable -mpower9-dform-vector and
	-mvsx-timode if it is appropriate.  Issue a warning if either
	-mpower9-dform-vector or -mvsx-timode are explicitly used without
	enabling LRA.
	(quad_address_offset_p): New helper function to return if the
	offset is legal for quad word memory instructions.
	(quad_address_p): New function to determin if GPR or vector
	register quad word memory addresses are legal.
	(mem_operand_gpr): Validate quad word address offsets.
	(reg_offset_addressing_ok_p): Add support for ISA 3.0 vector
	d-form (register + offset) instructions.
	(offsettable_ok_by_alignment): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(legitimate_lo_sum_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_legitimize_reload_address): Add more debug statements for
	-mdebug=addr.
	(rs6000_legitimate_address_p): Add support for ISA 3.0 vector
	d-form instructions.
	(rs6000_secondary_reload_memory): Add support for ISA 3.0 vector
	d-form instructions.  Distinguish different cases in debug
	output.	(rs6000_secondary_reload_inner): Add support for ISA 3.0 vector
	d-form instructions.
	(rs6000_preferred_reload_class): Likewise.
	(rs6000_output_move_128bit): Add support for ISA 3.0 d-form
	instructions.  If ISA 3.0 is available, generate lxvx/stxvx instead
	of the ISA 2.06 indexed memory instructions.
	(rs6000_emit_prologue): If we have ISA 3.0 d-form instructions,
	use them to save/restore the saved vector registers instead of
	using Altivec instructions.
	(rs6000_emit_epilogue): Likewise.
	(rs6000_lra_p): Use TARGET_LRA instead of the old option word.
	(rs6000_opt_masks): Split -mpower9-dform into
	-mpower9-dform-scalar and -mpower9-dform-vector.
	(rs6000_print_options_internal): Print -mno-<switch> if <switch>
	was not selected.
	* config/rs6000/vsx.md (p9_vecload_<mode>): Delete hack to emit
	ISA 3.0 vector indexed memory instructions, and fold the code into
	the normal mov<mode> patterns.
	(p9_vecstore_<mode>): Likewise.
	(vsx_mov<mode>): Add support for ISA 3.0 vector d-form
	instructions.
	(vsx_movti_64bit): Likewise.
	(vsx_movti_32bit): Likewise.
	* config/rs6000/constraints.md (wO constraint): New constraint for
	ISA 3.0 vector d-form support.
	* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Use
	-mpower9-dform-scalar instead of -mpower9-dform.  Add note not to
	include -mpower9-dform-vector until we switch over to LRA.
	(POWERPC_MASKS): Add -mlra. Split -mpower9-dform into two. 
	switches, -mpower9-dform-scalar and -mpower9-dform-vector.
	* config/rs6000/rs6000-protos.h (quad_address_p): Add declaration.
	* doc/invoke.texi (RS/6000 and PowerPC Options): Add documentation
	for -mpower9-dform and -mlra.
	* doc/md.texi (wO constraint): Document wO constraint.

[gcc/testsuite]
2016-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/dform-3.c: New test for ISA 3.0 vector d-form
	support.
	* gcc.target/powerpc/dform-1.c: Add -mlra option to silence
	warning when using -mvsx-timode.
	* gcc.target/powerpc/p8vector-int128-1.c: Likewise.
	* gcc.target/powerpc/dform-2.c: Likewise.
	* gcc.target/powerpc/pr68805.c: Likewise.

From-SVN: r236133
2016-05-11 18:38:10 +00:00
Alexander Monakov
d8aecc553d genautomata.c cleanup
* genattr.c (main): Change 'rtx' to 'rtx_insn *' in prototypes of
	'insn_latency', 'maximal_insn_latency', 'min_insn_conflict_delay'.
	* genautomata.c (output_internal_insn_code_evaluation): Simplify.
	Move handling of non-insn arguments inline into the sole user:
	(output_trans_func): ...here.
	(output_min_insn_conflict_delay_func): Change 'rtx' to 'rtx_insn *'
	in emitted function prototype.
	(output_internal_insn_latency_func): Ditto.  Simplify.
	(output_internal_maximal_insn_latency_func): Ditto.  Delete
	always-unused argument.
	(output_insn_latency_func): Ditto.
	(output_maximal_insn_latency_func): Ditto.

From-SVN: r236132
2016-05-11 21:13:11 +03:00
Marek Polacek
2c74f63ff5 attr-opt-1.c: Move to c-c++-common/.
* gcc.dg/attr-opt-1.c: Move to c-c++-common/.
	* gcc.dg/pr18079-2.c: Remove file.

From-SVN: r236130
2016-05-11 17:09:43 +00:00
Marek Polacek
5c3a10fbc1 re PR c++/71024 (Missing warning for contradictory attributes)
PR c++/71024
	* c-common.c (diagnose_mismatched_attributes): New function.
	* c-common.h (diagnose_mismatched_attributes): Declare.

	* c-decl.c (diagnose_mismatched_decls): Factor out code to
	diagnose_mismatched_attributes and call it.

	* decl.c (duplicate_decls): Call diagnose_mismatched_decls.

	* c-c++-common/attributes-3.c: New test.

From-SVN: r236129
2016-05-11 17:07:37 +00:00
Nathan Sidwell
7cfb065b0e pr68671.c: Xfail on PTX -- assembler crash.
* gcc.dg/pr68671.c: Xfail on PTX -- assembler crash.
	* gcc.c-torture/execute/pr68185.c: Likewise.
	* gcc.dg/ipa/pr70306.c: Requires global constructors.
	* gcc.dg/pr69634.c: Requires scheduling.
	* gcc.dg/torture/pr66178.c: Require label values.
	* gcc.dg/setjmp-6.c: Require indirect jumps.

From-SVN: r236125
2016-05-11 15:50:20 +00:00
Richard Biener
f35ea97de8 re PR tree-optimization/71055 (FAIL: gcc.dg/torture/pr53663-1.c -Os execution test)
2016-05-11  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71055
	* tree-ssa-sccvn.c (vn_reference_lookup_3): When native-interpreting
	sth with precision not equal to access size verify we don't chop
	off bits.

	* gcc.dg/torture/pr71055.c: New testcase.

From-SVN: r236122
2016-05-11 14:04:32 +00:00
Richard Biener
dff70323a3 re PR debug/71057 (ICE in schedule_generic_params_dies_gen, at dwarf2out.c:24142)
2016-05-11  Richard Biener  <rguenther@suse.de>

	PR debug/71057
	* dwarf2out.c (retry_incomplete_types): Set early_dwarf.
	(dwarf2out_finish): Move retry_incomplete_types call ...
	(dwarf2out_early_finish): ... here.

	* g++.dg/debug/pr71057.C: New testcase.

From-SVN: r236121
2016-05-11 13:59:34 +00:00
Jakub Jelinek
56a3d28ba3 re PR fortran/70855 (ICE with -fopenmp in gfc_trans_omp_workshare(): Bad statement code)
PR fortran/70855
	* frontend-passes.c (inline_matmul_assign): Disable in !$omp workshare.

	* gfortran.dg/gomp/pr70855.f90: New test.

From-SVN: r236119
2016-05-11 15:16:48 +02:00
Jonathan Wakely
3d73ae6ea9 libstdc++/71049 fix --disable-libstdcxx-dual-abi bootstrap
PR libstdc++/71049
	* src/c++11/cow-stdexcept.cc [!_GLIBCXX_USE_DUAL_ABI]: Don't define
	exception constructors with __sso_string parameters.

From-SVN: r236118
2016-05-11 13:39:28 +01:00
Richard Biener
ebc1b29edb re PR middle-end/71002 (-fstrict-aliasing breaks Boost's short string optimization implementation)
2016-05-11  Richard Biener  <rguenther@suse.de>

	PR middle-end/71002
	* alias.c (reference_alias_ptr_type): Preserve alias-set zero
	if the langhook insists on it.
	* fold-const.c (make_bit_field_ref): Add arg for the original
	reference and preserve its alias-set.
	(decode_field_reference): Take exp by reference and adjust it
	to the original memory reference.
	(optimize_bit_field_compare): Adjust callers.
	(fold_truth_andor_1): Likewise.
	* gimplify.c (gimplify_expr): Adjust in-SSA form test.

	* g++.dg/torture/pr71002.C: New testcase.

From-SVN: r236117
2016-05-11 10:24:11 +00:00
Ilya Enkovich
98ccd1d7ab re PR middle-end/70807 (fwprop pass ICE with incoming CDI_DOMINATORS)
gcc/

	PR middle-end/70807
	* cfgrtl.h (delete_insn_and_edges): Now return bool.
	* cfgrtl.c (delete_insn_and_edges): Likewise.
	* config/i386/i386.c (convert_scalars_to_vector): Remove
	redundant code.
	* cse.c (cse_insn): Compute cse_cfg_altered.
	(delete_trivially_dead_insns): Likewise.
	(cse_cc_succs): Likewise.
	(rest_of_handle_cse): Free dominance info if required.
	(rest_of_handle_cse2): Likewise.
	(rest_of_handle_cse_after_global_opts): Likewise.

gcc/testsuite/

	PR middle-end/70807
	* gcc.dg/pr70807.c: New test.

From-SVN: r236114
2016-05-11 09:33:13 +00:00
Martin Sebor
ed29e24b8b PR c++/38611 - missing -Wattributes on a typedef with attribute aligned
From-SVN: r236112
2016-05-10 21:04:03 -06:00
Alan Modra
c8acbe37ae [RS6000] complex long double ABI_V4 fix
Revision 235794 regressed compat/scalar-by-value-6 for powerpc-linux
-m32 due to accidentally changing the ABI.  By another historical
accident, complex long double is stupidly passed in gprs for -m32.

	* config/rs6000/rs6000.c (is_complex_IBM_long_double,
	abi_v4_pass_in_fpr): New functions.
	(rs6000_function_arg_boundary): Exclude complex IBM long double
	from 64-bit alignment when ABI_V4.
	(rs6000_function_arg, rs6000_function_arg_advance_1,
	rs6000_gimplify_va_arg): Use abi_v4_pass_in_fpr.

From-SVN: r236111
2016-05-11 11:39:38 +09:30
GCC Administrator
36bc016315 Daily bump.
From-SVN: r236110
2016-05-11 00:16:19 +00:00
Segher Boessenkool
ac2a4c0df8 cfgcleanup: Handle a branch with just a return in both arms (PR71028)
If we have a conditional jump that has only a return in both the branch
path and the fallthrough path, and the return on the branch path can not
be made a conditional return, we will try to make a conditional return
from the fallthrough path, and that does not work because we then try
to redirect the (new) jump in the fallthrough block to the original
dest in the branch path, which is the exit block.

For the testcase on ARM we end up in this situation because before the
jump2 pass there are some other insns in the return blocks as well, but
the same insns in both, so those are moved above the conditional jump.
Only later (in the ce3 pass) are the conditional jump and two returns
melded into one return, so we need to handle this strange case here.


	PR rtl-optimization/71028
	* cfgcleanup.c (try_optimize_cfg): Do not flip a conditional
	jump with just a return in the fallthrough block if the branch
	block contains just a returns as well.

From-SVN: r236106
2016-05-11 01:31:27 +02:00
Marc Glisse
e39dab2c21 Simple bitop reassoc in match.pd
2016-05-10  Marc Glisse  <marc.glisse@inria.fr>

gcc/
	* fold-const.c (fold_binary_loc) [(X ^ Y) & Y]: Remove and merge with...
	* match.pd ((X & Y) ^ Y): ... this.
	((X & Y) & Y, (X | Y) | Y, (X ^ Y) ^ Y, (X & Y) & (X & Z), (X | Y)
	| (X | Z), (X ^ Y) ^ (X ^ Z)): New transformations.

gcc/testsuite/
	* gcc.dg/tree-ssa/bit-assoc.c: New testcase.
	* gcc.dg/tree-ssa/pr69270.c: Adjust.
	* gcc.dg/tree-ssa/vrp59.c: Disable forwprop.

From-SVN: r236103
2016-05-10 19:52:20 +00:00
David Malcolm
601070fce9 Simplify read-md.c and read-rtl.c using require_char_ws
read-md.c and read-rtl.c repeatedly use this pattern:

    c = read_skip_spaces ();
    if (c != ')')
      fatal_expected_char (')', c);

Simplify them by introduce a helper function to do this.

gcc/ChangeLog:
	* read-md.c (require_char_ws): New function.
	(read_string): Simplify using require_char_ws.
	(handle_constants): Likewise.
	(handle_enum): Likewise.
	(handle_file): Likewise.
	* read-md.h (require_char_ws): New declaration.
	* read-rtl.c (read_conditions): Simplify using require_char_ws.
	(read_mapping): Likewise.
	(read_rtx_code): Likewise.
	(read_nested_rtx): Likewise.

From-SVN: r236101
2016-05-10 18:28:10 +00:00
James Norris
3126957087 sysv4.h (CRTOFFLOADBEGIN): Define.
* config/rs6000/sysv4.h (CRTOFFLOADBEGIN): Define. Add crtoffloadbegin.o
	if offloading is enabled and -fopenacc or -fopenmp is specified.
	(CRTOFFLOADEND): Likewise.
	(STARTFILE_LINUX_SPEC): Add CRTOFFLOADBEGIN.
	(ENDFILE_LINUX_SPEC): Add CRTOFFLOADEND.

From-SVN: r236098
2016-05-10 18:05:02 +00:00
Uros Bizjak
6ca7558bfe i386.c (legitimize_pic_address): Merge 64-bit and 32-bit gotoff_operand code paths.
* config/i386/i386.c (legitimize_pic_address): Merge 64-bit and 32-bit
	gotoff_operand code paths.  Use copy_to_suggested_regs and
	expand_simple_binop where appropriate.  Cleanup.

From-SVN: r236096
2016-05-10 19:17:20 +02:00
Matthias Klose
61431953d7 configure.ac: Move AC_USE_SYSTEM_EXTENSIONS behind AM_ENABLE_MULTILIB.
2016-05-10  Matthias Klose  <doko@ubuntu.com>

        * configure.ac: Move AC_USE_SYSTEM_EXTENSIONS behind AM_ENABLE_MULTILIB.
        * configure: Regenerate.

From-SVN: r236093
2016-05-10 16:44:19 +00:00
Ilya Enkovich
d067e238cb re PR target/70799 (STV pass does not convert DImode shifts)
gcc/

	PR target/70799
	* config/i386/i386.c (dimode_scalar_to_vector_candidate_p): Allow
	integer constants.
	(dimode_scalar_chain::vector_const_cost): New.
	(dimode_scalar_chain::compute_convert_gain): Handle constants.
	(dimode_scalar_chain::convert_op): Likewise.
	(dimode_scalar_chain::convert_insn): Likewise.

gcc/testsuite/

	PR target/70799
	* gcc.target/i386/pr70799-1.c: New test.

From-SVN: r236090
2016-05-10 16:08:42 +00:00
Ilya Enkovich
1e3af2a4e0 re PR middle-end/70877 ([MPX] ICE in in convert_move)
gcc/

	PR middle-end/70877
	* tree-chkp.c (chkp_add_bounds_to_call_stmt): Handle
	calls with type casted fndecl.

gcc/testsuite/

	PR middle-end/70877
	* gcc.target/i386/pr70877.c: New test.

From-SVN: r236088
2016-05-10 16:06:36 +00:00
Pierre-Marie de Rodat
cd36c83e9b DWARF: fix stack usage assessment for DW_OP_neg
When the DWARF back-end generates DW_OP_neg operations in DWARF
procedures, we get an ICE because of inconsistent stack usage
computation for the embedding expression. This is because
resolve_args_picking_1 thinks DW_OP_neg is a binary operation (pops 2
stack slots, pushes 1) whereas it really is an unary one (one pop, one
push).

This change fixes resolve_args_picking_1 and adds a regression testcase
(which crashes with the current trunk).  Bootstrapped and regtested
without regression on x86_64-linux.

gcc/

	* dwarf2out.c (resolve_args_picking_1): Consider DW_OP_neg as an
	unary operation, not a binary one.

gcc/testsuite/

	* gnat.dg/debug6.adb, gnat.dg/debug6_pkg.ads: New testcase.

From-SVN: r236087
2016-05-10 15:57:37 +00:00
Ilya Enkovich
afc610dba1 re PR tree-optimization/70876 (ICE in chkp_find_bounds: Unexpected tree code with_size_expr)
gcc/

	PR tree-optimization/70786
	* tree-chkp.c (chkp_find_bounds_1): Support WITH_SIZE_EXPR.
	* gcc/calls.c (initialize_argument_information): Bind bounds
	with corresponding args passed by reference.

gcc/testsuite/

	PR tree-optimization/70786
	* gcc.target/i386/pr70876.c: New test.

From-SVN: r236086
2016-05-10 15:56:27 +00:00
Jonathan Wakely
7f99d40a99 Test begin and end functions for directory iterators
* include/experimental/bits/fs_dir.h (begin, end): Add noexcept.
	* testsuite/experimental/filesystem/iterators/directory_iterator.cc:
	Test begin and end functions.
	* testsuite/experimental/filesystem/iterators/
	recursive_directory_iterator.cc: Likewise.

From-SVN: r236085
2016-05-10 16:39:20 +01:00
Jonathan Wakely
6fe673ad0f libstdc++/71038 fix error checks in filesystem::copy_file
PR libstdc++/71038
	* src/filesystem/ops.cc (do_copy_file): Fix backwards conditions.
	* testsuite/experimental/filesystem/operations/copy_file.cc: New test.

From-SVN: r236084
2016-05-10 16:39:14 +01:00
Jakub Jelinek
4b59d19ffd re PR target/70927 ([6 only] avx512dq instructions emitted even with -mavx512vl -mno-avx512dq)
PR target/70927
	* config/i386/sse.md (<sse>_andnot<mode>3<mask_name>),
	*<code><mode>3<mask_name>): For !TARGET_AVX512DQ and EVEX encoding,
	use vp*[dq] instead of v*p[sd] instructions and adjust mode attribute
	accordingly.

	* gcc.target/i386/avx512vl-logic-1.c: New test.
	* gcc.target/i386/avx512vl-logic-2.c: New test.
	* gcc.target/i386/avx512dq-logic-2.c: New test.

From-SVN: r236083
2016-05-10 16:30:02 +02:00
Bill Schmidt
9b5ee426fc re PR target/70963 (vec_cts/vec_ctf intrinsics produce wrong results for 64-bit floating point)
[gcc]

2016-05-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/70963
	* config/rs6000/vsx.md (vsx_xvcvdpsxds_scale): Generate correct
	code for a zero scale factor.
	(vsx_xvcvdpuxds_scale): Likewise.

[gcc/testsuite]

2016-05-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	PR target/70963
	* gcc.target/powerpc/pr70963.c: New.

From-SVN: r236082
2016-05-10 14:27:12 +00:00
David Malcolm
f3352cabb8 Add debugging ruler to diagnostic-show-locus.c
When debugging diagnostic-show-locus.c, it's invaluable to have a
"ruler" showing column numbers.

This patch adds in support via a new "show_ruler_p" flag within
the diagnostic_context.  There's no direct way for end-users to enable
this, but plugins can enable it by setting the flag, so the
plugin that tests the diagnostic subsystem uses this to verify that
the ruler is correctly printed.

gcc/ChangeLog:
	* diagnostic-show-locus.c (layout::layout): Call show_ruler
	if show_ruler_p was set on the context.
	(layout::show_ruler): New method.
	* diagnostic.h (struct diagnostic_context): Add field
	"show_ruler_p".

gcc/testsuite/ChangeLog:
	* gcc.dg/plugin/diagnostic-test-show-locus-bw.c
	(test_very_wide_line): Add ruler to expected output.
	* gcc.dg/plugin/diagnostic-test-show-locus-color.c
	(test_very_wide_line): Likewise.
	* gcc.dg/plugin/diagnostic_plugin_test_show_locus.c
	(test_show_locus): Within the handling of "test_very_wide_line",
	enable show_ruler_p on the diagnostic context.

From-SVN: r236080
2016-05-10 13:28:41 +00:00
Richard Biener
4a3255dd43 re PR tree-optimization/71039 (ICE: verify_ssa failed (error: definition in block 4 does not dominate use in block 5) w/ -O1 and above)
2016-05-10  Richard Biener  <rguenther@suse.de>

	PR tree-optimization/71039
	* tree-ssa-phiprop.c: Include tree-ssa-loop.h.
	(chk_uses): New function.
	(propagate_with_phi): Verify we can safely replicate the lhs of an
	aggregate assignment on all incoming edges.

	* gcc.dg/torture/pr71039.c: New testcase.

From-SVN: r236079
2016-05-10 13:13:59 +00:00