* config/i386/mmx.md (mmxdoublemode): New mode attribute.
(mmx_uavg<mode>3): Macroize expaner from mmx_uavgv8qi3 and
mmx_uavgv4hi3 using MMXMODE12 mode iterator.
(uavg<mode>3_ceil): New expander.
* config/i386/sse.md (uavg<mode>3_ceil): Use ssedoublemode
mode iterator when creating CONST1_RTX.
(<sse2_avx2>_uavg<mode>3<mask_name>): Ditto.
(*<sse2_avx2>_uavg<mode>3<mask_name>): Use ssedoublemode
mode iterator for const1_operand predicate.
From-SVN: r274572
If a variable with an automatic attribute appears in an
equivalence statement the storage should be allocated on the
stack.
Note: most of this patch was provided by Jeff Law <law@redhat.com>.
From-SVN: r274565
I'm trying to add a define_subst use in the arm backend but am getting many build errors complaining about:
`set_attr_alternative' is unsupported by `define_subst'
Looking at the gensupport.c code it iterates over all define_insns and errors if any of them have set_attr_alternative.
The usecase I'm targetting doesn't involve patterns with set_attr_alternative, so I would like to make the define_subst handling
more robust to only error out if the define_subst is actually attempted on a set_attr_alternative.
This patch produces the error only if the set_attr_alternative attr matches the subst name.
This allows a build of the arm backend with a define_subst usage to succeed.
PR other/91255
* gensupport.c (has_subst_attribute): Error out on set_attr_alternative
only if subst_name matches curr_attr string.
From-SVN: r274564
2019-08-16 Richard Biener <rguenther@suse.de>
* tree-ssa-forwprop.c (simplify_builtin_call): Do not remove
stmt at gsi_p, instead replace it with a NOP removed later.
(pass_forwprop::execute): Fully propagate lattice, DCE stmts
that became dead because of that.
fortran/
* trans-intrinsic.c (gfc_conv_intrinsic_findloc): Initialize
forward_branch to avoid bogus uninitialized warning.
* gcc.dg/tree-ssa/forwprop-31.c: Adjust.
From-SVN: r274563
Testcases that require support for trampolines should be marked as
such; gcc.target/i386/pr85044.c was missing it. Fixed.
for gcc/testsuite/ChangeLog
* gcc.target/i386/pr85044.c: Require support for trampolines.
From-SVN: r274560
gcc.target/i386/asm-4.c uses amd64's natural PC-relative addressing
mode on a single platform, using the 32-bit absolute addressing mode
elsewhere. There's no point in giving up amd64's natural addressing
mode and insisting on the 32-bit one when we're targeting amd64, and
having to make explicit exceptions for systems where that's found not
to work for whatever reason. If we just use the best-suited way to
take the address of a function behind the compiler's back on each
target variant, we're less likely to hit unexpected failures.
for gcc/testsuite/ChangeLog
* gcc.target/i386/asm-4.c: Use amd64 natural addressing mode
on all __LP64__ targets.
From-SVN: r274559
Since alloca.h is not ISO C, most of our alloca-using tests seem to
rely on __builtin_alloca instead of including the header and calling
alloca. This patch extends this practice to some of the exceptions I
found in gcc.target, marking them as requiring a functional alloca
while at that.
for gcc/testsuite/ChangeLog
* gcc.target/arc/interrupt-6.c: Use __builtin_alloca, require
effective target support for alloca, drop include of alloca.h.
* gcc.target/i386/pr80969-3.c: Likewise.
* gcc.target/sparc/setjmp-1.c: Likewise.
* gcc.target/x86_64/abi/ms-sysv/gen.cc: Likewise.
* gcc.target/x86_64/abi/ms-sysv/ms-sysv.c: Likewise.
From-SVN: r274558
The regexp that checks that -lgcov is linked in when --coverage is
passed to the compiler driver requires the command line to match
'/collect2'. Some of our targets don't match that, but they match /ld
or ${target_alias}-ld depending on the testing scenario, so I'd like
to tweak the test to match those as well.
for gcc/testsuite/ChangeLog
* gcc.misc-tests/options.exp: Match /ld and -ld besides
/collect2.
From-SVN: r274557
Oops, I forgot to update the MAINTAINERS file a couple of months ago,
when the address there stopped working.
Honestly, I haven't really had much involvement with the frv, mn10300
or sh ports for almost 15 years, so I wouldn't mind if someone else
stepped up and took over, but until someone does, I don't mind
reviewing the occasional patch, so it's best if it can reach me ;-)
for ChangeLog
* MAINTAINERS: aoliva from @redhat.com to @gcc.gnu.org.
From-SVN: r274556
2019-08-15 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/91443
* frontend-passes.c (check_externals_expr): New function.
(check_externals_code): New function.
(gfc_check_externals): New function.
* gfortran.h (debug): Add prototypes for gfc_symbol * and
gfc_expr *.
(gfc_check_externals): Add prototype.
* interface.c (compare_actual_formal): Do not complain about
alternate returns if the formal argument is optional.
(gfc_procedure_use): Handle cases when an error has been issued
previously. Break long line.
* parse.c (gfc_parse_file): Call gfc_check_externals for all
external procedures.
* resolve.c (resolve_global_procedure): Remove checking of
argument list.
2019-08-15 Thomas Koenig <tkoenig@gcc.gnu.org>
PR fortran/91443
* gfortran.dg/argument_checking_19.f90: New test.
* gfortran.dg/altreturn_10.f90: Change dg-warning to dg-error.
* gfortran.dg/dec_union_11.f90: Add -std=legacy.
* gfortran.dg/hollerith8.f90: Likewise. Remove warning for
Hollerith constant.
* gfortran.dg/integer_exponentiation_2.f90: New subroutine gee_i8;
use it to avoid type mismatches.
* gfortran.dg/pr41011.f: Add -std=legacy.
* gfortran.dg/whole_file_1.f90: Change warnings to errors.
* gfortran.dg/whole_file_2.f90: Likewise.
From-SVN: r274551
My previous patch for 64372 was incomplete: it only stopped making the
non-throw argument into an rvalue, lvalue_kind still considered the ?:
expression to be an rvalue, leaving us worse than before.
PR c++/64372, DR 1560 - Gratuitous lvalue-to-rvalue conversion in ?:
* tree.c (lvalue_kind): Handle throw in one arm.
* typeck.c (rationalize_conditional_expr): Likewise.
(cp_build_modify_expr): Likewise.
From-SVN: r274550
processor_costs has costs of RTL expressions with pseudo registers and
and costs of hard register moves:
1. Costs of RTL expressions are used to generate the most efficient RTL
operations with pseudo registers.
2. Costs of hard register moves are used by register allocator to
decide how to allocate and move hard registers.
Since relative costs of pseudo register load and store versus pseudo
register moves in RTL expressions can be different from relative costs
of hard registers, we should separate costs of RTL expressions with
pseudo registers from costs of hard registers so that register allocator
and RTL expressions can be improved independently.
This patch moves costs of hard register moves to the new hard_register
field and duplicates costs of moves which are also used for costs of RTL
expressions.
PR target/90878
* config/i386/i386.c (inline_memory_move_cost): Use hard_register
for costs of hard register moves.
(ix86_register_move_cost): Likewise.
* config/i386/i386.h (processor_costs): Move costs of hard
register moves to hard_register. Add int_load, int_store,
xmm_move, ymm_move, zmm_move, sse_to_integer, integer_to_sse,
sse_load, sse_store, sse_unaligned_load and sse_unaligned_store
for costs of RTL expressions.
* config/i386/x86-tune-costs.h: Move costs of hard register
moves to hard_register. Duplicate int_load, int_store,
xmm_move, ymm_move, zmm_move, sse_to_integer, integer_to_sse,
sse_load, sse_store for costs of RTL expressions.
From-SVN: r274543
In C++17 a function can return a prvalue of a type that cannot be moved
or copied. The current implementation of std::is_invocable_r uses
std::is_convertible to test the conversion to R required by INVOKE<R>.
That fails for non-copyable prvalues, because std::is_convertible is
defined in terms of std::declval which uses std::add_rvalue_reference.
In C++17 conversion from R to R involves no copies and so is not the
same as conversion from R&& to R.
This commit changes std::is_invocable_r to check the conversion without
using std::is_convertible.
std::function also contains a similar check using std::is_convertible,
which can be fixed by simply reusing std::is_invocable_r (but because
std::is_invocable_r is not defined for C++11 it uses the underlying
std::__is_invocable_impl trait directly).
PR libstdc++/91456
* include/bits/std_function.h (__check_func_return_type): Remove.
(function::_Callable): Use std::__is_invocable_impl instead of
__check_func_return_type.
* include/std/type_traits (__is_invocable_impl): Add another defaulted
template parameter. Define a separate partial specialization for
INVOKE and INVOKE<void>. For INVOKE<R> replace is_convertible check
with a check that models delayed temporary materialization.
* testsuite/20_util/function/91456.cc: New test.
* testsuite/20_util/is_invocable/91456.cc: New test.
From-SVN: r274542
If a target does not support libbacktrace, it might still the include
for $(top_srcdir).
Regenerate the built files using automake-1.15.1
libsanitizer/
2019-08-15 Iain Sandoe <iain@sandoe.co.uk>
PR bootstrap/91455
* Makefile.in: Regenerated.
* aclocal.m4: Likewise.
* asan/Makefile.in: Likewise.
* configure: Likewise.
* interception/Makefile.in: Likewise.
* libbacktrace/Makefile.in: Likewise.
* lsan/Makefile.in: Likewise.
* sanitizer_common/Makefile.am: Include top_srcdir unconditionally.
* sanitizer_common/Makefile.in: Regenerated.
* tsan/Makefile.in: Likewise.
* ubsan/Makefile.in: Likewise.
From-SVN: r274538
2019-08-15 Jozef Lawrynowicz <jozef.l@mittosystems.com>
MSP430: Fix whitespace errors and incorrect indentation in
config/msp430/*.{c,h} files
* config/msp430/driver-msp430.c (msp430_select_cpu): Fix indentation.
(msp430_select_hwmult_lib): Likewise.
* config/msp430/msp430-devices.c (parse_devices_csv_1): Likewise.
(msp430_extract_mcu_data): Likewise.
(struct t_msp430_mcu_data): Likewise.
* config/msp430/msp430.c (struct machine_function): Remove whitespace
before left square bracket.
(msp430_option_override): Fix indentation.
(msp430_hard_regno_nregs_with_padding): Likewise.
(msp430_initial_elimination_offset): Likewise.
(msp430_special_register_convention_p): Remove whitespace before left
square bracket and after exclamation mark.
(msp430_evaluate_arg): Likewise.
(msp430_callee_copies): Fix indentation.
(msp430_gimplify_va_arg_expr): Likewise.
(msp430_function_arg_advance): Remove whitespace before left square
bracket.
(reg_ok_for_addr): Likewise.
(msp430_preserve_reg_p): Likewise.
(msp430_compute_frame_info): Likewise.
(msp430_asm_output_addr_const_extra): Add space between function name
and open parenthesis.
(has_section_name): Fix indentation.
(msp430_attr): Remove trailing whitespace.
(msp430_section_attr): Likewise.
(msp430_data_attr): Likewise.
(struct msp430_attribute_table): Fix comment and whitespace.
(msp430_start_function): Remove whitespace before left square bracket.
Add space between function name and open parenthesis.
(msp430_select_section): Remove trailing whitespace.
(msp430_section_type_flags): Remove trailing whitespace.
(msp430_unique_section): Remove space before closing parenthesis.
(msp430_output_aligned_decl_common): Change 8 spaces to a tab.
(msp430_builtins): Remove whitespace before left square bracket.
(msp430_init_builtins): Fix indentation.
(msp430_expand_prologue): Remove whitespace before left square bracket.
Remove space before closing parenthesis.
(msp430_expand_epilogue): Remove whitespace before left square bracket.
(msp430_split_movsi): Remove space before closing parenthesis.
(helper_function_name_mappings): Fix indentation.
(msp430_use_f5_series_hwmult): Fix whitespace.
(use_32bit_hwmult): Likewise.
(msp430_no_hwmult): Likewise.
(msp430_output_labelref): Remove whitespace before left square bracket.
(msp430_print_operand_raw): Likewise.
(msp430_print_operand_addr): Likewise.
(msp430_print_operand): Add two spaces after '.' in comment.
Fix trailing whitespace.
(msp430x_extendhisi): Fix indentation.
* config/msp430/msp430.h (TARGET_CPU_CPP_BUILTINS): Change 8 spaces to
tab.
(PC_REGNUM): Likewise.
(STACK_POINTER_REGNUM): Likewise.
(CC_REGNUM): Likewise.
From-SVN: r274536
2019-08-15 Richard Biener <rguenther@suse.de>
PR target/91454
* config/i386/i386-features.c (gen_gpr_to_xmm_move_src): New
helper.
(general_scalar_chain::make_vector_copies): Use it.
From-SVN: r274535
With Concepts, overloads of special member functions can differ in
constraints, and this paper clarifies how that affects class properties: if
a class has a more constrained trivial copy constructor and a less
constrained non-trivial copy constructor, it is still trivially copyable.
* tree.c (special_memfn_p): New.
* class.c (add_method): When overloading, hide ineligible special
member fns.
(check_methods): Set TYPE_HAS_COMPLEX_* here.
* decl.c (grok_special_member_properties): Not here.
* name-lookup.c (push_class_level_binding_1): Move overloaded
functions case down, accept FUNCTION_DECL as target_decl.
From-SVN: r274534
2019-08-15 Martin Liska <mliska@suse.cz>
* tree-ssa-dce.c (propagate_necessity): We can't reach now
operators with no arguments.
(eliminate_unnecessary_stmts): Likewise here.
From-SVN: r274529
2019-08-15 Richard Biener <rguenther@suse.de>
c-family/
* c-common.c (c_stddef_cpp_builtins): When the GIMPLE FE is
enabled, define __SIZETYPE__.
* gcc.dg/pr80170.c: Adjust to use __SIZETYPE__.
From-SVN: r274528
In this PR we were passing an ordinary non-built-in function to
targetm.vectorize.builtin_md_vectorized_function, which is only
supposed to handle BUILT_IN_MD.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
PR middle-end/91444
* tree-vect-stmts.c (vectorizable_call): Check that the function
is a BUILT_IN_MD function before passing it to
targetm.vectorize.builtin_md_vectorized_function.
From-SVN: r274524
This patch adds an exported function for testing whether a mode is
an SVE mode. The ACLE will make more use of it, but there's already
one place that can benefit.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h (aarch64_sve_mode_p): Declare.
* config/aarch64/aarch64.c (aarch64_sve_mode_p): New function.
(aarch64_select_early_remat_modes): Use it.
From-SVN: r274523
aarch64_simd_vector_alignment was only giving predicates 16-bit
alignment in VLA mode, not VLS mode. I think the problem is latent
because we can't yet create an ABI predicate type, but it seemed worth
fixing in a standalone patch rather than as part of the main ACLE series.
The ACLE patches have tests for this.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_simd_vector_alignment): Return
16 for SVE predicates even if they are fixed-length.
From-SVN: r274522
SVE defines an assembly alias:
MOV pa.B, pb/Z, pc.B -> AND pa.B. pb/Z, pc.B, pc.B
Our and<mode>3 pattern was instead using the functionally-equivalent:
AND pa.B. pb/Z, pb.B, pc.B
^^^^
This patch duplicates pc.B instead so that the alias can be seen
in disassembly.
I wondered about using the alias in the pattern instead, but using AND
explicitly seems to fit better with the pattern name and surrounding code.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (and<PRED_ALL:mode>3): Make the
operand order match the MOV /Z alias.
From-SVN: r274521
This patch makes us always pass an explicit vector pattern to
aarch64_output_sve_cnt_immediate, rather than assuming it's ALL.
The ACLE patches need to be able to pass in other values.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_output_sve_cnt_immediate): Take
the vector pattern as an aarch64_svpattern argument. Update the
overloaded caller accordingly.
(aarch64_output_sve_scalar_inc_dec): Update call accordingly.
(aarch64_output_sve_vector_inc_dec): Likewise.
From-SVN: r274520
aarch64_add_offset contains code to decompose all SVE VL-based constants
into native operations. The worst-case fallback is to load the number
of SVE elements into a register and use a general multiplication.
This patch improves that fallback by reusing expand_mult if
can_create_pseudo_p, rather than emitting a MULT pattern directly.
In order to increase the chances of being able to use a simple
add-and-shift, the patch also tries to compute VG * the lowest set
bit of the multiplier, rather than always using CNTD as the basis
for the multiplication path.
This is tested by the ACLE patches but is really an independent
improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64.c (aarch64_add_offset): In the fallback
multiplication case, try to compute VG * (lowest set bit) directly
rather than always basing the multiplication on VG. Use
expand_mult for the multiplication if we can.
gcc/testsuite/
* gcc.target/aarch64/sve/loop_add_4.c: Expect 10 INCWs and
INCDs rather than 8.
From-SVN: r274519
The scalar addition patterns allowed all the VL constants that
ADDVL and ADDPL allow, but wrote the instructions as INC or DEC
if possible (i.e. adding or subtracting a number of elements * [1, 16]
when the source and target registers the same). That works for the
cases that the autovectoriser needs, but there are a few constants
that INC and DEC can handle but ADDPL and ADDVL can't. E.g.:
inch x0, all, mul #9
is not a multiple of the number of bytes in an SVE register, and so
can't use ADDVL. It represents 36 times the number of bytes in an
SVE predicate, putting it outside the range of ADDPL.
This patch therefore adds separate alternatives for INC and DEC,
tied to a new Uai constraint. It also adds an explicit "scalar"
or "vector" to the function names, to avoid a clash with the
existing support for vector INC and DEC.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-protos.h
(aarch64_sve_scalar_inc_dec_immediate_p): Declare.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_addvl_addpl): Take a single rtx argument.
(aarch64_output_sve_scalar_inc_dec): Declare.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this.
* config/aarch64/aarch64.c (aarch64_sve_scalar_inc_dec_immediate_p)
(aarch64_output_sve_scalar_inc_dec): New functions.
(aarch64_output_sve_addvl_addpl): Remove the base and offset
arguments. Only handle true ADDVL and ADDPL instructions;
don't emit an INC or DEC.
(aarch64_sve_inc_dec_immediate_p): Rename to...
(aarch64_sve_vector_inc_dec_immediate_p): ...this.
(aarch64_output_sve_inc_dec_immediate): Rename to...
(aarch64_output_sve_vector_inc_dec): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/predicates.md (aarch64_sve_scalar_inc_dec_immediate)
(aarch64_sve_plus_immediate): New predicates.
(aarch64_pluslong_operand): Accept aarch64_sve_plus_immediate
rather than aarch64_sve_addvl_addpl_immediate.
(aarch64_sve_inc_dec_immediate): Rename to...
(aarch64_sve_vector_inc_dec_immediate): ...this. Update call to
aarch64_sve_vector_inc_dec_immediate_p.
(aarch64_sve_add_operand): Update accordingly.
* config/aarch64/constraints.md (Uai): New constraint.
(vsi): Update call to aarch64_sve_vector_inc_dec_immediate_p.
* config/aarch64/aarch64.md (add<GPI:mode>3): Don't force the second
operand into a register if it satisfies aarch64_sve_plus_immediate.
(*add<GPI:mode>3_aarch64, *add<GPI:mode>3_poly_1): Add an alternative
for Uai. Update calls to aarch64_output_sve_addvl_addpl.
* config/aarch64/aarch64-sve.md (add<mode>3): Call
aarch64_output_sve_vector_inc_dec instead of
aarch64_output_sve_inc_dec_immediate.
From-SVN: r274518
The current SVE REV patterns follow the AArch64 scheme, in which
UNSPEC_REV<NN> reverses elements within an <NN>-bit granule.
E.g. UNSPEC_REV64 on VNx8HI reverses the four 16-bit elements
within each 64-bit granule.
The native SVE scheme is the other way around: UNSPEC_REV64 is seen
as an operation on 64-bit elements, with REVB swapping bytes within
the elements, REVH swapping halfwords, and so on. This fits SVE more
naturally because the operation can then be predicated per <NN>-bit
granule/element.
Making the patterns use the Advanced SIMD scheme was more natural
when all we cared about were permutes, since we could then use
the source and target of the permute in their original modes.
However, the ACLE does need patterns that follow the native scheme,
treating them as operations on integer elements. This patch defines
the patterns that way instead and updates the existing uses to match.
This also brings in a couple of helper routines from the ACLE branch.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/iterators.md (UNSPEC_REVB, UNSPEC_REVH)
(UNSPEC_REVW): New constants.
(elem_bits): New mode attribute.
(SVE_INT_UNARY): New int iterator.
(optab): Handle UNSPEC_REV[BHW].
(sve_int_op): New int attribute.
(min_elem_bits): Handle VNx16QI and the predicate modes.
* config/aarch64/aarch64-sve.md (*aarch64_sve_rev64<mode>)
(*aarch64_sve_rev32<mode>, *aarch64_sve_rev16vnx16qi): Delete.
(@aarch64_pred_<SVE_INT_UNARY:optab><SVE_I:mode>): New pattern.
* config/aarch64/aarch64.c (aarch64_sve_data_mode): New function.
(aarch64_sve_int_mode, aarch64_sve_rev_unspec): Likewise.
(aarch64_split_sve_subreg_move): Use UNSPEC_REV[BHW] instead of
unspecs based on the total width of the reversed data.
(aarch64_evpc_rev_local): Likewise (for SVE only). Use a
reinterpret followed by a subreg on big-endian targets.
gcc/testsuite/
* gcc.target/aarch64/sve/revb_1.c: Restrict to little-endian targets.
Avoid including stdint.h.
* gcc.target/aarch64/sve/revh_1.c: Likewise.
* gcc.target/aarch64/sve/revw_1.c: Likewise.
* gcc.target/aarch64/sve/revb_2.c: New big-endian test.
* gcc.target/aarch64/sve/revh_2.c: Likewise.
* gcc.target/aarch64/sve/revw_2.c: Likewise.
From-SVN: r274517
This patch makes the floating-point conditional FMA patterns provide the
same /z alternatives as the integer patterns added by a previous patch.
We can handle cases in which individual inputs are allocated to the same
register as the output, so we don't need to force all registers to be
different.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md
(*cond_<SVE_COND_FP_TERNARY:optab><SVE_F:mode>_any): Add /z
alternatives in which one of the inputs is in the same register
as the output.
gcc/testsuite/
* gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA
and FMSB as well as FMLS.
Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274516
We use EXT both to implement vec_extract for large indices and as a
permute. In both cases we can use MOVPRFX to handle the case in which
the first input and output can't be tied.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*vec_extract<mode><Vel>_ext)
(*aarch64_sve_ext<mode>): Add MOVPRFX alternatives.
gcc/testsuite/
* gcc.target/aarch64/sve/ext_2.c: Expect a MOVPRFX.
* gcc.target/aarch64/sve/ext_3.c: New test.
From-SVN: r274515
The floating-point subtraction patterns don't need to handle
subtraction of constants, since those go through the addition
patterns instead. There was a missing MOVPRFX alternative for
FSUBR though.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (*sub<SVE_F:mode>3): Remove immediate
FADD and FSUB alternatives. Add a MOVPRFX alternative for FSUBR.
From-SVN: r274514
FABD and some immediate instructions were missing MOVPRFX alternatives.
This is tested by the ACLE patches but is really an independent improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Kugan Vivekanandarajah <kugan.vivekanandarajah@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (add<SVE_I:mode>3, sub<SVE_I:mode>3)
(<LOGICAL:optab><SVE_I:mode>3, *add<SVE_F:mode>3, *mul<SVE_F:mode>3)
(*fabd<SVE_F:mode>3): Add more MOVPRFX alternatives.
Co-Authored-By: Kugan Vivekanandarajah <kuganv@linaro.org>
From-SVN: r274513
This patch makes us use reversed SVE shifts when the first operand
can't be tied to the output but the second can. This is tested
more thoroughly by the ACLE patches but is really an independent
improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
gcc/
* config/aarch64/aarch64-sve.md (*v<ASHIFT:optab><SVE_I:mode>3):
Add an alternative that uses reversed shifts.
gcc/testsuite/
* gcc.target/aarch64/sve/shift_1.c: Accept reversed shifts.
Co-Authored-By: Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
From-SVN: r274512
The neoversen1 tuning struct gives better performance on the Cortex-A76, so use that.
The only difference from the current tuning is the function and label alignment settings.
This gives about 1.3% improvement on SPEC2006 int and 0.3% on SPEC2006 fp.
* config/aarch64/aarch64-cores.def (cortex-a76): Use neoversen1 tuning
struct.
From-SVN: r274511
This will be tested by the ACLE patches, but it's really an
independent improvement.
2019-08-15 Richard Sandiford <richard.sandiford@arm.com>
gcc/
* config/aarch64/aarch64-sve.md (aarch64_<su>abd<mode>_3): Add
a commutativity marker.
From-SVN: r274510
