* gimplify.c (gimplify_cond_expr): Don't check TREE_ADDRESSABLE.
The front end shouldn't produce a GENERIC COND_EXPR of TREE_ADDRESSABLE
type.
From-SVN: r271524
Here initializing the argument from a TARGET_EXPR isn't an empty class
copy even though the type is !TREE_ADDRESSABLE, so we should check
simple_empty_class_p.
* call.c (build_call_a): Use simple_empty_class_p.
From-SVN: r271523
Remove the hardcoded whitelist of allocators expected to return memory
aligned to alignof(max_align_t), because that doesn't work when the
platform's malloc() and GCC's max_align_t do not agree what the largest
fundamental alignment is. It's also sub-optimal for user-defined
allocators that return memory suitable for any fundamental alignment.
Instead use a hardcoded list of alignments that are definitely supported
by the platform malloc, and use a copy of the allocator rebound to a POD
type with the requested alignment. Only allocate an oversized
buffer to use with std::align for alignments larger than any of the
hardcoded values.
For 32-bit Solaris x86 do not include alignof(max_align_t) in the
hardcoded values.
PR libstdc++/77691
* include/experimental/memory_resource: Add system header pragma.
(__resource_adaptor_common::__guaranteed_alignment): Remove.
(__resource_adaptor_common::_Types)
(__resource_adaptor_common::__new_list)
(__resource_adaptor_common::_New_list)
(__resource_adaptor_common::_Alignments)
(__resource_adaptor_common::_Fund_align_types): New utilities for
creating a list of types with fundamental alignments.
(__resource_adaptor_imp::do_allocate): Call new _M_allocate function.
(__resource_adaptor_imp::do_deallocate): Call new _M_deallocate
function.
(__resource_adaptor_imp::_M_allocate): New function that first tries
to use an allocator rebound to a type with a fundamental alignment.
(__resource_adaptor_imp::_M_deallocate): Likewise for deallocation.
* testsuite/experimental/memory_resource/new_delete_resource.cc:
Adjust expected allocation sizes.
* testsuite/experimental/memory_resource/resource_adaptor.cc: Remove
xfail.
From-SVN: r271522
Yet another tweak that would have fixed this bug: we should treat INIT_EXPR
and MODIFY_EXPR differently for determining whether this is a simple empty
class copy, since a TARGET_EXPR on the RHS is direct initialization if
INIT_EXPR but copy if MODIFY_EXPR.
* cp-gimplify.c (simple_empty_class_p): Also true for MODIFY_EXPR.
From-SVN: r271521
get_frame_size () returns used stack slots during compilation, which
may be optimized out later. This patch does the followings:
1. Add stack_frame_required to machine_function to indicate that the
function needs a stack frame.
2. Change ix86_find_max_used_stack_alignment to set stack_frame_required.
3. Always call ix86_find_max_used_stack_alignment to check if stack
frame is needed.
Tested on i686 and x86-64 with
--with-arch=native --with-cpu=native
Tested on AVX512 machine configured with
--with-arch=native --with-cpu=native
gcc/
PR target/88483
* config/i386/i386-options.c (ix86_init_machine_status): Set
stack_frame_required to true.
* config/i386/i386.c (ix86_get_frame_size): New function.
(ix86_frame_pointer_required): Replace get_frame_size with
ix86_get_frame_size.
(ix86_compute_frame_layout): Likewise.
(ix86_find_max_used_stack_alignment): Changed to void. Set
stack_frame_required.
(ix86_finalize_stack_frame_flags): Always call
ix86_find_max_used_stack_alignment. Replace get_frame_size with
ix86_get_frame_size.
* config/i386/i386.h (machine_function): Add stack_frame_required.
gcc/testsuite/
PR target/88483
* gcc.target/i386/stackalign/pr88483-1.c: New test.
* gcc.target/i386/stackalign/pr88483-2.c: Likewise.
From-SVN: r271517
This patch adds support in the compiler for the architecture feature
flags that binutils will use to enable/disable the new "Future
Architecture Technologies" feature Scalable Vector Extension V2 (SVE2)
announced at Linaro Connect this week.
The "sve2" extension that enables the core sve2 instructions.
This also enables the sve extension, since sve is a requirement of sve2.
Extra optional sve2 features are the bitperm, sm4, aes, and sha3 extensions.
These are all given extra feature flags, "bitperm", "sve2-sm4",
"sve2-aes", and "sve2-sha3" respectively.
The sm4, aes, and sha3 extensions are explicitly marked as sve2
extensions to distinguish them from the corresponding NEON extensions.
When introducing macros to denote these new features we have gone past
what a 32 bit value can represent which means we need to change the type
of those variables working with these feature flags to ensure they use
64 bit quantities.
Tested with bootstrap on aarch64-none-linux-gnu and manually seeing that
-march=armv8-a+typo prints out the expected flags while using the new
feature flags does not complain about a missing flag (until reaching the
assembler).
gcc/ChangeLog:
2019-05-22 Matthew Malcomson <matthew.malcomson@arm.com>
* common/config/aarch64/aarch64-common.c
(struct aarch64_option_extension, struct processor_name_to_arch,
struct arch_to_arch_name, aarch64_parse_extension, opt_ext_cmp,
aarch64_contains_opt,
aarch64_get_extension_string_for_isa_flags): Change type of
variables storing flags to uint64_t.
* config/aarch64/aarch64-option-extensions.def (sve2, sve2-sm4,
sve2-aes, sve2-sha3, bitperm): New optional SVE2 extension flags.
* config/aarch64/aarch64.c (struct processor,
aarch64_parse_arch, aarch64_parse_cpu, aarch64_validate_mcpu,
aarch64_validate_march, aarch64_override_options,
aarch64_option_print, aarch64_handle_attr_isa_flags,
aarch64_declare_function_name, aarch64_start_file): Make flag
variables uint64_t.
* config/aarch64/aarch64.h (AARCH64_FL_SVE2, AARCH64_FL_SVE2_AES,
AARCH64_FL_SVE2_SM4, AARCH64_FL_SVE2_SHA3,
AARCH64_FL_SVE2_BITPERM): New macro feature flags.
* config/aarch64/aarch64.opt (aarch64_isa_flags): Make uint64_t.
* config/aarch64/driver-aarch64.c
(struct aarch64_arch_extension, struct aarch64_core_data,
struct aarch64_arch_driver_info, host_detect_local_cpu): Make
flag variables uint64_t.
* doc/invoke.texi: Add documentation for new arguments.
From-SVN: r271514
2019-05-22 Andrew Stubbs <ams@codesourcery.com>
gcc/fortran/
* trans-stmt.c (gfc_trans_critical): Use size_type_node for
gfor_fndecl_caf_lock and gfor_fndecl_caf_unlock calls.
(gfc_trans_allocate): Use size_type_node for gfor_fndecl_caf_sync_all
call.
From-SVN: r271512
gcc/fortran ChangeLog:
2019-05-22 Jeff Law <law@redhat.com>
Mark Eggleston <mark.eggleston@codethink.com>
PR fortran/89100
* gfortran.texi: Add Default widths for F, G and I format
descriptors to Extensions section.
* invoke.texi: Add -fdec-format-defaults
* io.c (check_format): Use default widths for i, f and g when
flag_dec_format_defaults is enabled.
* lang.opt: Add new option.
* options.c (set_dec_flags): Add SET_BITFLAG for
flag_dec_format_defaults.
gcc/testsuite ChangeLog:
2019-05-22 Mark Eggleston <mark.eggleston@codethink.com>
PR fortran/89100
* gfortran.dg/fmt_f_default_field_width_1.f90: New test.
* gfortran.dg/fmt_f_default_field_width_2.f90: New test.
* gfortran.dg/fmt_f_default_field_width_3.f90: New test.
* gfortran.dg/fmt_g_default_field_width_1.f90: New test.
* gfortran.dg/fmt_g_default_field_width_2.f90: New test.
* gfortran.dg/fmt_g_default_field_width_3.f90: New test.
* gfortran.dg/fmt_i_default_field_width_1.f90: New test.
* gfortran.dg/fmt_i_default_field_width_2.f90: New test.
* gfortran.dg/fmt_i_default_field_width_3.f90: New test.
libgfortran ChangeLog:
2019-05-22 Jeff Law <law@redhat.com>
PR fortran/89100
* io/format.c (parse_format_list): set default width when the
IOPARM_DT_DEC_EXT flag is set for i, f and g.
* io/io.h: add default_width_for_integer, default_width_for_float
and default_precision_for_float.
* io/write.c (write_boz): extra parameter giving length of data
corresponding to the type's kind.
(write_b): pass data length as extra parameter in calls to
write_boz.
(write_o): pass data length as extra parameter in calls to
write_boz.
(write_z): pass data length as extra parameter in calls to
write_boz.
(size_from_kind): also set size is default width is set.
* io/write_float.def (build_float_string): new paramter inserted
before result parameter. If default width use values passed
instead of the values in fnode.
(FORMAT_FLOAT): macro modified to check for default width and
calls to build_float_string to pass in default width.
(get_float_string): set width and precision to defaults when
needed.
From-SVN: r271511
The test can't succeed on 32b powerpc Darwin since the
ABI demands a different result to the tested one.
2019-05-22 Iain Sandoe <iain@sandoe.co.uk>
PR testsuite/27221
* g++.dg/ext/alignof2.C: XFAIL for 32bit Darwin.
From-SVN: r271505
2019-05-22 Martin Liska <mliska@suse.cz>
PR lto/90500
* c-attribs.c (handle_copy_attribute): Do not copy
target_clones attribute.
2019-05-22 Martin Liska <mliska@suse.cz>
PR lto/90500
* gcc.target/i386/pr90500-1.c: Make the test-case valid
now.
2019-05-22 Martin Liska <mliska@suse.cz>
PR lto/90500
* doc/extend.texi: Document the change.
From-SVN: r271504
2019-05-22 Richard Biener <rguenther@suse.de>
PR tree-optimization/90450
* tree-ssa-loop-im.c (struct im_mem_ref): Add ref_decomposed.
(mem_ref_hasher::equal): Check it.
(mem_ref_alloc): Initialize it.
(gather_mem_refs_stmt): Set it.
From-SVN: r271503
I'd like to remove -many from the options passed by default to the
assembler, on the grounds that a gcc bug in instruction selection (eg.
emitting a power9 insn for -mcpu=power8) is better found at assembly
time than run time.
For now, just do this when --enable-checking or gcc is not a release.
This patch also emits .machine assembler directives for ELF targets
when functions are compiled for different cpus via attributes or
pragmas. That's necessary when the initial -m<cpu> option passed to
the assembler doesn't enable the superset of all opcodes emitted, as
seen by a failure of gcc.target/powerpc/clone2.c without .machine
when building gcc for power8.
rs6000_machine_from_flags deliberately uses ISA_2_4_MASKS rather than
ISA_2_2_MASKS for power5 because "friz" and other similar instructions
enabled by gcc with TARGET_FPRND are enabled in gas by "-mpower5".
(gas -mpower5 supports power5+ too.) rs6000-cpus.def puts
OPTION_MASK_FPRND in ISA_2_4_MASKS, so ISA_2_4_MASKS is the one to use
in deciding to pass "-mpower5" to gas.
O3-pr70130.c also failed on an earlier version of this patch (when
only testing one ISA bit to determine .machine). This is a test for a
power7 vector bug, but on power8 hw check_vect_support_and_set_flags
passes -mpower8-vector which means the test isn't exercising the
original bug exactly. I reckon that is wrong, and similary for other
vector testcases that ask for a specific cpu. I've fixed it here by
explicitly passing -mno-power8-vector and similar vector options.
* config/rs6000/rs6000.h (ASM_OPT_ANY): Define.
(ASM_CPU_SPEC): Conditionally add -many.
* config/rs6000/rs6000.c (rs6000_machine): New static var.
(rs6000_machine_from_flags, emit_asm_machine): New functions..
(rs6000_file_start): ..extracted from here, and modified to
test all ISA bits.
(rs6000_output_function_prologue): Emit .machine as necessary.
* testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c: Don't use
power mnemonics.
* testsuite/gcc.dg/vect/O3-pr70130.c: Disable default options
added by check_vect_support_and_set_flags.
* testsuite/gcc.dg/vect/pr48765.c: Likewise.
* testsuite/gfortran.dg/vect/pr45714-b.f: Likewise.
From-SVN: r271500
Gimple jump threading does not duplicate forwarder blocks that might
be present before or after the second copied block. This silently
drops debug binds and markers that might be present in them. This
patch attempts to preserve them.
For blocks after either copied block, we attempt to append debug stmts
to the copied block, if it does not end with a block-ending stmt.
Failing that, for blocks between both copied blocks, we prepend its
debug stmts to the copy of the second block.
If everything fails, we still drop debug stmts on the floor, though
preexisting code consolidates debug binds in the block that threading
flows into, so only markers are really lost. We can't do much better
than that without conditional binds and markers, or debug stmts in
edges, or somesuch.
If we append debug stmts to a reusable template block, we copy it
after splitting out the debug stmts, and before putting them back.
for gcc/ChangeLog
* tree-ssa-threadupdate.c (struct ssa_local_info_t): Add
field template_last_to_copy.
(ssa_create_duplicates): Set it, and use it. Attempt to
preserve more debug stmts.
From-SVN: r271477
These tests require specific scan-asms in some cases because
of the different codegen for Dawin. Added some explanations
too.
2019-05-21 Iain Sandoe <iain@sandoe.co.uk>
PR testsuite/67958
* gcc.target/i386/pr32219-1.c: Adjust scan-asms for Darwin, comment
the differences.
* gcc.target/i386/pr32219-2.c: Likewise.
* gcc.target/i386/pr32219-3.c: Likewise.
* gcc.target/i386/pr32219-4.c: Likewise.
* gcc.target/i386/pr32219-5.c: Likewise.
* gcc.target/i386/pr32219-6.c: Likewise.
* gcc.target/i386/pr32219-7.c: Likewise.
* gcc.target/i386/pr32219-8.c: Likewise.
From-SVN: r271475
This is a testcase failing because one part of the codegen is
(correctly) generating the scan-asm-not signature.
Fixed by altering the build options.
gcc/testsuite/
2019-05-18 Iain Sandoe <iain@sandoe.co.uk>
PR target/63891
* gcc.dg/darwin-weakimport-3.c: Adjust options and explain
the reasons.
From-SVN: r271474
PR bootstrap/87338
* dwarf2out.c (dwarf2out_inline_entry): Use ASM_OUTPUT_DEBUG_LABEL
instead of ASM_GENERATE_INTERNAL_LABEL and ASM_OUTPUT_LABEL.
From-SVN: r271472
* config/i386/cpuid.h (__cpuid): For 32bit targets, zero
%ebx and %ecx bafore calling cpuid with leaf 1 or
non-constant leaf argument.
From-SVN: r271469
PR libstdc++/90252
* testsuite/lib/libstdc++.exp (check_effective_target_tbb-backend):
Use "additional_flags" to pass -ltbb to v3_target_compile command.
Use check_v3_target_prop_cached to cache the result of the test.
From-SVN: r271466
I figure a tweak to register_move_cost is better than sprinkling ?s
in instruction operand alternatives.
PR target/90545
* config/rs6000/rs6000.c (rs6000_register_move_cost): Increase
power9 direct move cost.
* testsuite/gcc.target/powerpc/fold-vec-splats-floatdouble.c:
Correct comments and rename functions to suit parameters.
From-SVN: r271464
