This adds support for Arm's Neoverse N2 CPU to the AArch32 backend.
Neoverse N2 builds AArch32 at EL0 and therefore needs support in AArch32
GCC.
gcc/ChangeLog:
* config/arm/arm-cpus.in (neoverse-n2): New.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* doc/invoke.texi: Document support for Neoverse N2.
This patch adds support for Arm's Neoverse N2 CPU to the AArch64
backend.
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Neoverse N2.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Document AArch64 support for Neoverse N2.
This adds a move CTOR to auto_vec<T, 0> and makes use of a
auto_vec<edge> return value for get_loop_exit_edges denoting
that lifetime management of the vector is handed to the caller.
The move CTOR prompted the hash_table change because it appearantly
makes the copy CTOR implicitely deleted (good) and hash-table
expansion of the odr_enum_map which is
hash_map <nofree_string_hash, odr_enum> where odr_enum has an
auto_vec<odr_enum_val, 0> member triggers this. Not sure if
there's a latent bug there before this (I think we're not
invoking DTORs, but we're invoking copy-CTORs).
2020-08-06 Richard Biener <rguenther@suse.de>
* vec.h (auto_vec<T, 0>::auto_vec (auto_vec &&)): New move CTOR.
(auto_vec<T, 0>::operator=(auto_vec &&)): Delete.
* hash-table.h (hash_table::expand): Use std::move when expanding.
* cfgloop.h (get_loop_exit_edges): Return auto_vec<edge>.
* cfgloop.c (get_loop_exit_edges): Adjust.
* cfgloopmanip.c (fix_loop_placement): Likewise.
* ipa-fnsummary.c (analyze_function_body): Likewise.
* ira-build.c (create_loop_tree_nodes): Likewise.
(create_loop_tree_node_allocnos): Likewise.
(loop_with_complex_edge_p): Likewise.
* ira-color.c (ira_loop_edge_freq): Likewise.
* loop-unroll.c (analyze_insns_in_loop): Likewise.
* predict.c (predict_loops): Likewise.
* tree-predcom.c (last_always_executed_block): Likewise.
* tree-ssa-loop-ch.c (ch_base::copy_headers): Likewise.
* tree-ssa-loop-im.c (store_motion_loop): Likewise.
* tree-ssa-loop-ivcanon.c (loop_edge_to_cancel): Likewise.
(canonicalize_loop_induction_variables): Likewise.
* tree-ssa-loop-manip.c (get_loops_exits): Likewise.
* tree-ssa-loop-niter.c (find_loop_niter): Likewise.
(finite_loop_p): Likewise.
(find_loop_niter_by_eval): Likewise.
(estimate_numbers_of_iterations): Likewise.
* tree-ssa-loop-prefetch.c (emit_mfence_after_loop): Likewise.
(may_use_storent_in_loop_p): Likewise.
This fixes an ICE in noexcept instantiation. It was presuming
functions always have template_info, but that changed with my
DECL_LOCAL_DECL_P changes. Fortunately DECL_LOCAL_DECL_P fns are
never member fns, so we don't need to go fishing out a this pointer.
Also I realized I'd misnamed local10.C, so renaming it local-fn3.C,
and while there adding the effective-target lto that David E pointed
out was missing.
PR c++/97186
gcc/cp/
* pt.c (maybe_instantiate_noexcept): Local externs are never
member fns.
gcc/testsuite/
* g++.dg/template/local10.C: Rename ...
* g++.dg/template/local-fn3.C: .. here. Require lto.
* g++.dg/template/local-fn4.C: New.
re-add tracking of accesses which was unfinished in David's patch.
At the moment I only implemented tracking of the fact that access is based on
derefernece of the parameter (so we track THIS pointers).
Patch does not implement IPA propagation since it needs bit more work which
I will post shortly: ipa-fnsummary needs to track when parameter points to
local memory, summaries needs to be merged when function is inlined (because
jump functions are) and propagation needs to be turned into iterative dataflow
on SCC components.
Patch also adds documentation of -fipa-modref and params that was left uncommited
in my branch :(.
Even without this change it does lead to nice increase of disambiguations
for cc1plus build.
Alias oracle query stats:
refs_may_alias_p: 62758323 disambiguations, 72935683 queries
ref_maybe_used_by_call_p: 139511 disambiguations, 63654045 queries
call_may_clobber_ref_p: 23502 disambiguations, 29242 queries
nonoverlapping_component_refs_p: 0 disambiguations, 37654 queries
nonoverlapping_refs_since_match_p: 19417 disambiguations, 55555 must overlaps, 75721 queries
aliasing_component_refs_p: 54665 disambiguations, 752449 queries
TBAA oracle: 21917926 disambiguations 53054678 queries
15763411 are in alias set 0
10162238 queries asked about the same object
124 queries asked about the same alias set
0 access volatile
3681593 are dependent in the DAG
1529386 are aritificially in conflict with void *
Modref stats:
modref use: 8311 disambiguations, 32527 queries
modref clobber: 742126 disambiguations, 1036986 queries
1987054 tbaa queries (1.916182 per modref query)
125479 base compares (0.121004 per modref query)
PTA query stats:
pt_solution_includes: 968314 disambiguations, 13609584 queries
pt_solutions_intersect: 1019136 disambiguations, 13147139 queries
So compared to
https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554605.html
we get 41% more use disambiguations (with similar number of queries) and 8% more
clobber disambiguations.
For tramp3d:
Alias oracle query stats:
refs_may_alias_p: 2052256 disambiguations, 2312703 queries
ref_maybe_used_by_call_p: 7122 disambiguations, 2089118 queries
call_may_clobber_ref_p: 234 disambiguations, 234 queries
nonoverlapping_component_refs_p: 0 disambiguations, 4299 queries
nonoverlapping_refs_since_match_p: 329 disambiguations, 10200 must overlaps, 10616 queries
aliasing_component_refs_p: 857 disambiguations, 34555 queries
TBAA oracle: 885546 disambiguations 1677080 queries
132105 are in alias set 0
469030 queries asked about the same object
0 queries asked about the same alias set
0 access volatile
190084 are dependent in the DAG
315 are aritificially in conflict with void *
Modref stats:
modref use: 426 disambiguations, 1881 queries
modref clobber: 10042 disambiguations, 16202 queries
19405 tbaa queries (1.197692 per modref query)
2775 base compares (0.171275 per modref query)
PTA query stats:
pt_solution_includes: 313908 disambiguations, 526183 queries
pt_solutions_intersect: 130510 disambiguations, 416084 queries
Here uses decrease by 4 disambiguations and clobber improve by 3.5%. I think
the difference is caused by fact that gcc has much more alias set 0 accesses
originating from gimple and tree unions as I mentioned in original mail.
After pushing out the IPA propagation I will re-add code to track offsets and
sizes that further improve disambiguation. On tramp3d it enables a lot of DSE
for structure fields not acessed by uninlined function.
gcc/
* doc/invoke.texi: Document -fipa-modref, ipa-modref-max-bases,
ipa-modref-max-refs, ipa-modref-max-accesses, ipa-modref-max-tests.
* ipa-modref-tree.c (test_insert_search_collapse): Update.
(test_merge): Update.
(gt_ggc_mx): New function.
* ipa-modref-tree.h (struct modref_access_node): New structure.
(struct modref_ref_node): Add every_access and accesses array.
(modref_ref_node::modref_ref_node): Update ctor.
(modref_ref_node::search): New member function.
(modref_ref_node::collapse): New member function.
(modref_ref_node::insert_access): New member function.
(modref_base_node::insert_ref): Do not collapse base if ref is 0.
(modref_base_node::collapse): Copllapse also refs.
(modref_tree): Add accesses.
(modref_tree::modref_tree): Initialize max_accesses.
(modref_tree::insert): Add access parameter.
(modref_tree::cleanup): New member function.
(modref_tree::merge): Add parm_map; merge accesses.
(modref_tree::copy_from): New member function.
(modref_tree::create_ggc): Add max_accesses.
* ipa-modref.c (dump_access): New function.
(dump_records): Dump accesses.
(dump_lto_records): Dump accesses.
(get_access): New function.
(record_access): Record access.
(record_access_lto): Record access.
(analyze_call): Compute parm_map.
(analyze_function): Update construction of modref records.
(modref_summaries::duplicate): Likewise; use copy_from.
(write_modref_records): Stream accesses.
(read_modref_records): Sream accesses.
(pass_ipa_modref::execute): Update call of merge.
* params.opt (-param=modref-max-accesses): New.
* tree-ssa-alias.c (alias_stats): Add modref_baseptr_tests.
(dump_alias_stats): Update.
(base_may_alias_with_dereference_p): New function.
(modref_may_conflict): Check accesses.
(ref_maybe_used_by_call_p_1): Update call to modref_may_conflict.
(call_may_clobber_ref_p_1): Update call to modref_may_conflict.
With nvptx, we run into:
...
FAIL: gcc.dg/tls/thr-cse-1.c scan-assembler-not \
emutls_get_address.*emutls_get_address.*
...
because the nvptx assembly looks like:
...
call (%value_in), __emutls_get_address, (%out_arg1);
...
// BEGIN GLOBAL FUNCTION DECL: __emutls_get_address
.extern .func (.param.u64 %value_out) __emutls_get_address (.param.u64 %in_ar0);
...
Fix this by checking the slim final dump instead, where we have just:
...
12: r35:DI=call [`__emutls_get_address'] argc:0
...
gcc/testsuite/ChangeLog:
2020-09-24 Tom de Vries <tdevries@suse.de>
* gcc.dg/tls/thr-cse-1.c: Scan final dump instead of assembly for
nvptx.
When running test-case gcc.dg/independent-cloneids-1.c for nvptx, we get:
...
FAIL: scan-assembler-times (?n)^_*bar[.$_]constprop[.$_]0: 1
FAIL: scan-assembler-times (?n)^_*bar[.$_]constprop[.$_]1: 1
FAIL: scan-assembler-times (?n)^_*bar[.$_]constprop[.$_]2: 1
FAIL: scan-assembler-times (?n)^_*foo[.$_]constprop[.$_]0: 1
FAIL: scan-assembler-times (?n)^_*foo[.$_]constprop[.$_]1: 1
FAIL: scan-assembler-times (?n)^_*foo[.$_]constprop[.$_]2: 1
...
The test expects to find something like:
...
bar.constprop.0:
...
but instead on nvptx we have:
...
.func (.param.u32 %value_out) bar$constprop$0
...
Fix this by rewriting the scans to use the final dump instead.
Tested on x86_64.
gcc/testsuite/ChangeLog:
2020-09-24 Tom de Vries <tdevries@suse.de>
* gcc.dg/independent-cloneids-1.c: Use scan-rtl-dump instead of
scan-assembler.
This adds another testcase for the PR97085 fix.
2020-09-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/97085
* gcc.dg/pr97192.c: New testcase.
2020-24-09 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/96495
* trans-expr.c (gfc_conv_procedure_call): Take the deallocation
of allocatable result components of a scalar result outside the
scalarization loop. Find and use the stored result.
gcc/testsuite/
PR fortran/96495
* gfortran.dg/alloc_comp_result_2.f90 : New test.
with nvptx we run into:
...
FAIL: gcc.dg/pr87314-1.c scan-assembler hellooo
...
The required string is part of the assembly, just in a different format than
expected:
...
.const .align 1 .u8 $LC0[12] =
{ 104, 101, 108, 108, 111, 111, 111, 111, 98, 121, 101, 0 };
...
Fix this by adding an nvptx-specific scan-assembler directive.
Tested on nvptx and x86_64.
gcc/testsuite/ChangeLog:
2020-09-24 Tom de Vries <tdevries@suse.de>
* gcc.dg/pr87314-1.c: Add nvptx-specific scan-assembler directive.
These tests were inspired by corresponding aarch64 ones.
They already pass.
gcc/testsuite/
* gcc.target/arm/stack-protector-5.c: New test.
* gcc.target/arm/stack-protector-6.c: Likewise.
For non-PIC, the stack protector patterns did:
rtx mem = XEXP (force_const_mem (SImode, operands[1]), 0);
emit_move_insn (operands[2], mem);
Here, operands[1] is the address of the canary (&__stack_chk_guard)
and operands[2] is the register that we want to move that address into.
However, the code above instead sets operands[2] to the address of a
constant pool entry that contains &__stack_chk_guard, rather than to
&__stack_chk_guard itself. The sequence therefore does one less
pointer indirection than it should.
The net effect was to use &__stack_chk_guard for stack-smash detection,
instead of using __stack_chk_guard itself.
gcc/
* config/arm/arm.md (*stack_protect_combined_set_insn): For non-PIC,
load the address of the canary rather than the address of the
constant pool entry that points to it.
(*stack_protect_combined_test_insn): Likewise.
gcc/testsuite/
* gcc.target/arm/stack-protector-3.c: New test.
* gcc.target/arm/stack-protector-4.c: Likewise.
The following aovids the ICE in the testcase by doing some additional
simplification of VEC_COND_EXPRs for VECTOR_BOOLEAN_TYPE_P which
we don't really expect, esp. when they are not classical vectors,
thus AVX512 or SVE masks.
2020-09-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/97085
* match.pd (mask ? { false,..} : { true, ..} -> ~mask): New.
* gcc.dg/vect/pr97085.c: New testcase.
With the nvptx target, we run into:
...
FAIL: gcc.dg/pr94600-1.c scan-rtl-dump-times final "\\(mem/v" 6
FAIL: gcc.dg/pr94600-1.c scan-rtl-dump-times final "\\(set \\(mem/v" 6
FAIL: gcc.dg/pr94600-3.c scan-rtl-dump-times final "\\(mem/v" 1
FAIL: gcc.dg/pr94600-3.c scan-rtl-dump-times final "\\(set \\(mem/v" 1
...
The scans attempt to check for volatile stores, but on nvptx we have memcpy
instead.
This is due to nvptx being a STRICT_ALIGNMENT target, which has the effect
that the TYPE_MODE for the store target is set to BKLmode in
compute_record_mode.
Fix the FAILs by requiring effective target non_strict_align.
Tested on nvptx.
gcc/testsuite/ChangeLog:
2020-09-24 Tom de Vries <tdevries@suse.de>
* gcc.dg/pr94600-1.c: Require effective target non_strict_align for
scan-rtl-dump-times.
* gcc.dg/pr94600-3.c: Same.
Pair ggc_delete with ggc_alloc_no_dtor. I copy same scheme as used by Martin
in ipa-fnsummary, that is creating a static member function create_ggc hidding
the ugly bits and using it in ipa-modref.c.
I also noticed that modref-tree leaks memory on destruction/collapse method and
fixed that.
Bootstrapped/regtested x86_64-linux.
gcc/ChangeLog:
2020-09-24 Jan Hubicka <hubicka@ucw.cz>
* ipa-modref-tree.h (modref_base::collapse): Release memory.
(modref_tree::create_ggc): New member function.
(modref_tree::colapse): Release memory.
(modref_tree::~modref_tree): New destructor.
* ipa-modref.c (modref_summaries::create_ggc): New function.
(analyze_function): Use create_ggc.
(modref_summaries::duplicate): Likewise.
(read_modref_records): Likewise.
(modref_read): Likewise.
When running test-case c-c++-common/builtin-has-attribute-3.c on nvptx, I get:
...
FAIL: c-c++-common/builtin-has-attribute-3.c -Wc++-compat \
(test for excess errors)
Excess errors:
src/gcc/testsuite/c-c++-common/builtin-has-attribute-3.c:33:33: error: \
alias definitions not supported in this configuration
...
Fix this by adding -DSKIP_ALIAS to the compilation options for effective
target ! alias.
Tested on nvptx.
gcc/testsuite/ChangeLog:
* c-c++-common/builtin-has-attribute-3.c: Compile with -DSKIP_ALIAS
for effective target ! alias.
The commit r11-3230 brings a nice improvement to use full
vectors instead of partial vectors when available. This
patch is to fix the test failures on p9-vec-length-full-6.c,
where 64bit/32bit pairs are able to use full vector instead.
Bootstrapped/regtested on powerpc64le-linux-gnu P9.
gcc/testsuite/ChangeLog:
PR tree-optimization/97075
* gcc.target/powerpc/p9-vec-length-full-6.c: Adjust.
These functions do behave a little differently for SImode, so the
mode should be passed.
* config/rs6000/rs6000.c (rs6000_rtx_costs): Pass mode to
reg_or_add_cint_operand and reg_or_sub_cint_operand.
rldimi is generated by rs6000_emit_set_long_const when the high and
low 32 bits of a 64-bit constant are equal.
PR target/93012
* config/rs6000/rs6000.c (num_insns_constant_gpr): Count rldimi
constants correctly.
Power10 pc-relative code doesn't use or preserve r2 as a TOC pointer.
That means calling between pc-relative and TOC using code can't be
done without intervening linker stubs, and a call from TOC code to
pc-relative code must have a nop after the bl in order to restore r2.
Now the PowerPC libffi assembly code doesn't use r2 except for the
implicit use when making calls back to C, ffi_closure_helper_LINUX64
and ffi_prep_args64. So changing the assembly to interoperate with
pc-relative code without stubs is easily done.
* src/powerpc/linux64.S (ffi_call_LINUX64): Don't emit global
entry when __PCREL__. Call using @notoc. Add nops.
* src/powerpc/linux64_closure.S (ffi_closure_LINUX64): Likewise.
(ffi_go_closure_linux64): Likewise.
Useful in assembly to know details of power10 function calls.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros):
Conditionally define __PCREL__.
Calls from split-stack code to non-split-stack code need to expand
mapped stack memory via __morestack. Even tail calls.
__morestack is quite a surprising function on powerpc in that it calls
back to its caller, and a tail call will continue running in the
context of extra mapped stack.
PR target/97107
* config/rs6000/rs6000-internal.h (struct rs6000_stack): Improve
calls_p comment.
* config/rs6000/rs6000-logue.c (rs6000_stack_info): Likewise.
(rs6000_expand_split_stack_prologue): Emit the prologue for
functions that make a sibling call.
PR analyzer/93355 reports a missing diagnostic about a FILE leak in
intl/localealias.c. This appears to be due to a issue in the
feasibility-checking code, though there is also a state explosion.
This patch adds test cases that I've been using when investigating this,
two of them currently requiring -fno-analyzer-feasibility, and one
currently requiring -Wno-analyzer-too-complex.
gcc/testsuite/ChangeLog:
PR analyzer/93355
* gcc.dg/analyzer/pr93355-localealias-feasibility.c: New test.
* gcc.dg/analyzer/pr93355-localealias-simplified.c: New test.
* gcc.dg/analyzer/pr93355-localealias.c: New test.
This patch provides a new option "-fno-analyzer-feasibility" as a way
to disable feasibility-checking of the constraints along the control
flow paths for -fanalyzer diagnostics. I'm adding this in the hope of
making it easier to debug issues involving the feasibility-checking
logic.
The patch adds a new rejected_constraint object which is captured if
exploded_path::feasible_p fails, and adds logic that uses this to emit
an additional custom_event within the checker_path for the diagnostic,
showing where in the control flow path the diagnostic would have been
rejected, and giving details of why.
gcc/analyzer/ChangeLog:
* analyzer.h (struct rejected_constraint): New decl.
* analyzer.opt (fanalyzer-feasibility): New option.
* diagnostic-manager.cc (path_builder::path_builder): Add
"problem" param and use it to initialize new field.
(path_builder::get_feasibility_problem): New accessor.
(path_builder::m_feasibility_problem): New field.
(dedupe_winners::add): Remove inversion of logic in "if" clause,
swapping if/else suites. In the !feasible_p suite, inspect
flag_analyzer_feasibility and add code to handle when this
is off, accepting the infeasible path, but recording the
feasibility_problem.
(diagnostic_manager::emit_saved_diagnostic): Pass the
feasibility_problem to the path_builder.
(diagnostic_manager::add_events_for_eedge): If we have
a feasibility_problem at this edge, use it to add a custom event.
* engine.cc (exploded_path::feasible_p): Pass a
rejected_constraint ** to model.maybe_update_for_edge and transfer
ownership of any created instance to any feasibility_problem.
(feasibility_problem::dump_to_pp): New.
* exploded-graph.h (feasibility_problem::feasibility_problem):
Drop "model" param; add rejected_constraint * param.
(feasibility_problem::~feasibility_problem): New.
(feasibility_problem::dump_to_pp): New decl.
(feasibility_problem::m_model): Drop field.
(feasibility_problem::m_rc): New field.
* program-point.cc (function_point::get_location): Handle
PK_BEFORE_SUPERNODE and PK_AFTER_SUPERNODE.
* program-state.cc (program_state::on_edge): Pass NULL to new
param of region_model::maybe_update_for_edge.
* region-model.cc (region_model::add_constraint): New overload
adding a rejected_constraint ** param.
(region_model::maybe_update_for_edge): Add rejected_constraint **
param and pass it to the various apply_constraints_for_ calls.
(region_model::apply_constraints_for_gcond): Add
rejected_constraint ** param and pass it to add_constraint calls.
(region_model::apply_constraints_for_gswitch): Likewise.
(region_model::apply_constraints_for_exception): Likewise.
(rejected_constraint::dump_to_pp): New.
* region-model.h (region_model::maybe_update_for_edge):
Add rejected_constraint ** param.
(region_model::add_constraint): New overload adding a
rejected_constraint ** param.
(region_model::apply_constraints_for_gcond): Add
rejected_constraint ** param.
(region_model::apply_constraints_for_gswitch): Likewise.
(region_model::apply_constraints_for_exception): Likewise.
(struct rejected_constraint): New.
gcc/ChangeLog:
* doc/analyzer.texi (Analyzer Paths): Add note about
-fno-analyzer-feasibility.
* doc/invoke.texi (Static Analyzer Options): Add
-fno-analyzer-feasibility.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/feasibility-2.c: New test.
When the "Vector Insert" section was added to the documentation,
the doubleword ('d') variant was omitted. Add it.
2020-09-23 Paul A. Clarke <pc@us.ibm.com>
gcc/
* doc/extend.texi: Add 'd' for doubleword variant of
vector insert instruction.
gcc/ChangeLog:
PR middle-end/97175
* builtins.c (maybe_warn_for_bound): Handle both DECLs and EXPRESSIONs
in pad->dst.ref, same is pad->src.ref.
gcc/testsuite/ChangeLog:
PR middle-end/97175
* gcc.dg/Wstringop-overflow-44.c: New test.
With test-case gcc.c-torture/compile/pr92231.c, we run into:
...
nvptx-as: ptxas terminated with signal 11 [Segmentation fault], core dumped^M
compiler exited with status 1
FAIL: gcc.c-torture/compile/pr92231.c -O0 (test for excess errors)
...
due to using a function reference plus constant as operand:
...
mov.u64 %r24,bar+4096';
...
Fix this by splitting such an insn into:
...
mov.u64 %r24,bar';
add.u64 %r24,%r24,4096';
...
Tested on nvptx.
gcc/ChangeLog:
* config/nvptx/nvptx.md: Don't allow operand containing sum of
function ref and const.
This patch fixes the equivalent of arm bug PR85434/CVE-2018-12886
for aarch64: under high register pressure, the -fstack-protector
code might spill the address of the canary onto the stack and
reload it at the test site, giving an attacker the opportunity
to change the expected canary value.
This would happen in two cases:
- when generating PIC for -mstack-protector-guard=global
(tested by stack-protector-6.c). This is a direct analogue
of PR85434, which was also about PIC for the global case.
- when using -mstack-protector-guard=sysreg.
The two problems were really separate bugs and caused by separate code,
but it was more convenient to fix them together.
The post-patch code still spills _GLOBAL_OFFSET_TABLE_ for
stack-protector-6.c, which is a more general problem. However,
it no longer spills the canary address itself.
The patch also fixes an ICE when using -mstack-protector-guard=sysreg
with ILP32: even if the register read is SImode, the address
calculation itself should still be DImode.
gcc/
* config/aarch64/aarch64-protos.h (aarch64_salt_type): New enum.
(aarch64_stack_protect_canary_mem): Declare.
* config/aarch64/aarch64.md (UNSPEC_SALT_ADDR): New unspec.
(stack_protect_set): Forward to stack_protect_combined_set.
(stack_protect_combined_set): New pattern. Use
aarch64_stack_protect_canary_mem.
(reg_stack_protect_address_<mode>): Add a salt operand.
(stack_protect_test): Forward to stack_protect_combined_test.
(stack_protect_combined_test): New pattern. Use
aarch64_stack_protect_canary_mem.
* config/aarch64/aarch64.c (strip_salt): New function.
(strip_offset_and_salt): Likewise.
(tls_symbolic_operand_type): Use strip_offset_and_salt.
(aarch64_stack_protect_canary_mem): New function.
(aarch64_cannot_force_const_mem): Use strip_offset_and_salt.
(aarch64_classify_address): Likewise.
(aarch64_symbolic_address_p): Likewise.
(aarch64_print_operand): Likewise.
(aarch64_output_addr_const_extra): New function.
(aarch64_tls_symbol_p): Use strip_salt.
(aarch64_classify_symbol): Likewise.
(aarch64_legitimate_pic_operand_p): Use strip_offset_and_salt.
(aarch64_legitimate_constant_p): Likewise.
(aarch64_mov_operand_p): Use strip_salt.
(TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA): Override.
gcc/testsuite/
* gcc.target/aarch64/stack-protector-5.c: New test.
* gcc.target/aarch64/stack-protector-6.c: Likewise.
* gcc.target/aarch64/stack-protector-7.c: Likewise.
These tests were inspired by corresponding arm ones. They already pass.
gcc/testsuite/
* gcc.target/aarch64/stack-protector-3.c: New test.
* gcc.target/aarch64/stack-protector-4.c: Likewise.
This patch implements the missing reinterprets to and from poly128_t and
float64x2_t.
I've plugged in the appropriate testing in the advsimd-intrinsics.exp
too.
Bootstrapped and tested on aarch64-none-linux-gnu.
Tested advsimd-intrinsics.exp on arm-none-eabi too to make sure arm
testing isn't affected.
gcc/
PR target/71233
* config/aarch64/arm_neon.h (vreinterpretq_f64_p128,
vreinterpretq_p128_f64): Define.
gcc/testsuite/
PR target/71233
* gcc.target/aarch64/advsimd-intrinsics/arm-neon-ref.h
(clean_results): Add float64x2_t cleanup.
(DECL_VARIABLE_128BITS_VARIANTS): Add float64x2_t variable.
* gcc.target/aarch64/advsimd-intrinsics/vreinterpret_p128.c: Add
testing of vreinterpretq_f64_p128, vreinterpretq_p128_f64.
This is C++, we don't need 'typedef struct foo foo;'. Oh, and bool
bitfields are a thing.
gcc/cp/
* name-lookup.h (typedef cxx_binding): Delete tdef.
(typedef cp_binding_level): Likewise.
(struct cxx_binding): Flags are bools.
This adds support for Arm's Neoverse V1 CPU to the AArch32 backend.
---
gcc/ChangeLog:
* config/arm/arm-cpus.in (neoverse-v1): New.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* doc/invoke.texi: Document support for Neoverse V1.
This adds support for Arm's Neoverse V1 CPU to the AArch64 backend.
---
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def: Add Neoverse V1.
* config/aarch64/aarch64-tune.md: Regenerate.
* doc/invoke.texi: Document support for Neoverse V1.
I'd missed the piece of substutution for the uses of a local extern
decl. Just grab the local specialization. We need to do this
regardless of dependentness because we always cloned the local extern.
PR c++/97171
gcc/cp/
* pt.c (tsubst_copy) [FUNCTION_DECL,VAR_DECL]: Retrieve local
specialization for DECL_LOCAL_P decls.
gcc/testsuite/
* g++.dg/template/local10.C: New.
We crash here because since r11-3302 the C FE uses codes like SWITCH_STMT
in the else branches in the attached test, and inchash::add_expr in
do_warn_duplicated_branches doesn't handle these front-end codes. In
the C++ FE this works because by the time we get to do_warn_duplicated_branches
we've already cp_genericize'd the SWITCH_STMT tree into a SWITCH_EXPR.
The fix is to call do_warn_duplicated_branches_r only after loops and other
structured control constructs have been lowered.
gcc/c-family/ChangeLog:
PR c/97125
* c-gimplify.c (c_genericize): Only call do_warn_duplicated_branches_r
after loops and other structured control constructs have been lowered.
gcc/testsuite/ChangeLog:
PR c/97125
* c-c++-common/Wduplicated-branches-15.c: New test.
This relaxes the condition under which we also try NE_EXPR
for a fake generated compare in addition to LT_EXPR given
the fact the verification ICEd when it failed but obviously
was only implemented for constants. Thus the patch removes
the verification and the restriction to constant operands.
2020-09-23 Richard Biener <rguenther@suse.de>
PR middle-end/96453
* gimple-isel.cc (gimple_expand_vec_cond_expr): Remove
LT_EXPR -> NE_EXPR verification and also apply it for
non-constant masks.
* gcc.dg/pr96453.c: New testcase.
this patch fixes bug in tracking memory stats and also I have noticed that while
the pass takes care to stop traking things when things are obviously out of hand
it still keeps summaries that have no useful info for loads or stores and also
many summaries are just copying const/pure attributes. This patch thus also
adds logic to detect if summary is useful and drop it early otherwise. This
reduces number of queries to the oracle and saves memory/lto streaming.
For cc1plus LTO build (configured with --disable-plugin
--enable-checking=release --with-build-config=lto) I now get:
Alias oracle query stats:
refs_may_alias_p: 62488734 disambiguations, 72660949 queries
ref_maybe_used_by_call_p: 128863 disambiguations, 63393551 queries
call_may_clobber_ref_p: 16013 disambiguations, 21776 queries
nonoverlapping_component_refs_p: 0 disambiguations, 37628 queries
nonoverlapping_refs_since_match_p: 19397 disambiguations, 55370 must overlaps, 75516 queries
aliasing_component_refs_p: 54741 disambiguations, 752198 queries
TBAA oracle: 21632692 disambiguations 52565147 queries
15656420 are in alias set 0
10108172 queries asked about the same object
124 queries asked about the same alias set
0 access volatile
3640460 are dependent in the DAG
1527279 are aritificially in conflict with void *
Modref stats:
modref use: 5712 disambiguations, 31221 queries
modref clobber: 684316 disambiguations, 1010000 queries
1779717 tbaa queries (1.762096 per modref query)
PTA query stats:
pt_solution_includes: 947334 disambiguations, 13601373 queries
pt_solutions_intersect: 1011662 disambiguations, 13139565 queries
The number of queries should change, but the number of disambiguations should
not. However comparing with stats here
https://gcc.gnu.org/pipermail/gcc-patches/2020-September/554309.html
I see about 50% drop in clobber disambiguations. There is however same drop in
other alias oracle stats. I suppose someting changed in meanwhile on mainline
because I was basing that on older tree. I tried to proofread changes between
mainline and branch and they seem all quite obvious.
This is consistent with what I get on tramp3d:
Alias oracle query stats:
refs_may_alias_p: 2051320 disambiguations, 2312132 queries
ref_maybe_used_by_call_p: 7058 disambiguations, 2088222 queries
call_may_clobber_ref_p: 232 disambiguations, 232 queries
nonoverlapping_component_refs_p: 0 disambiguations, 4339 queries
nonoverlapping_refs_since_match_p: 329 disambiguations, 10200 must overlaps, 10616 queries
aliasing_component_refs_p: 857 disambiguations, 34639 queries
TBAA oracle: 886768 disambiguations 1670635 queries
131572 are in alias set 0
461689 queries asked about the same object
0 queries asked about the same alias set
0 access volatile
190291 are dependent in the DAG
315 are aritificially in conflict with void *
Modref stats:
modref use: 430 disambiguations, 1885 queries
modref clobber: 9657 disambiguations, 16076 queries
19027 tbaa queries (1.183566 per modref query)
PTA query stats:
pt_solution_includes: 311756 disambiguations, 524179 queries
pt_solutions_intersect: 129689 disambiguations, 415878 queries
In both cases the number of disambiguations should be same (queries are not
comparable).
Bootstrapped/regtested x86_64-linux, comitted.
gcc/ChangeLog:
2020-09-23 Jan Hubicka <hubicka@ucw.cz>
* ipa-modref.c (modref_summary::lto_useful_p): New member function.
(modref_summary::useful_p): New member function.
(analyze_function): Drop useless summaries.
(modref_write): Skip useless summaries.
(pass_ipa_modref::execute): Drop useless summaries.
* ipa-modref.h (struct GTY): Declare useful_p and lto_useful_p.
* tree-ssa-alias.c (dump_alias_stats): Fix.
(modref_may_conflict): Fix stats.
We need to avoid forcing BLKmode for truth vectors, instead do as
other code and use VOIDmode so layout_type can pick a suitable and
consistent mode. RTL expansion of vect_cond_mask also needs to deal
with CONST_INT operands which means passing the mode explicitely.
2020-09-23 Richard Biener <rguenther@suse.de>
PR middle-end/96466
* internal-fn.c (expand_vect_cond_mask_optab_fn): Use
appropriate mode for force_reg.
* tree.c (build_truth_vector_type_for): Pass VOIDmode to
make_vector_type.
* gcc.dg/pr96466.c: New testcase.
This patch fixes the fallout that Kewen reported on Power after
the recent change to avoid unnecessary use of partial vectors.
As Kewen said, the problem is that vect_analyze_loop_2 doesn't
know how many epilogue iterations there will be, and so it
cannot make a final decision about whether the number of
iterations forces an epilogue loop to use partial vectors.
This is similar to the current situation for peeling: we don't know
during initial analysis whether an epilogue loop will itself require
peeling. Instead we decide that during vect_do_peeling, where the
final number of epilogue loop iterations is known.
The patch takes a similar approach for the decision about whether
to use partial vectors. As the comments in the patch say, the
idea is that vect_analyze_loop_2 should make peeling and partial-
vector decisions based on the assumption that the loop_vinfo will
be used as the main loop, while vect_do_peeling should make them
in the knowledge that the loop_vinfo will be used as an epilogue loop.
This allows the same analysis to be used for both cases, which we
rely on for implementing VECT_COMPARE_COSTS; see the big comment
in vect_analyze_loop for details.
I hope the patch makes the (mostly preexisting) structure a bit
more obvious. It isn't what anyone would design from scratch,
but that's the nature of working with a mature vector framework.
Arranging things this way means that vect_verify_full_masking
and vect_verify_loop_lens now become part of the “can” rather
than “will” test for partial vectors.
Also, while splitting out the logic that handles epilogues with
constant iterations, I added a check to make sure that we don't
try to use partial vectors to vectorise a single-scalar loop.
This required some changes to the Power tests.
gcc/
* tree-vectorizer.h (determine_peel_for_niter): Delete in favor of...
(vect_determine_partial_vectors_and_peeling): ...this new function.
* tree-vect-loop-manip.c (vect_update_epilogue_niters): New function.
Reject using vector epilogue loops for single iterations. Install
the constant number of epilogue loop iterations in the associated
loop_vinfo. Rely on vect_determine_partial_vectors_and_peeling
to do the main part of the test.
(vect_do_peeling): Use vect_update_epilogue_niters to handle
epilogue loops with a known number of iterations. Skip recomputing
the number of iterations later in that case. Otherwise, use
vect_determine_partial_vectors_and_peeling to decide whether the
epilogue loop needs to use partial vectors or peeling.
* tree-vect-loop.c (_loop_vec_info::_loop_vec_info): Set the
default can_use_partial_vectors_p to false if partial-vector-usage=0.
(determine_peel_for_niter): Remove in favor of...
(vect_determine_partial_vectors_and_peeling): ...this new function,
split out from...
(vect_analyze_loop_2): ...here. Reflect the vect_verify_full_masking
and vect_verify_loop_lens results in CAN_USE_PARTIAL_VECTORS_P
rather than USING_PARTIAL_VECTORS_P.
gcc/testsuite/
* gcc.target/powerpc/p9-vec-length-epil-1.c: Do not expect the
single-iteration epilogues of the 64-bit loops to be vectorized.
* gcc.target/powerpc/p9-vec-length-epil-7.c: Likewise.
* gcc.target/powerpc/p9-vec-length-epil-8.c: Likewise.
This patch implements the missing vrndns_f32 intrinsic. This operates on a scalar float32_t value.
It can be mapped down to a __builtin_aarch64_frintnsf builtin.
This patch does that.
Bootstrapped and tested on aarch64-none-linux-gnu.
gcc/
PR target/71233
* config/aarch64/aarch64-simd-builtins.def (frintn): Use BUILTIN_VHSDF_HSDF
for modes. Remove explicit hf instantiation.
* config/aarch64/arm_neon.h (vrndns_f32): Define.
gcc/testsuite/
PR target/71233
* gcc.target/aarch64/simd/vrndns_f32_1.c: New test.
The condition we're expecting to eventually run into isn't fully
captured by checking for CTORs, instead we can also run into the
CTOR element conversion.
2020-09-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/97173
* tree-vect-loop.c (vectorizable_live_operation): Extend
assert to also conver element conversions.
* gcc.dg/vect/pr97173.c: New testcase.
