We used to build baremetal (AKA Elf32) multilibbed toolchains for years
now but never made that for Linux targets since there were problems with
uClibc n multilib setup. Now with help of Crosstool-NG it is finally
possible to create uClibc-based multilibbed toolchains and so we add
relevant CPUs for multilib in case of configuration for "arc*-*-linux*".
This will be essentially useful for glibc-based multilibbbed toolchains
in the future.
gcc/
2018-05-16 Alexey Brodkin <abrodkin@synopsys.com>
* config.gcc: Add arc/t-multilib-linux to tmake_file for
arc*-*-linux*.
* config/arc/t-multilib-linux: Specify MULTILIB_OPTIONS and
MULTILIB_DIRNAMES
From-SVN: r260434
2018-05-20 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82275
Correcting ChangeLogs
* match.c (gfc_match_type_spec): Go through the array ref and
decrement 'rank' for every dimension that is an element.
2018-05-20 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82275
Correcting ChangeLogs
* gfortran.dg/select_type_42.f90: New test.
From-SVN: r260416
2018-05-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/80657
* resolve.c (flag_fn_result_spec): Use the 'sym' argument to
test for self refs to the function result in the character len
expression. If a self reference is found, emit an error and
return true.
(resolve_fntype): Use the function symbol in the calls to the
above.
2018-05-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/80657
* gfortran.dg/char_result_18.f90: New test.
From-SVN: r260415
2018-05-20 Paul Thomas <pault@gcc.gnu.org>
PR fortran/49636
* trans-array.c (gfc_get_array_span): Renamed from
'get_array_span'.
(gfc_conv_expr_descriptor): Change references to above.
* trans-array.h : Add prototype for 'gfc_get_array_span'.
* trans-stmt.c (trans_associate_var): If the associate name is
a subref array pointer, use gfc_get_array_span for the span.
2018-05-20 Paul Thomas <pault@gcc.gnu.org>
PR fortran/49636
* gfortran.dg/associate_38.f90: New test.
From-SVN: r260414
2018-05-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82923
PR fortran/66694
PR fortran/82617
* trans-array.c (gfc_alloc_allocatable_for_assignment): Set the
charlen backend_decl of the rhs expr to ss->info->string_length
so that the value in the current scope is used.
2018-05-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82923
* gfortran.dg/allocate_assumed_charlen_4.f90: New test. Note
that the patch fixes PR66694 & PR82617, although the testcases
are not explicitly included.
From-SVN: r260413
gcc/
* config/nds32/nds32.c (nds32_register_move_cost): Take garywolf cpu
into consideration.
Co-Authored-By: Chung-Ju Wu <jasonwucj@gmail.com>
From-SVN: r260412
* config/i386/i386.md (rex64namesuffix): New mode attribute.
* config/i386/sse.md (sse_cvtsi2ss<rex64namesuffix><round_name>):
Merge insn pattern from sse_cvtsi2ss<round_name> and
sse_cvtsi2ssq<round_name> using SWI48 mode iterator.
(sse_cvtss2si<rex64namesuffix><round_name>): Merge insn pattern
from sse_cvtss2si<round_name> and sse_cvtss2siq<round_name>
using SWI48 mode iterator.
(sse_cvtss2si<rex64namesuffix>_2): Merge insn pattern from
sse_cvtss2si_2 and sse_cvtss2siq_2 using SWI48 mode iterator.
(sse_cvttss2si<rex64namesuffix><round_saeonly_name>): Merge insn
pattern from sse_cvttss2si<round_saeonly_name>
and sse_cvttss2siq<round_saeonly_name> using SWI48 mode iterator.
(avx512f_vcvtss2usi<rex64namesuffix><round_name>): Merge insn pattern
from avx512f_vcvtss2usi<round_name> and avx512f_vcvtss2usiq<round_name>
using SWI48 mode iterator.
(avx512f_vcvttss2usi<rex64namesuffix><round_saeonly_name>): Merge
insn pattern from avx512f_vcvttss2usi<round_saeonly_name> and
avx512f_vcvttss2usiq<round_saeonly_name> using SWI48 mode iterator.
(avx512f_vcvtsd2usi<rex64namesuffix><round_name>): Merge insn pattern
from avx512f_vcvtsd2usi<round_name> and avx512f_vcvtsd2usiq<round_name>
using SWI48 mode iterator.
(avx512f_vcvttsd2usi<rex64namesuffix><round_saeonly_name>): Merge
insn pattern from avx512f_vcvttsd2usi<round_saeonly_name> and
avx512f_vcvttsd2usiq<round_saeonly_name> using SWI48 mode iterator.
(sse2_cvtsd2si<rex64namesuffix><round_name>): Merge insn pattern from
sse2_cvtsd2si<round_name> and sse2_cvtsd2siq<round_name> using
SWI48 mode iterator.
(sse2_cvtsd2si<rex64namesuffix>_2): Merge insn pattern from
sse2_cvtsd2si_2 and sse2_cvtsd2siq_2 using SWI48 mode iterator.
(sse_cvttsd2si<rex64namesuffix><round_saeonly_name>): Merge insn
pattern from sse_cvttsd2si<round_saeonly_name>
and sse_cvttsd2siq<round_saeonly_name> using SWI48 mode iterator.
From-SVN: r260397
2018-05-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82923
PR fortran/66694
PR fortran/82617
* trans-array.c (gfc_alloc_allocatable_for_assignment): Set the
charlen backend_decl of the rhs expr to ss->info->string_length
so that the value in the current scope is used.
2018-05-19 Paul Thomas <pault@gcc.gnu.org>
PR fortran/82923
* gfortran.dg/allocate_assumed_charlen_4.f90: New test. Note
that the patch fixes PR66694 & PR82617, although the testcases
are not explicitly included.
From-SVN: r260392
* src/c++11/codecvt.cc (__codecvt_utf8_base<wchar_t>::do_in)
[__SIZEOF_WCHAR_T__==2 && __BYTE_ORDER__!=__ORDER_BIG_ENDIAN__]: Set
little_endian element in bitmask.
* testsuite/22_locale/codecvt/codecvt_utf8/69703.cc: Run all tests.
* testsuite/22_locale/codecvt/codecvt_utf8/wchar_t/1.cc: New.
From-SVN: r260389
In C++11 and C++14 any odr-use of these constants requires a definition
at namespace-scope. In C++17 they are implicitly inline and so the
namespace-scope redeclarations are redundant (and allowing them is
deprecated).
PR libstdc++/85098
* include/bits/regex.h [__cplusplus < 201703L] (basic_regex::icase)
(basic_regex::nosubs, basic_regex::optimize, basic_regex::collate)
(basic_regex::ECMAScript, basic_regex::basic, basic_regex::extended)
(basic_regex::awk, basic_regex::grep, basic_regex::egrep): Add
definitions.
* include/bits/regex_automaton.h (_NFA::_M_insert_state): Adjust
whitespace.
* include/bits/regex_compiler.tcc (__INSERT_REGEX_MATCHER): Add
braces around body of do-while.
* testsuite/28_regex/basic_regex/85098.cc: New
From-SVN: r260371
We deprecated architecture versions earlier than Armv4T in GCC 6 [1].
This patch removes support for architectures lower than Armv4.
That is the -march values armv2, armv2a, armv3, armv3m are removed
with this patch. I did not remove armv4 because it's a bit more
involved code-wise and there has been some pushback on the implications
for -mcpu=strongarm support.
Removing armv3m and earlier though is pretty straightforward.
This allows us to get rid of the armv3m and mode32 feature bits
in arm-cpus.in as they can be assumed to be universally available.
Consequently the mcpu values arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720, arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dm are now also removed.
Bootstrapped and tested on arm-none-linux-gnueabihf and on arm-none-eabi
with an aprofile multilib configuration (which builds quite a lot of library
configurations).
[1] https://gcc.gnu.org/gcc-6/changes.html#arm
* config/arm/arm-cpus.in (armv3m, mode32): Delete features.
(ARMv4): Update.
(ARMv2, ARMv3, ARMv3m): Delete fgroups.
(ARMv6m): Update.
(armv2, armv2a, armv3, armv3m): Delete architectures.
(arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620,
arm7, arm7d, arm7di, arm70, arm700, arm700i, arm710, arm720,
arm710c, arm7100, arm7500, arm7500fe, arm7m, arm7dm, arm7dmi):
Delete cpus.
* config/arm/arm.md (maddsidi4): Remove check for arm_arch3m.
(*mulsidi3adddi): Likewise.
(mulsidi3): Likewise.
(*mulsidi3_nov6): Likewise.
(umulsidi3): Likewise.
(umulsidi3_nov6): Likewise.
(umaddsidi4): Likewise.
(*umulsidi3adddi): Likewise.
(smulsi3_highpart): Likewise.
(*smulsi3_highpart_nov6): Likewise.
(umulsi3_highpart): Likewise.
(*umulsi3_highpart_nov6): Likewise.
* config/arm/arm.h (arm_arch3m): Delete.
* config/arm/arm.c (arm_arch3m): Delete.
(arm_option_override_internal): Update armv3-related comment.
(arm_configure_build_target): Delete use of isa_bit_mode32.
(arm_option_reconfigure_globals): Delete set of arm_ach3m.
(arm_rtx_costs_internal): Delete check of arm_arch3m.
* config/arm/arm-fixed.md (mulsq3): Delete check for arm_arch3m.
(mulsa3): Likewise.
(mulusa3): Likewise.
* config/arm/arm-protos.h (arm_arch3m): Delete.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Likewise.
* config/arm/t-arm-elf (all_early_nofp): Delete mentions of
deleted architectures.
* gcc.target/arm/pr62554.c: Delete.
* gcc.target/arm/pr69610-1.c: Likewise.
* gcc.target/arm/pr69610-2.c: Likewise.
From-SVN: r260363
The -march=armv5 and armv5e options have been deprecated in GCC 7 [1].
This patch removes support for them.
It's mostly mechanical stuff. The functionality that was previously
gated on arm_arch5 is now gated on arm_arch5t and the functionality
that was gated on arm_arch5e is now gated on arm_arch5te.
A path in TARGET_OS_CPP_BUILTINS for VxWorks is now unreachable and
therefore is deleted.
References to armv5 and armv5e are deleted/updated throughout the
source tree and testsuite.
Bootstrapped and tested on arm-none-linux-gnueabihf.
Also built a cc1 for arm-wrs-vxworks as a sanity check.
* config/arm/arm-cpus.in (armv5, armv5e): Delete features.
(armv5t, armv5te): New features.
(ARMv5, ARMv5e): Delete fgroups.
(ARMv5t, ARMv5te): Adjust for above changes.
(ARMv6m): Likewise.
(armv5, armv5e): Delete arches.
* config/arm/arm.md (*call_reg_armv5): Use arm_arch5t instead of
arm_arch5.
(*call_reg_arm): Likewise.
(*call_value_reg_armv5): Likewise.
(*call_value_reg_arm): Likewise.
(*call_symbol): Likewise.
(*call_value_symbol): Likewise.
(*sibcall_insn): Likewise.
(*sibcall_value_insn): Likewise.
(clzsi2): Likewise.
(prefetch): Likewise.
(define_split and define_peephole2 dependent on arm_arch5):
Likewise.
* config/arm/arm.h (TARGET_LDRD): Use arm_arch5te instead of
arm_arch5e.
(TARGET_ARM_QBIT): Likewise.
(TARGET_DSP_MULTIPLY): Likewise.
(enum base_architecture): Delete BASE_ARCH_5, BASE_ARCH_5E.
(arm_arch5, arm_arch5e): Delete.
(arm_arch5t, arm_arch5te): Declare.
* config/arm/arm.c (arm_arch5, arm_arch5e): Delete.
(arm_arch5t): Declare.
(arm_option_reconfigure_globals): Update for the above.
(arm_options_perform_arch_sanity_checks): Update comment, replace
use of arm_arch5 with arm_arch5t.
(use_return_insn): Likewise.
(arm_emit_call_insn): Likewise.
(output_return_instruction): Likewise.
(arm_final_prescan_insn): Likewise.
(arm_coproc_builtin_available): Likewise.
* config/arm/arm-c.c (arm_cpu_builtins): Replace arm_arch5 and
arm_arch5e with arm_arch5t and arm_arch5te.
* config/arm/arm-protos.h (arm_arch5, arm_arch5e): Delete.
(arm_arch5t, arm_arch5te): Declare.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/t-arm-elf: Remove references to armv5, armv5e.
* config/arm/t-multilib: Likewise.
* config/arm/thumb1.md (*call_reg_thumb1_v5): Check arm_arch5t
instead of arm_arch5.
(*call_reg_thumb1): Likewise.
(*call_value_reg_thumb1_v5): Likewise.
(*call_value_reg_thumb1): Likewise.
* config/arm/vxworks.h (TARGET_OS_CPP_BUILTINS): Remove now
unreachable path.
* doc/invoke.texi (ARM Options): Remove references to armv5, armv5e.
* gcc.target/arm/pr40887.c: Update comment.
* lib/target-supports.exp: Don't generate effective target checks
and related helpers for armv5. Update comment.
* gcc.target/arm/armv5_thumb_isa.c: Delete.
* gcc.target/arm/di-longlong64-sync-withhelpers.c: Update effective
target check and options.
* config/arm/libunwind.S: Update comment relating to armv5.
From-SVN: r260362
2018-05-18 Martin Liska <mliska@suse.cz>
PR gcov-profile/84846
* gcov.c (print_usage): Add new -t option.
(process_args): Handle the option.
(generate_results): Use stdout as output when requested by
the option.
2018-05-18 Martin Liska <mliska@suse.cz>
PR gcov-profile/84846
* doc/gcov.texi: Document -t option of gcov tool.
From-SVN: r260361
2018-05-18 Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org>
PR middle-end/85817
* ipa-pure-const.c (malloc_candidate_p): Remove the check integer_zerop
for retval and return false if all args to phi are zero.
testsuite/
* gcc.dg/tree-ssa/pr83648.c: Change scan-tree-dump to
scan-tree-dump-not for h.
From-SVN: r260358
2018-05-18 Toon Moene <toon@moene.org>
* doc/invoke.texi: Move -floop-unroll-and-jam documentation
directly after that of -floop-interchange. Indicate that both
options are enabled by default when specifying -O3.
From-SVN: r260352
We've a deficiency in our vec_set family of patterns.
We don't support directly loading a vector lane using LD1 for V2DImode and all the vector floating-point modes.
We do do it correctly for the other integer vector modes (V4SI, V8HI etc) though.
The alternatives on the relative floating-point patterns only allow a register-to-register INS instruction.
That means if we want to load a value into a vector lane we must first load it into a scalar register and then
perform an INS, which is wasteful.
There is also an explicit V2DI vec_set expander dangling around for no reason that I can see. It seems to do the
exact same things as the other vec_set expanders. This patch removes that.
It now unifies all vec_set expansions into a single "vec_set<mode>" define_expand using the catch-all VALL_F16 iterator.
With this patch we avoid loading values into scalar registers and then doing an explicit INS on them to move them into
the desired vector lanes. For example for:
typedef float v4sf __attribute__ ((vector_size (16)));
typedef long long v2di __attribute__ ((vector_size (16)));
v2di
foo_v2di (long long *a, long long *b)
{
v2di res = { *a, *b };
return res;
}
v4sf
foo_v4sf (float *a, float *b, float *c, float *d)
{
v4sf res = { *a, *b, *c, *d };
return res;
}
we currently generate:
foo_v2di:
ldr d0, [x0]
ldr x0, [x1]
ins v0.d[1], x0
ret
foo_v4sf:
ldr s0, [x0]
ldr s3, [x1]
ldr s2, [x2]
ldr s1, [x3]
ins v0.s[1], v3.s[0]
ins v0.s[2], v2.s[0]
ins v0.s[3], v1.s[0]
ret
but with this patch we generate the much cleaner:
foo_v2di:
ldr d0, [x0]
ld1 {v0.d}[1], [x1]
ret
foo_v4sf:
ldr s0, [x0]
ld1 {v0.s}[1], [x1]
ld1 {v0.s}[2], [x2]
ld1 {v0.s}[3], [x3]
ret
* config/aarch64/aarch64-simd.md (vec_set<mode>): Use VALL_F16 mode
iterator. Delete separate integer-mode vec_set<mode> expander.
(aarch64_simd_vec_setv2di): Delete.
(vec_setv2di): Delete.
(aarch64_simd_vec_set<mode>): Delete all other patterns with that name.
Use VALL_F16 mode iterator. Add LD1 alternative and use vwcore for
the "w, r" alternative.
* gcc.target/aarch64/vect-init-ld1.c: New test.
From-SVN: r260351
2018-05-18 Martin Liska <mliska@suse.cz>
* passes.def: Add pass_lower_switch and pass_lower_switch_O0.
* tree-pass.h (make_pass_lower_switch_O0): New function.
* tree-switch-conversion.c (node_has_low_bound): Remove.
(node_has_high_bound): Likewise.
(node_is_bounded): Likewise.
(class pass_lower_switch): Make it a template type and create
two instances.
(pass_lower_switch::execute): Add template argument.
(make_pass_lower_switch): New function.
(make_pass_lower_switch_O0): New function.
(do_jump_if_equal): Remove.
(emit_case_nodes): Simplify to just handle all 3 cases and leave
all the hard work to tree optimization passes.
2018-05-18 Martin Liska <mliska@suse.cz>
* gcc.dg/tree-ssa/vrp104.c: Adjust dump file that is scanned.
* gcc.dg/tree-prof/update-loopch.c: Likewise.
From-SVN: r260350
