2019-01-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/88929
* trans-array.c (gfc_conv_descriptor_elem_len): New function.
* trans-array.h : Add prototype for above.
* trans-expr.c (gfc_conv_gfc_desc_to_cfi_desc): Take account of
assumed rank arrays being flagged by rank = -1 in expressions.
Intent in arrays need a pointer to a copy of the data to be
assigned to the descriptor passed for conversion. This should
then be freed, together with the CFI descriptor on return from
the C call.
2019-01-24 Paul Thomas <pault@gcc.gnu.org>
PR fortran/88929
* gfortran.dg/ISO_Fortran_binding_3.f90 : New test
* gfortran.dg/ISO_Fortran_binding_3.c : Subsidiary source.
From-SVN: r268231
Precise stack scan uses SIGURG to trigger a stack scan. We need
to have Go signal handler installed for SIGURG.
Reviewed-on: https://go-review.googlesource.com/c/159097
From-SVN: r268230
ChangeLog
2019-01-24 Xiong Hu Luo <luoxhu@linux.vnet.ibm.com>
* ChangeLog: replace space with tab.
* MAINTAINERS: delete 1 tab to keep alignment.
From-SVN: r268228
2019-01-23 Bin Cheng <bin.cheng@arm.com>
Steve Ellcey <sellcey@marvell.com>
PR target/85711
* recog.c (address_operand): Return false on wrong mode for address.
(constrain_operands): Check for mode with 'p' constraint.
Co-Authored-By: Steve Ellcey <sellcey@marvell.com>
From-SVN: r268219
FSTYPE FUNC (DWtype u) in libgcc2.c, which converts DI/TI to SF/DF, has
/* No leading bits means u == minimum. */
if (count == 0)
return -(Wtype_MAXp1_F * (Wtype_MAXp1_F / 2));
in the third case (where actually count == 0 only means the high part is
minimum). It should be:
/* No leading bits means u == minimum. */
if (count == 0)
return Wtype_MAXp1_F * (FSTYPE) (hi | ((UWtype) u != 0));
instead.
gcc/testsuite/
2019-01-23 H.J. Lu <hongjiu.lu@intel.com>
PR libgcc/88931
* gcc.dg/torture/fp-int-convert-timode-1.c: New test.
* gcc.dg/torture/fp-int-convert-timode-2.c: Likewise.
* gcc.dg/torture/fp-int-convert-timode-3.c: Likewise.
* gcc.dg/torture/fp-int-convert-timode-4.c: Likewise.
libgcc/
2019-01-23 Joseph Myers <joseph@codesourcery.com>
PR libgcc/88931
* libgcc2.c (FSTYPE FUNC (DWtype u)): Correct no leading bits
case.
From-SVN: r268216
* parser.c (cp_parser_direct_declarator): don't treat qualified-ids
in parameter-list as types if name lookup for declarator-id didn't
find one or more function templates.
* g++.dg/cpp0x/dependent2.c: new test.
* g++.dg/cpp2a/typename10.c: remove dg-error.
* g++.dg/cpp2a/typename12.c: new test.
* g++.dg/template/static30.c: remove dg-error.
From-SVN: r268192
Running:
$ valgrind ./xgcc -B. -c test.c -march=native
on aarch64 shows a use-after-free in host_detect_local_cpu due
to the std::string result of aarch64_get_extension_string_for_isa_flags
only living until immediately after a c_str call.
This leads to corrupt "-march=" values being passed to cc1.
This patch fixes the use-after-free, though it appears to also need
Tamar's patch here:
https://gcc.gnu.org/ml/gcc-patches/2018-12/msg01302.html
in order to generate valid values for cc1. This may have worked by
accident in the past, if the corrupt "-march=" value happened to be
0-terminated in the "right" place; with this patch it now appears
to reliably break without Tamar's patch.
gcc/ChangeLog:
PR driver/89014
* config/aarch64/driver-aarch64.c (host_detect_local_cpu): Fix
use-after-free of the result of
aarch64_get_extension_string_for_isa_flags.
From-SVN: r268189
PR c/44715
* cp-gimplify.c (genericize_cp_loop): Call begin_bc_block only
after genericizing cond and incr expressions.
* doc/extend.texi: Document break and continue behavior in
statement expressions.
* c-c++-common/pr44715.c: New test.
From-SVN: r268188
2019-01-23 Richard Biener <rguenther@suse.de>
PR tree-optimization/89008
* tree-ssa-reassoc.c (eliminate_using_constants): For * 0 do
not leave another stray operand.
* gcc.dg/torture/pr89008.c: New testcase.
From-SVN: r268186
* cgraphunit.c (cgraph_node::expand_thunk): When expanding a GIMPLE
thunk that returns by reference, use the type of the return object
of the thunk instead of that of the alias to build the dereference.
From-SVN: r268182
Atomics use DMB instruction to enforce ordering of loads/stores.
Currently gcc generates DMB w/o any arg which is a no-op. Fix that by
generating DMB 3 which enforces R+W ordering. It is stricter than what
acq/rel expect, but there's no other way.
gcc/
2019-xx-xx Vineet Gupta <vgupta@synopsys.com>
* config/arc/atomic.md: Add operand to DMB instruction
From-SVN: r268181
2019-01-23 Tom de Vries <tdevries@suse.de>
* dwarf.c (struct unit): Use size_t for low_offset/high_offset fields.
(units_search, find_unit): Use size_t for offset.
(build_address_map): Use size_t for unit_offset.
From-SVN: r268180
PR tree-optimization/88964
* gimple-loop-interchange.cc (loop_cand::analyze_induction_var): Use
build_zero_cst instead of build_int_cst. Return false for loop
invariants which honor signed zeros.
* gfortran.dg/pr88964.f90: New test.
From-SVN: r268179
Consider test-case:
...
int
main (void)
{
#pragma acc parallel async
;
#pragma acc parallel async
;
#pragma acc wait
return 0;
}
...
This fails with:
...
libgomp: cuMemAlloc error: invalid argument
Segmentation fault (core dumped)
...
The cuMemAlloc error is due to the fact that we're try to allocate 0 bytes.
Fix this by preventing calling map_push with size zero argument in nvptx_exec.
This also has the consequence that for the abort-1.c test-case, we end up
calling cuMemFree during map_fini for the struct cuda_map allocated in
map_init, which fails because an abort happened. Fix this by calling
cuMemFree with CUDA_CALL_NOCHECK in cuda_map_destroy.
2019-01-23 Tom de Vries <tdevries@suse.de>
PR target/PR88946
* plugin/plugin-nvptx.c (cuda_map_destroy): Use CUDA_CALL_NOCHECK for
cuMemFree.
(nvptx_exec): Don't call map_push if mapnum == 0.
* testsuite/libgomp.oacc-c-c++-common/pr88946.c: New test.
From-SVN: r268178
There are currently two situations where this assert triggers:
...
libgomp/plugin/plugin-nvptx.c: map_fini: Assertion `!s->map->active' failed.
...
First, in abort-1.c, a parallel region triggering an abort:
...
int
main (void)
{
#pragma acc parallel
abort ();
return 0;
}
...
The abort is detected in nvptx_exec as the CUDA_ERROR_ILLEGAL_INSTRUCTION
return status of the cuStreamSynchronize call after kernel launch, which is
then handled by calling non-returning function GOMP_PLUGIN_fatal.
Consequently, the map_pop in nvptx_exec that in case of cuStreamSynchronize
success would remove or inactive the element added by the map_push earlier in
nvptx_exec, does not trigger. With the element no longer active, but still
marked active and a member of s->map, we run into the assert during
GOMP_OFFLOAD_fini_device, which is triggered from atexit handler
gomp_target_fini (which is triggered by the GOMP_PLUGIN_fatal mentioned above
calling exit).
Second, in pr88941.c, an async parallel region without wait:
...
int
main (void)
{
#pragma acc parallel async
;
/* no #pragma acc wait */
return 0;
}
...
Because nvptx_exec is handling an async region, it does not call map_pop for
the element added by map_push, but schedules an kernel execution completion
event to call map_pop. Again, we run into the assert during
GOMP_OFFLOAD_fini_device, which is triggered from atexit handler
gomp_target_fini, but the exit in this case is triggered by returning from main.
So either the kernel is still running, or the kernel has completed but the
corresponding event that is supposed to call map_pop is stuck in the event
queue, waiting for an event_gc.
Fix this by removing the assert, and skipping the freeing of device memory if
the map is still marked active (though in the async case, this is more a
workaround than an fix).
2019-01-23 Tom de Vries <tdevries@suse.de>
PR target/88941
PR target/88939
* plugin/plugin-nvptx.c (cuda_map_destroy): Handle map->active case.
(map_fini): Remove "assert (!s->map->active)".
* testsuite/libgomp.oacc-c-c++-common/pr88941.c: New test.
From-SVN: r268177
The map field of a struct ptx_stream is a FIFO. The FIFO is implemented as a
single linked list, with pop-from-the-front semantics.
The function map_pop pops an element, either by:
- deallocating the element, if there is more than one element
- or marking the element inactive, if there's only one element
The responsibility of map_push is to push an element to the back, as well as
selecting the element to push, by:
- allocating an element, or
- reusing the element at the front if inactive and big enough, or
- dropping the element at the front if inactive and not big enough, and
allocating one that's big enough
The current implemention gets at least the first and most basic scenario wrong:
> map = cuda_map_create (size);
We create an element, and assign it to map.
> for (t = s->map; t->next != NULL; t = t->next)
> ;
We determine the last element in the fifo.
> t->next = map;
We append the new element.
> s->map = map;
But here, we throw away the rest of the FIFO, and declare the FIFO to be just
the new element.
This problem causes the test-case asyncwait-1.c to fail intermittently on some
systems. The pr87835.c test-case added here is a a minimized and modified
version of asyncwait-1.c (avoiding the kernel construct) that is more likely to
fail.
Fix this by rewriting map_pop more robustly, by:
- seperating the function in two phases: select element, push element
- when reusing or dropping an element, making sure that the element is cleanly
popped from the queue
- rewriting the push element part in such a way that it can handle all cases
without needing if statements, such that each line is exercised for each of
the three cases.
2019-01-23 Tom de Vries <tdevries@suse.de>
PR target/87835
* plugin/plugin-nvptx.c (map_push): Fix adding of allocated element.
* testsuite/libgomp.oacc-c-c++-common/pr87835.c: New test.
From-SVN: r268176
gcc/testsuite/ChangeLog:
* c-c++-common/Warray-bounds-2.c: Include headers only if they exist.
* c-c++-common/Warray-bounds-3.c: Make xfails conditional on target
non_strict_align.
* c-c++-common/Wrestrict-2.c: Include headers only if they exist.
* c-c++-common/Wrestrict.c: Make xfails conditional on target
non_strict_align.
From-SVN: r268175
It is enabled at -O3, but the doc currently says -O2. This fixes it.
* doc/invoke.texi (-fsplit-paths): This is enabled by default at -O3.
From-SVN: r268170
PR target/88965
* config/rs6000/rs6000.c: Include tree-vrp.h and tree-ssanames.h.
(rs6000_gimple_fold_builtin): If MEM_REF address doesn't satisfy
is_gimple_mem_ref_addr predicate, force it into a SSA_NAME first.
* gcc.target/powerpc/pr88965.c: New test.
From-SVN: r268166
PR middle-end/88968
* gimplify.c (gimplify_omp_atomic): Handle bitfield atomics with
non-integral DECL_BIT_FIELD_REPRESENTATIVEs.
* c-omp.c (c_finish_omp_atomic): For bitfield atomics, update type
variable after using BIT_FIELD_REF.
* c-c++-common/gomp/atomic-23.c: New test.
From-SVN: r268165
A bitfield that is exactly the same size as an integral type and
naturally aligned will have DECL_BIT_FIELD cleared. So we need to
check DECL_BIT_FIELD_TYPE to be sure whether or not the underlying
type was declared with a bitfield declaration.
I've also added a test for bitfields that are based on overaligned types.
PR target/88469
gcc:
* config/arm/arm.c (arm_needs_double_word_align): Check
DECL_BIT_FIELD_TYPE.
gcc/testsuite:
* gcc.target/arm/aapcs/bitfield2.c: New test.
* gcc.target/arm/aapcs/bitfield3.c: New test.
From-SVN: r268160
Fix a failing test - changes in Combine mean the test now fails
eventhough the generated code is the same. Given there are several
AArch64-specific tests for vec-select, remove the scanning of Combine
output. Committed as trivial fix.
testsuite/
PR rtl-optimization/87763
* gcc.dg/vect/vect-nop-move.c: Fix testcase on AArch64.
From-SVN: r268159
There are
struct builtin_description
{
const HOST_WIDE_INT mask;
const enum insn_code icode;
const char *const name;
const enum ix86_builtins code;
const enum rtx_code comparison;
const int flag;
};
Since "mask" is used for both ix86_isa_flags and ix86_isa_flags2, buitins
with both flags can't be handled easily. This patch adds mask2 to
builtin_description to handle it properly.
2019-01-22 Hongtao Liu <hongtao.liu@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
PR target/88909
* config/i386/i386-builtin.def: Add mask2 to all builtin
initializations. Merge ARGS2 and SPECIAL_ARGS2 into ARGS and
SPECIAL_ARGS.
* config/i386/i386.c (BDESC): Add mask2 to the definition.
(BDESC_FIRST): Likewise.
(define_builtin): Add an argument for mask2. Updated to handle
both ix86_isa_flags and ix86_isa_flags2.
(define_builtin_const): Likewise.
(define_builtin_pure): Likewise.
(define_builtin2): Deleted.
(define_builtin_const2): Likewise.
(builtin_description): Add a member, mask2.
(bdesc_*): Add mask2 to builtin initializations.
(ix86_init_mmx_sse_builtins): Update calls to def_builtin,
def_builtin_const and def_builtin_pure. Remove SPECIAL_ARGS2
support.
(ix86_get_builtin_func_type): Remove SPECIAL_ARGS2 support.
Co-Authored-By: H.J. Lu <hongjiu.lu@intel.com>
From-SVN: r268155
For the gofrontend copy, change calls to types.SizesFor to pass
"gccgo" rather than "gc". Leave the asmdecl pass unchanged since that
pass is gc-specific anyhow.
This has been fixed in a better way in the external repo by
https://golang.org/cl/158317 and friends, but that is not in 1.12, so
use this approach for now.
Reviewed-on: https://go-review.googlesource.com/c/158842
From-SVN: r268153
With noplt attribute, we load the external function address via the GOT
slot so that linker won't create an PLT entry for extern function address.
gcc/
PR target/88954
* config/i386/i386.c (ix86_force_load_from_GOT_p): Also check
noplt attribute.
gcc/testsuite/
PR target/88954
* gcc.target/i386/pr88954-1.c: New test.
* gcc.target/i386/pr88954-2.c: Likewise.
From-SVN: r268152
Unfortunately another PCS bug has come to light with the layout of
structs whose alignment is dominated by a 64-bit bitfield element.
Such fields in the type list appear to have alignment 1, but in
reality, for the purposes of alignment of the underlying structure,
the alignment is derived from the underlying bitfield's type. We've
been getting this wrong since support for over-aligned record types
was added several releases back. Worse still, the existing code may
generate unaligned memory accesses that may fault on some versions of
the architecture.
I've taken the opportunity to add a few more tests that check the
passing arguments with overalignment in the PCS. Looking through the
existing tests it looked like they were really only checking
self-consistency and not the precise location of the arguments.
PR target/88469
gcc:
* config/arm/arm.c (arm_needs_doubleword_align): Return 2 if a record's
alignment is dominated by a bitfield with 64-bit aligned base type.
(arm_function_arg): Emit a warning if the alignment has changed since
earlier GCC releases.
(arm_function_arg_boundary): Likewise.
(arm_setup_incoming_varargs): Likewise.
gcc/testsuite:
* gcc.target/arm/aapcs/bitfield1.c: New test.
* gcc.target/arm/aapcs/overalign_rec1.c: New test.
* gcc.target/arm/aapcs/overalign_rec2.c: New test.
* gcc.target/arm/aapcs/overalign_rec3.c: New test.
From-SVN: r268151
* config/sparc/sparc.c (parc_delegitimize_address): Recognize the GOT
register and decoded HIGH/LO_SUM combinations for labels in PIC mode.
From-SVN: r268145
PR tree-optimization/88044
* tree-ssa-loop-niter.c (number_of_iterations_cond): If condition
is false in the first iteration, but !every_iteration, return false
instead of true with niter->niter zero.
From-SVN: r268143
