AIX symbol references can refer to either the symbol (a label) or a
symbol with a qualifier (the storage mapping class). The storage mapping
class provide information about the underlying COFF section into which the
symbol will be placed, e.g. [RO] for read-only in the text section,
[RW] for read-writer in the data section, or [BS] for the BSS section.
A label is distinct from a qualname in the assembler language, e.g.,
foo and foo[RW] are different, but the symbol table of an object file strips
the storage mapping class from the name, so that it no longer is relevant
when referring to symbols across object files and libraries.
.csect .data[RW]
i:
is a label "i" in the .data CSECT, which has storage mapping class [RW]
so that it is placed in the read-write COFF section.
.csect i[RW]
is a CSECT "i[RW]". BSS does not allow interior labels.
The AIX port of GCC had been emitting the storage mapping class where
appropriate but not consistently using the storage mapping class on
the DECL or SYM name. This patch updates the section encoding to properly
place storage mapping class on symbol names and remove the decorations
placed when emitting the symbol.
The mapping classes correspond to sections and the encoding choices must
exactly match the section choices made by get_section, so the logic for
the computation of reloc in get_variable_section is split into its own
function that XCOFF encode section info can call.
gcc/ChangeLog:
* varasm.c (compute_reloc_for_var): Split out from...
(get_variable_section): Use it.
* output.h (compute_reloc_for_var): Declare.
* config/rs6000/rs6000-protos.h
(rs6000_xcoff_asm_output_aligned_decl_common): Change alignment to
unsigned int.
* config/rs6000/rs6000.c (rs6000_legitimize_tls_address_aix):
Don't append storage mapping class to symbol.
(rs6000_xcoff_asm_named_section): Add BS and UL mapping classes.
Don't convert TLS BSS to common.
(rs6000_xcoff_unique_section): Don't fall back to select_secton.
(rs6000_xcoff_section_type_flags): Add SECTION_BSS if DECL is
bss_initializer.
(rs6000_xcoff_asm_globalize_decl_name): Don't strip storage
mapping class.
(rs6000_xcoff_asm_output_aligned_decl_common): Align is unsigned int.
If align is 0 from TLS class, use the same rules as varasm.c
If not common, switch to BSS section manually.
If common, emit appropriate comm or lcomm directive.
(rs6000_xcoff_encode_section_info): Add logic to append all
storage mapping classes.
(rs6000_asm_weaken_decl): Adjust for qualname symbols.
* config/rs6000/xcoff.h (ASM_OUTPUT_ALIGNED_DECL_LOCAL): Use
rs6000_xcoff_asm_output_aligned_decl_common.
(ASM_OUTPUT_ALIGNED_DECL_LOCAL): Use
rs6000_xcoff_asm_output_aligned_decl_common.
(ASM_OUTPUT_TLS_COMMON): Use
rs6000_xcoff_asm_output_aligned_decl_common.
gcc/testsuite/ChangeLog:
* g++.dg/ext/visibility/fvisibility-inlines-hidden-4.C: Expect [BS]
mapping class on AIX.
* gcc.c-torture/compile/pr61159.c: XFAIL on AIX.
* gcc.c-torture/execute/alias-2.c: Same.
* gcc.dg/alias-7.c: Same.
Follow up to PR100352, which moved unit unlocking to st_*_done_worker to
avoid lock order reversal; however, as async_io uses a different lock,
the (unlocked locked) unit lock shall not be unlocked there.
libgfortran/ChangeLog:
PR libgomp/100352
* io/transfer.c (st_read_done_worker, st_write_done_worker): Add new
arg whether to unlock unit.
(st_read_done, st_write_done): Call it with true.
* io/async.c (async_io): Call it with false.
* io/io.h (st_write_done_worker, st_read_done_worker): Update prototype.
The r12-220-gd96db15967e78d7cecea3b1cf3169ceb924678ac change
deprecated some non-standard std::pair constructors and that apparently
broke nvptx.c build, where pseudo_node_t is std::pair<struct basic_block_def *, int>
and so nullptr (or NULL) needs to be used for the first argument of the
ctors instead of 0.
2021-05-02 Jakub Jelinek <jakub@redhat.com>
PR target/100375
* config/nvptx/nvptx.c (nvptx_sese_pseudo): Use nullptr instead of 0
as first argument of pseudo_node_t constructors.
The recent addition of i386-isa.def which is included from i386.h results
in failures to build gcc plugins, the i386.h header is installed, but
i386-isa.def is not.
2021-05-02 Jakub Jelinek <jakub@redhat.com>
PR target/100336
* config/i386/t-i386 (TM_H): Add $(srcdir)/config/i386/i386-isa.def.
We can't use C++11 range-based 'for' over a tree directly, because we don't
know what kind of range we want to use it as. I suppose in some cases we
could guess, but it seems better to tersely make it explicit. This patch
adds range adaptors ovl_range and lkp_range for use as the range of a
range-for, e.g.
for (tree fn : lkp_range (fns)) { ... }
This patch also removes the private copy ops from ovl_iterator; it's
necessary for range-for, and these are effectively C++ forward_iterators,
which allow copying, so I don't see a reason to prevent it. A bit more
would need to be done to make them actually conform as C++11 forward
iterators, but I don't think we particularly want to #include <iterator>
yet.
gcc/cp/ChangeLog:
* cp-tree.h (class ovl_iterator): Allow copying. Add op==.
(class ovl_range, class lkp_range): New.
* call.c (build_op_call_1, add_candidates): Use them.
(build_op_delete_call, has_trivial_copy_assign_p): Likewise.
(has_trivial_copy_p): Likewise.
* class.c (handle_using_decl, get_basefndecls): Likewise.
(maybe_warn_about_overly_private_class): Likewise.
(warn_hidden, add_implicitly_declared_members): Likewise.
(check_methods, clone_constructors_and_destructors): Likewise.
(type_has_user_nondefault_constructor): Likewise.
Right now we have GTY support for static storage iranges
(int_range<>). However, there's no reason why the base
class can't be used with GC, other than it was an oversight.
For that matter, the base class has a pointer to the sub-range
storage, so we can use the same implementation for both. This
patch does so.
I have also removed the DEFINE_INT_RANGE_GC_STUBS
stuff, and have documented why we need a separate
gt_pch_nx (int_range<1> *&) version. This has to do with
hash-traits.h, which ipa-prop.c is using to store a value_range.
The header file hash-traits.h is defining an extern of
gt_pch_nx (int_range<1> *&) etc, instead of calling the
more generic (int_range<1> *) which is already available.
It seems suspect that has-traits.h has their own externs
for GC functions, and if someone has a better solution, I'd
be glad to hear it.
gcc/ChangeLog:
* value-range.cc (DEFINE_INT_RANGE_GC_STUBS): Remove.
(gt_pch_nx (int_range<1> *&)): New.
(gt_ggc_mx (int_range<1> *&)): New.
* value-range.h (class irange): Add GTY support for
the base class.
This implements the wording changes of P2328R0 "join_view should join
all views of ranges".
libstdc++-v3/ChangeLog:
* include/std/ranges (__detail::__non_propating_cache): Define
as per P2328.
(join_view): Remove constraints on the value and reference types
of the wrapped iterator type as per P2328.
(join_view::_Iterator::_M_satisfy): Adjust as per P2328.
(join_view::_Iterator::operator++): Likewise.
(join_view::_M_inner): Use __non_propating_cache as per P2328.
Remove now-redundant use of __maybe_present_t.
* testsuite/std/ranges/adaptors/join.cc: Include <array>.
(test10): New test.
The __cpp_lib_constexpr_string and __cpp_lib_semaphore feature test
macros are not defined consistently in <version> and the relevant header
for the feature.
libstdc++-v3/ChangeLog:
* include/bits/basic_string.h (__cpp_lib_constexpr_string):
Only define for C++17 and later.
* include/std/version (__cpp_lib_semaphore): Fix condition
to match the one in <semaphore>.
This simplifies the definition of std::streamoff by using the predefined
__INT64_TYPE__ macro, instead of the _GLIBCXX_HAVE_INT64_T_LONG,
_GLIBCXX_HAVE_INT64_T_LONG_LONG and _GLIBCXX_HAVE_INT64_T macros defined
by configure.
By using the __INT64_TYPE__ macro (which all of GCC, Clang and Intel
define) we do not need to determine the type of int64_t in configure, we
can just use that type directly.
The background for the change was explained by David Edelsohn:
Currently the type of streamoff is determined at libstdc++ configure
time, chosen by the definitions of _GLIBCXX_HAVE_INT64_T_LONG and
_GLIBCXX_HAVE_INT64_T_LONG_LONG. For a multilib configuration, the
difference is encoded in the different multilib header file paths.
For "FAT" library targets that package 32 bit and 64 bit libraries
together, G++ also expects a single header file directory hierarchy,
causing an incorrect value for streamoff in some situations.
And in a subsequent mail:
Most of the libstdc++ headers are architecture-neutral, OS neutral and
ABI neutral. The differences are localized in bits/c++config.h. And
most of c++config.h is identical for 32 bit AIX and 64 bit AIX. The
only differences that matter are __int128 and __int64_t.
This change removes some of those differences. With the only uses of the
INT64_T configure macros removed, the configure checks themselves can
also be removed.
Co-authored-by: David Edelsohn <dje.gcc@gmail.com>
libstdc++-v3/ChangeLog:
* acinclude.m4 (GLIBCXX_CHECK_INT64_T): Delete.
* config.h.in: Regenerate.
* configure: Regenerate.
* configure.ac: Do not use GLIBCXX_CHECK_INT64_T.
* include/bits/postypes.h: Remove include of <stdint.h> and
definition/undefinition of the __STDC_LIMIT_MACROS and
__STDC_CONSTANT_MACROS macros.
(streamoff): Use __INT64_TYPE__ if defined.
Add compilation tests to make sure that the output of vmla/vmls
floating-point Neon intrinsics (fmul, fadd/fsub) is not fused into
fmla/fmls instructions.
gcc/testsuite/ChangeLog:
2021-02-16 Jonathan Wright <jonathan.wright@arm.com>
* gcc.target/aarch64/advsimd-intrinsics/vmla_float_not_fused.c:
New test.
* gcc.target/aarch64/advsimd-intrinsics/vmls_float_not_fused.c:
New test.
Rewrite floating-point vml[as][q]_laneq Neon intrinsics to use RTL
builtins rather than relying on the GCC vector extensions. Using RTL
builtins allows control over the emission of fmla/fmls instructions
(which we don't want here.)
With this commit, the code generated by these intrinsics changes from
a fused multiply-add/subtract instruction to an fmul followed by an
fadd/fsub instruction. If the programmer really wants fmla/fmls
instructions, they can use the vfm[as] intrinsics.
gcc/ChangeLog:
2021-02-17 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add
float_ml[as][q]_laneq builtin generator macros.
* config/aarch64/aarch64-simd.md (mul_laneq<mode>3): Define.
(aarch64_float_mla_laneq<mode>): Define.
(aarch64_float_mls_laneq<mode>): Define.
* config/aarch64/arm_neon.h (vmla_laneq_f32): Use RTL builtin
instead of GCC vector extensions.
(vmlaq_laneq_f32): Likewise.
(vmls_laneq_f32): Likewise.
(vmlsq_laneq_f32): Likewise.
Rewrite floating-point vml[as][q]_lane Neon intrinsics to use RTL
builtins rather than relying on the GCC vector extensions. Using RTL
builtins allows control over the emission of fmla/fmls instructions
(which we don't want here.)
With this commit, the code generated by these intrinsics changes from
a fused multiply-add/subtract instruction to an fmul followed by an
fadd/fsub instruction. If the programmer really wants fmla/fmls
instructions, they can use the vfm[as] intrinsics.
gcc/ChangeLog:
2021-02-16 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add
float_ml[as]_lane builtin generator macros.
* config/aarch64/aarch64-simd.md (*aarch64_mul3_elt<mode>):
Rename to...
(mul_lane<mode>3): This, and re-order arguments.
(aarch64_float_mla_lane<mode>): Define.
(aarch64_float_mls_lane<mode>): Define.
* config/aarch64/arm_neon.h (vmla_lane_f32): Use RTL builtin
instead of GCC vector extensions.
(vmlaq_lane_f32): Likewise.
(vmls_lane_f32): Likewise.
(vmlsq_lane_f32): Likewise.
Rewrite floating-point vml[as][q] Neon intrinsics to use RTL builtins
rather than relying on the GCC vector extensions. Using RTL builtins
allows control over the emission of fmla/fmls instructions (which we
don't want here.)
With this commit, the code generated by these intrinsics changes from
a fused multiply-add/subtract instruction to an fmul followed by an
fadd/fsub instruction. If the programmer really wants fmla/fmls
instructions, they can use the vfm[as] intrinsics.
gcc/ChangeLog:
2021-02-16 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add float_ml[as]
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_float_mla<mode>):
Define.
(aarch64_float_mls<mode>): Define.
* config/aarch64/arm_neon.h (vmla_f32): Use RTL builtin
instead of relying on GCC vector extensions.
(vmla_f64): Likewise.
(vmlaq_f32): Likewise.
(vmlaq_f64): Likewise.
(vmls_f32): Likewise.
(vmls_f64): Likewise.
(vmlsq_f32): Likewise.
(vmlsq_f64): Likewise.
* config/aarch64/iterators.md: Define VDQF_DF mode iterator.
This patch adjusts peepholes to match and generate parallels with
a clobber of REG_CC.
It also sets mov<mode>_insn as the name of the pattern for the split
insn (rather than the define_insn_and_split), so that
avr_2word_insn_p, which looks for CODE_FOR_mov<mode>_insn, works
correctly. This is required for the *cpse.eq peephole to fire, and
also helps generate better code for avr_out_sbxx_branch.
gcc/ChangeLog:
* config/avr/avr.md: Adjust peepholes to match and
generate parallels with clobber of REG_CC.
(mov<mode>_insn): Rename to mov<mode>_insn_split.
(*mov<mode>_insn): Rename to mov<mode>_insn.
-fdata-sections places data symbols into their own, unique, named sections.
-fsection-anchors create an anchor to access neighboring symbols
within a section.
When both are enabled, a separate section anchor is created for each
symbol, which provides no benefit.
This patch updates the common gating function use_blocks_for_decl_p() to
return false if -fdata-sections is enabled.
gcc/ChangeLog:
* varasm.c (use_blocks_for_decl_p): Don't use section anchors
for VAR_DECLs if -fdata-sections enabled.
This patch defines a target hook so that the KFmode constants
(__LIBGCC_KF_MAX__, __LIBGCC_KF_MIN__, and __LIBGCC_KF_EPSILON__) needed to
build _divkc3.c in libgcc are defined. The need for these constants were added
in the April 28th changes to libgcc that added complex division optimizations.
We only define the KFmode constants if IEEE 128-bit floating point is
supported, but long double does not use the IEEE 128-bit format. If long
double uses the IEEE 128-bit format, it will use TFmode and not KFmode.
gcc/
2021-04-30 Michael Meissner <meissner@linux.ibm.com>
PR bootstrap/100327
* config/rs6000/rs6000.c
(TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Define.
(rs6000_libgcc_floating_mode_supported_p): New target hook.
This refactors the registry and the profitability code from the
backwards threader into two separate classes. It cleans up the code,
and makes it easier for alternate implementations to share code.
gcc/ChangeLog:
* tree-ssa-threadbackward.c (class thread_jumps): Split out code
from here...
(class back_threader_registry): ...to here...
(class back_threader_profitability): ...and here...
(thread_jumps::thread_through_all_blocks): Remove argument.
(back_threader_registry::back_threader_registry): New.
(back_threader_registry::~back_threader_registry): New.
(back_threader_registry::thread_through_all_blocks): New.
(thread_jumps::profitable_jump_thread_path): Move from here...
(back_threader_profitability::profitable_path_p): ...to here.
(thread_jumps::find_taken_edge): New.
(thread_jumps::convert_and_register_current_path): Move...
(back_threader_registry::register_path): ...to here.
(thread_jumps::register_jump_thread_path_if_profitable): Move...
(thread_jumps::maybe_register_path): ...to here.
(thread_jumps::handle_phi): Call find_taken_edge and
maybe_register_path.
(thread_jumps::handle_assignment): Same.
(thread_jumps::fsm_find_control_statement_thread_paths): Remove
tree argument to handle_phi and handle_assignment.
(thread_jumps::find_jump_threads_backwards): Set m_name. Remove
set of m_speed_p and m_max_threaded_paths.
(pass_thread_jumps::execute): Remove second argument from
find_jump_threads_backwards.
(pass_early_thread_jumps::execute): Same.
This is an overall refactor of the jump threader, both for the low level
bits in tree-ssa-threadupdate.* and the high level bits in
tree-ssa-threadedge.*.
There should be no functional changes.
Some of the benefits of the refactor are:
a) Eliminates some icky global state (for example the x_vr_values hack).
b) Provides some semblance of an API for the threader.
c) Makes it clearer to see what parts are from the high level
threader, and what parts belong in the low level path registry and
BB threading mechanism.
d) Avoids passing a ton of variables around.
e) Provides for easier sharing with the backward threader.
f) Merged simplify stmt code in VRP and DOM as they were nearly
identical.
This has been bootstrapped and regression tested on x86-64 Linux.
Jeff had also been testing this path as part of his Fedora throughout the
off-season.
gcc/ChangeLog:
* tree-ssa-dom.c (class dom_jump_threader_simplifier): New.
(class dom_opt_dom_walker): Initialize some class variables.
(pass_dominator::execute): Pass evrp_range_analyzer and
dom_jump_threader_simplifier to dom_opt_dom_walker.
Adjust for some functions moving into classes.
(simplify_stmt_for_jump_threading): Adjust and move to...
(jump_threader_simplifier::simplify): ...here.
(dom_opt_dom_walker::before_dom_children): Adjust for
m_evrp_range_analyzer.
(dom_opt_dom_walker::after_dom_children): Remove x_vr_values hack.
(test_for_singularity): Place in dom_opt_dom_walker class.
(dom_opt_dom_walker::optimize_stmt): The argument
evrp_range_analyzer is now a class field.
* tree-ssa-threadbackward.c (class thread_jumps): Add m_registry.
(thread_jumps::thread_through_all_blocks): New.
(thread_jumps::convert_and_register_current_path): Use m_registry.
(pass_thread_jumps::execute): Adjust for thread_through_all_blocks
being in the threader class.
(pass_early_thread_jumps::execute): Same.
* tree-ssa-threadedge.c (threadedge_initialize_values): Move...
(jump_threader::jump_threader): ...here.
(threadedge_finalize_values): Move...
(jump_threader::~jump_threader): ...here.
(jump_threader::remove_jump_threads_including): New.
(jump_threader::thread_through_all_blocks): New.
(record_temporary_equivalences_from_phis): Move...
(jump_threader::record_temporary_equivalences_from_phis): ...here.
(record_temporary_equivalences_from_stmts_at_dest): Move...
(jump_threader::record_temporary_equivalences_from_stmts_at_dest):
Here...
(simplify_control_stmt_condition_1): Move to jump_threader class.
(simplify_control_stmt_condition): Move...
(jump_threader::simplify_control_stmt_condition): ...here.
(thread_around_empty_blocks): Move...
(jump_threader::thread_around_empty_blocks): ...here.
(thread_through_normal_block): Move...
(jump_threader::thread_through_normal_block): ...here.
(thread_across_edge): Move...
(jump_threader::thread_across_edge): ...here.
(thread_outgoing_edges): Move...
(jump_threader::thread_outgoing_edges): ...here.
* tree-ssa-threadedge.h: Move externally facing functings...
(class jump_threader): ...here...
(class jump_threader_simplifier): ...and here.
* tree-ssa-threadupdate.c (struct redirection_data): Remove comment.
(jump_thread_path_allocator::jump_thread_path_allocator): New.
(jump_thread_path_allocator::~jump_thread_path_allocator): New.
(jump_thread_path_allocator::allocate_thread_edge): New.
(jump_thread_path_allocator::allocate_thread_path): New.
(jump_thread_path_registry::jump_thread_path_registry): New.
(jump_thread_path_registry::~jump_thread_path_registry): New.
(jump_thread_path_registry::allocate_thread_edge): New.
(jump_thread_path_registry::allocate_thread_path): New.
(dump_jump_thread_path): Make extern.
(debug (const vec<jump_thread_edge *> &path)): New.
(struct removed_edges): Move to tree-ssa-threadupdate.h.
(struct thread_stats_d): Remove.
(remove_ctrl_stmt_and_useless_edges): Make static.
(lookup_redirection_data): Move...
(jump_thread_path_registry::lookup_redirection_data): ...here.
(ssa_redirect_edges): Make static.
(thread_block_1): Move...
(jump_thread_path_registry::thread_block_1): ...here.
(thread_block): Move...
(jump_thread_path_registry::thread_block): ...here.
(thread_through_loop_header): Move...
(jump_thread_path_registry::thread_through_loop_header): ...here.
(mark_threaded_blocks): Move...
(jump_thread_path_registry::mark_threaded_blocks): ...here.
(debug_path): Move...
(jump_thread_path_registry::debug_path): ...here.
(debug_all_paths): Move...
(jump_thread_path_registry::dump): ..here.
(rewire_first_differing_edge): Move...
(jump_thread_path_registry::rewire_first_differing_edge): ...here.
(adjust_paths_after_duplication): Move...
(jump_thread_path_registry::adjust_paths_after_duplication): ...here.
(duplicate_thread_path): Move...
(jump_thread_path_registry::duplicate_thread_path): ..here.
(remove_jump_threads_including): Move...
(jump_thread_path_registry::remove_jump_threads_including): ...here.
(thread_through_all_blocks): Move to...
(jump_thread_path_registry::thread_through_all_blocks): ...here.
(delete_jump_thread_path): Remove.
(register_jump_thread): Move...
(jump_thread_path_registry::register_jump_thread): ...here.
* tree-ssa-threadupdate.h: Move externally facing functions...
(class jump_thread_path_allocator): ...here...
(class jump_thread_path_registry): ...and here.
(thread_through_all_blocks): Remove.
(struct removed_edges): New.
(register_jump_thread): Remove.
(remove_jump_threads_including): Remove.
(delete_jump_thread_path): Remove.
(remove_ctrl_stmt_and_useless_edges): Remove.
(free_dom_edge_info): New prototype.
* tree-vrp.c: Remove x_vr_values hack.
(class vrp_jump_threader_simplifier): New.
(vrp_jump_threader_simplifier::simplify): New.
(vrp_jump_threader::vrp_jump_threader): Adjust method signature.
Remove m_dummy_cond.
Instantiate m_simplifier and m_threader.
(vrp_jump_threader::thread_through_all_blocks): New.
(vrp_jump_threader::simplify_stmt): Remove.
(vrp_jump_threader::after_dom_children): Do not set m_dummy_cond.
Remove x_vr_values hack.
(execute_vrp): Adjust for thread_through_all_blocks being in a
class.
This implements the wording changes of P2367R0 "Remove misuses of
list-initialization from Clause 24", modulo the parts that depend
on P1739R4 which we don't yet implement (due to LWG 3407).
libstdc++-v3/ChangeLog:
* include/bits/ranges_util.h (subrange::subrange): Avoid
list-initialization in delegating constructor.
* include/std/ranges (single_view): Replace implicit guide
with explicit deduction guide that decays its argument.
(_Single::operator()): Avoid CTAD when constructing the
single_view object.
(_Iota::operator()): Avoid list-initialization.
(__detail::__can_filter_view, _Filter::operator()): Likewise.
(__detail::__can_transform_view, _Transform::operator()): Likewise.
(take_view::begin): Likewise.
(__detail::__can_take_view, _Take::operator()): Likewise.
(__detail::__can_take_while_view, _TakeWhile::operator()): Likewise.
(__detail::__can_drop_view, _Drop::operator()): Likewise.
(__detail::__can_drop_while_view, _DropWhile::operator()): Likewise.
(split_view::split_view): Use views::single when initializing
_M_pattern.
(__detail::__can_split_view, _Split::operator()): Avoid
list-initialization.
(_Counted::operator()): Likewise.
* testsuite/std/ranges/p2367.cc: New test.
This is another small step towards avoiding the problems described in PR
60497, by using std::addressof to avoid ADL, so that we don't require
all template arguments to be complete.
libstdc++-v3/ChangeLog:
PR libstdc++/60497
* include/bits/basic_ios.tcc (basic_ios::copyfmt): use
std::addressof.
* include/bits/basic_string.tcc (basic_string::swap)
(basic_string::assign): Likewise.
* include/bits/deque.tcc (deque::operator=(const deque&)):
Likewise.
* include/bits/stl_tree.h (_Rb_tree::operator=(const * _Rb_tree&)):
Likewise.
* include/bits/vector.tcc (vector::operator=(const vector&)):
Likewise.
This implements the resolution of LWG 1203 so that the constraints for
rvalue stream insertion/extraction are simpler, and the return type is
the original rvalue stream type not its base class.
Signed-off-by: Jonathan Wakely <jwakely@redhat.com>
libstdc++-v3/ChangeLog:
* include/std/istream (operator>>(Istream&&, x&)): Simplify, as
per LWG 1203.
* include/std/ostream (operator<<(Ostream&&, const x&)):
Likewise.
* testsuite/27_io/basic_istream/extractors_character/char/lwg2499_neg.cc:
Adjust dg-error pattern.
* testsuite/27_io/basic_istream/extractors_character/wchar_t/lwg2499_neg.cc:
Likewise.
* testsuite/27_io/basic_istream/extractors_other/char/4.cc: Define
is_extractable trait to replace std::__is_extractable. Make it
work with rvalue streams as well as lvalues, to replace f() and
g() helper functions.
* testsuite/27_io/basic_istream/extractors_other/wchar_t/4.cc:
Likewise.
* testsuite/27_io/basic_ostream/inserters_other/char/6.cc:
Define is_insertable trait to replace std::__is_insertable. Make
it work with rvalue streams as well as lvalues, to replace f()
and g() helper functions.
* testsuite/27_io/basic_ostream/inserters_other/wchar_t/6.cc:
Likewise.
* testsuite/27_io/filesystem/path/io/dr2989.cc: Prune additional
errors from new constraints.
* testsuite/27_io/rvalue_streams-2.cc: Remove PR 80675 checks,
which are no longer expected to compile.
* testsuite/27_io/rvalue_streams.cc: Adjust existing test.
Verify LWG 1203 changes.
This makes the uses of getsockopt and setsockopt in
<experimental/socket> conditional on the availability of <sys/socket.h>.
It also fixes a test to check for <sys/socket.h> instead of <socket.h>.
libstdc++-v3/ChangeLog:
PR libstdc++/100285
* include/experimental/socket (__basic_socket_impl::set_option)
(__basic_socket_impl::get_option) [!_GLIBCXX_HAVE_SYS_SOCKET_H]:
Just set error code.
* testsuite/experimental/net/socket/socket_base.cc: CHeck
for <sys/socket.h> not <socket.h>.
Define a new effective-target keyword so that tests for the Networking
TS <experimental/internet> header can be skipped on targets where none
of it can be usefully defined.
libstdc++-v3/ChangeLog:
PR libstdc++/100180
PR libstdc++/100286
PR libstdc++/100351
* testsuite/experimental/net/internet/address/v4/comparisons.cc:
Use new effective-target keyword.
* testsuite/experimental/net/internet/address/v4/cons.cc:
Likewise.
* testsuite/experimental/net/internet/address/v4/creation.cc:
Likewise.
* testsuite/experimental/net/internet/address/v4/members.cc:
Likewise.
* testsuite/experimental/net/internet/address/v6/members.cc:
Likewise.
* testsuite/experimental/net/internet/resolver/base.cc:
Likewise.
* testsuite/experimental/net/internet/resolver/ops/lookup.cc:
Likewise.
* testsuite/experimental/net/internet/resolver/ops/reverse.cc:
Likewise.
* testsuite/experimental/net/internet/socket/opt.cc:
Likewise.
* testsuite/experimental/net/internet/tcp.cc:
Likewise.
* testsuite/experimental/net/internet/udp.cc:
Likewise.
* testsuite/lib/libstdc++.exp (check_effective_target_net_ts_ip):
New proc to check net_ts_ip et.
When an iterator cannot be expanded, it is helpful to see the expanded
name which is causing problems. It would be better to also print the
current iterator value (which couldn't match), but I couldn't find
how.
2021-04-30 Christophe Lyon <christophe.lyon@linaro.org>
gcc/
* genflags.c (gen_insn): Print failed expansion string.
alignment_for_piecewise_move is called only with MOVE_MAX_PIECES or
STORE_MAX_PIECES, which are the number of bytes at a time that we
can move or store efficiently. We should call mode_for_size without
limit to MAX_FIXED_MODE_SIZE, which is an integer expression for the
size in bits of the largest integer machine mode that should actually
be used, may be smaller than MOVE_MAX_PIECES or STORE_MAX_PIECES, which
may use vector.
* expr.c (alignment_for_piecewise_move): Call mode_for_size
without limit to MAX_FIXED_MODE_SIZE.
Check nullptr return from simplify_gen_subreg. Don't use it if it is
nullptr.
PR middle-end/90773
* builtins.c (builtin_memset_gen_str): Don't use return from
simplify_gen_subreg.
This adds a testcase for a bug that was fixed with the
hybrid SLP detection rewrite.
2021-04-30 Richard Biener <rguenther@suse.de>
PR tree-optimization/96513
* gcc.dg/torture/pr96513.c: New testcase.
The compiler is able to merge LTU comparisons with PLUS or MINUS pattern to
form addition with carry (ADC) and subtraction with borrow (SBB) instructions:
op = op + carry [ADC $0, op]
op = op - carry [SBB $0, op]
The patch introduces reversed ADC and SBB insn patterns:
op = op + !carry [SBB $-1, op]
op = op - !carry [ADC $-1, op]
allowing the compiler to also merge GEU comparisons.
2021-04-30 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/98060
* config/i386/i386.md (*add<mode>3_carry_0r): New insn pattern.
(*addsi3_carry_zext_0r): Ditto.
(*sub<mode>3_carry_0): Ditto.
(*subsi3_carry_zext_0r): Ditto.
* config/i386/predicates.md (ix86_carry_flag_unset_operator):
New predicate.
* config/i386/i386.c (ix86_rtx_costs) <case PLUS, case MINUS>:
Also consider ix86_carry_flag_unset_operator to calculate
the cost of adc/sbb insn.
gcc/testsuite/
PR target/98060
* gcc.target/i386/pr98060.c: New test.
PR84878 fix adds an assertion which can fail, e.g. when stack pointer
is adjusted inside the loop. We have to prevent it and search earlier
for any 'strange' instruction. The solution is to skip the whole loop
if using 'note_stores' we found that one of hard registers is in
'df->regular_block_artificial_uses' set.
Also patch properly prohibit not single-set instruction in loop body.
gcc/ChangeLog:
PR rtl-optimization/100225
PR rtl-optimization/84878
* modulo-sched.c (sms_schedule): Use note_stores to skip loops
where we have an instruction which touches (writes) any hard
register from df->regular_block_artificial_uses set.
Allow not-single-set instruction only right before basic block
tail.
gcc/testsuite/ChangeLog:
PR rtl-optimization/100225
PR rtl-optimization/84878
* gcc.dg/pr100225.c: New test.
libgomp/ChangeLog:
* testsuite/libgomp.oacc-c-c++-common/atomic_capture-3.c: New test.
When use multi-lib riscv-tool-chain. A bug is triggered when there are two
'-march' at command line.
riscv64-unknown-elf-gcc -march=rv32gcp -mabi=ilp32f -march=rv32gcpzp64 HelloWorld.c
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o: ABI is incompatible with that of the selected emulation:
target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/lib/crt0.o
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o: ABI is incompatible with that of the selected emulation:
target emulation `elf64-littleriscv' does not match `elf32-littleriscv'
/lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /lhome/gengq/riscv64-linux-ptest/lib/gcc/riscv64-unknown-elf/10.2.0/crtbegin.o
......
This patch fix it. And the DRIVER would prune the extra '-march' and '-mabi'
options and keep only the last one valid.
gcc/ChangeLog:
* config/riscv/riscv.opt (march=,mabi=): Negative itself.
Uros observed that i[34567]86-*-* and x86_64-*-* cpu_type-setting
target cases were equivalent. I've verified that this was the case,
and combined them.
for gcc/ChangeLog
* config.gcc: Merged x86 and x86_64 cpu_type-setting cases.
In ix86_int_compare, opportunistically swap operands of GTU and LEU comparisons
to emit carry flag comparison, with the expectation that the comparison will
combine to *add<mode>3_carry_0 or *sub<mode>3_carry_0 insn pattern.
Do not use ix86_expand_carry_flag_compare because this function prefers
carry flag comparisons too much - it forces the constants into registers
and/or emits additional arithmetic instructions to convert simple
comparisons into carry flag comparisons - but simply swap operands to
convert GTU and LEU comparisons into GEU and LTU ones.
Also, change the insn predicates of *add<mode>3_carry_0 and
*sub<mode>3_carry_0 insn patterns to allow more combine opportunities
with memory operands.
2021-04-29 Uroš Bizjak <ubizjak@gmail.com>
gcc/
* config/i386/i386-expand.c (ix86_expand_int_compare):
Swap operands of GTU and LEU comparison to emit carry flag comparison.
* config/i386/i386.md (*add<mode>3_carry_0): Change insn
predicate to allow more combine opportunities with memory operands.
(*sub<mode>3_carry_0): Ditto.
As reported in bug 82359, the preprocessor does not allow C++ digit
separators in the line number in a #line directive, despite the
standard syntax for that directive using digit-sequence which allows
digit separators.
There is some confusion in that bug about whether C++ is meant to
allow digit separators there or not, but the last comment there
suggests they are meant to be allowed, and the version of digit
separators accepted for C2X at the March meeting explicitly mentions
digit separators in the #line specification to avoid any ambiguity
there.
This patch thus adds code to handle digit separators in the line
number in #line, as part of the preparation for enabling digit
separators in C2X mode. The code changed does not contain any
conditionals for whether digit separators are supported in the chosen
language version, because that was handled earlier in pp-number lexing
and if they aren't supported they won't appear in the string passed to
that function. It does however make sure not to allow adjacent digit
separators because those are only handled at a later stage of lexing
at present. (Problems with how certain source character sequences
involving digit separators that don't actually match the pp-number
syntax get lexed as a pp-number and only diagnosed later, if at all,
are bugs 83873 and 97604, to be addressed separately.)
Making the change in this location will have the effect of allowing
digit separators in the "# <line-number> <file> <flags>" form of
directive as well as #line; I don't think that's a problem.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
libcpp/
PR preprocessor/82359
* directives.c (strtolinenum): Handle digit separators.
gcc/testsuite/
PR preprocessor/82359
* g++.dg/cpp1y/digit-sep-line.C,
g++.dg/cpp1y/digit-sep-line-neg.C: New tests.
In discussion of PR98463, Jakub noted that cxx_fold_indirect_ref_1 was
bailing out early for empty bases even when we do have fields for them (in
C++17 mode or later). This corrects that.
gcc/cp/ChangeLog:
* constexpr.c (cxx_fold_indirect_ref_1): Only set *empty_base if we
don't find a field.
51344 was a problem with calling save_template_attributes twice for the same
friend function: once from do_friend and once from grokmethod. The 2012
patch for the bug avoided creating an infinite loop when this happens, but
it's better to avoid the duplication in the first place. This also restores
the dependent attributes to the beginning of the attribute list, as
originally intended. And then apply_late_template_attributes can avoid
copying the non-dependent attributes.
gcc/cp/ChangeLog:
PR c++/51344
* decl2.c (grokfield): Call cplus_decl_attributes for friend.
(save_template_attributes): Use chainon.
* friend.c (do_friend): Remove attrlist parm.
* cp-tree.h (do_friend): Adjust.
* class.c (add_implicitly_declared_members): Adjust.
* decl.c (grokdeclarator): Adjust.
* pt.c (apply_late_template_attributes): Optimize.
While working on the GCC 11 patch, it occurred to me that we could move
the errors about invalid members from finish_struct_anon_r to here, so we
properly get a diagnostic in g++.law/union4.C.
gcc/cp/ChangeLog:
PR c++/97974
* class.c (finish_struct_anon_r): Drop complain parm.
Remove non-field diagnostic.
(finish_struct_anon): Adjust.
* decl.c (fixup_anonymous_aggr): Move non-field diagnostic here.
gcc/testsuite/ChangeLog:
PR c++/97974
* g++.old-deja/g++.law/union4.C: Add expected diagnostic.
My GCC 11 patch for PR93314 turned off cp_unevaluated_operand while
processing an id-expression that names a non-static data member, but the
broader issue is that in general, a constant-expression is evaluated even in
an unevaluated operand.
gcc/cp/ChangeLog:
* cp-tree.h (cp_evaluated): Add reset parm to constructor.
* parser.c (cp_parser_constant_expression): Change
allow_non_constant_p to int. Use cp_evaluated.
(cp_parser_initializer_clause): Pass 2 to allow_non_constant_p.
* semantics.c (finish_id_expression_1): Don't mess with
cp_unevaluated_operand here.
