[gcc]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from mainline
PR target/81348
* config/rs6000/rs6000.md (HI sign_extend splitter): Use the
correct operand in doing the split.
[gcc/testsuite]
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from mainline
2017-07-07 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/81348
* gcc.target/powerpc/pr81348.c: New test.
From-SVN: r250060
This patch serie adds support for the SPARC M8 processor to GCC.
The SPARC M8 processor implements the Oracle SPARC Architecture 2017.
- bmask* instructions are put in their own instruction type. It makes
little sense to have them in the same category than array
instructions.
- Similarly, VIS compare instructions are put in their own instruction
type. This is to better accommodate subtypes, which are not quite
the same than the subtypes of `visl' instructions.
- The introduction of a new `subtype' insn attribute in sparc.md
avoids the need for adjusting the instruction scheduler DFAs for
previous cpu models every time a new cpu is introduced.
- The full set of SPARC instructions used in sparc.md, and their
position in the type/subtype hierarchy, is documented in a comment.
This eases the modification of the DFA schedulers, and the addition
of new cpus.
- The M7 DFA scheduler is reworked:
+ To use the new type/subtype hierarchy.
+ The v3pipe insn attribute is no longer needed.
+ More accurate latencies for instructions.
+ The S4 core pipeline is documented in a comment in niagara7.md.
- Support for -mcpu=m8 (we are thus suggesting to abandon the niagaraN
denomination for M8 and later processors.)
- Support for a new VIS level, VIS4B, covering the new VIS
instructions introduced in OSA2017 and implemented in the M8. Also
built-ins.
- A M8 DFA scheduler:
+ Also based on the new type/subtype hierarchy.
+ The functional units in the S5 core are explicitly documented in a
comment in m8.md.
gcc/ChangeLog:
* config/sparc/m8.md: New file.
* config/sparc/sparc.md: Include m8.md.
* config/sparc/sparc.opt: New option -mvis4b.
* config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B.
(sparc_option_override): Handle VIS4B.
(enum sparc_builtins): Define
SPARC_BUILTIN_DICTUNPACK{8,16,32},
SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and
SPARC_BUILTIN_FPCMPUR{8,16,32}SHL.
(check_constant_argument): New function.
(sparc_vis_init_builtins): Define builtins
__builtin_vis_dictunpack{8,16,32},
__builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl,
__builtin_vis_fpcmpu{le,gt}{8,16,32}shl,
__builtin_vis_fpcmpde{8,16,32}shl and
__builtin_vis_fpcmpur{8,16,32}shl.
(sparc_expand_builtin): Check that the constant operands to
__builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed
constant and in range.
* config/sparc/sparc-c.c (sparc_target_macros): Handle
TARGET_VIS4B.
* config/sparc/sparc.h (SPARC_IMM2_P): Define.
(SPARC_IMM5_P): Likewise.
* config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b".
(enabled): Handle vis4b.
(UNSPEC_DICTUNPACK): New unspec.
(UNSPEC_FPCMPSHL): Likewise.
(UNSPEC_FPUCMPSHL): Likewise.
(UNSPEC_FPCMPDESHL): Likewise.
(UNSPEC_FPCMPURSHL): Likewise.
(cpu_feature): New CPU feature `vis4b'.
(dictunpack{8,16,32}): New insns.
(FPCSMODE): New mode iterator.
(fpcscond): New code iterator.
(fpcsucond): Likewise.
(fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns.
(fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise.
(fpcmpde{8,16,32}{si,di}shl): Likewise.
(fpcmpur{8,16,32}{si,di}shl): Likewise.
* config/sparc/constraints.md: Define constraints `q' for unsigned
2-bit integer constants and `t' for unsigned 5-bit integer
constants.
* config/sparc/predicates.md (imm5_operand_dictunpack8): New
predicate.
(imm5_operand_dictunpack16): Likewise.
(imm5_operand_dictunpack32): Likewise.
(imm2_operand): Likewise.
* doc/invoke.texi (SPARC Options): Document -mvis4b.
* doc/extend.texi (SPARC VIS Built-in Functions): Document the
ditunpack* and fpcmp*shl builtins.
* config.gcc: Handle m8 in --with-{cpu,tune} options.
* config.in: Add HAVE_AS_SPARC6 define.
* config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC
M8.
* config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for
TARGET_CPU_m8.
(ASM_CPU32_DEFAUILT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle m8.
(ASM_CPU_SPEC): Likewise.
* config/sparc/sparc-opts.h (enum processor_type): Add
PROCESSOR_M8.
* config/sparc/sparc.c (m8_costs): New struct.
(sparc_option_override): Handle TARGET_CPU_m8.
(sparc32_initialize_trampoline): Likewise.
(sparc64_initialize_trampoline): Likewise.
(sparc_issue_rate): Likewise.
(sparc_register_move_cost): Likewise.
* config/sparc/sparc.h (TARGET_CPU_m8): Define.
(CPP_CPU64_DEFAULT_SPEC): Define for M8.
(ASM_CPU64_DEFAULT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle M8.
(ASM_CPU_SPEC): Likewise.
(AS_M8_FLAG): Define.
* config/sparc/sparc.md: Add m8 to the cpu attribute.
* config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets.
* configure.ac (HAVE_AS_SPARC6): Check for assembler support for
M8 instructions.
* configure: Regenerate.
* doc/invoke.texi (SPARC Options): Document -mcpu=m8 and
-mtune=m8.
* config/sparc/niagara7.md: Rework the DFA scheduler to use insn
subtypes.
* config/sparc/sparc.md: Remove the `v3pipe' insn attribute.
("*movdi_insn_sp32"): Do not set v3pipe.
("*movsi_insn"): Likewise.
("*movdi_insn_sp64"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("*sign_extendsidi2_insn"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("<vlop:code><VL:mode>3"): Likewise.
("*not_<vlop:code><VL:mode>3"): Likewise.
("*nand<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise.
("one_cmpl<VL:mode>2"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likweise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
("bmaskdi_vis"): Likewise.
("bmasksi_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("pdistn<P:mode>_vis"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
* config/sparc/sparc.md ("subtype"): New insn attribute.
("*wrgsr_sp64"): Set insn subtype.
("*rdgsr_sp64"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likewise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("fexpand_vis"): Likewise.
("fpmerge_vis"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("fchksm16_vis"): Likewise.
("v<vis3_shift_patname><GCM:mode>3"): Likewise.
("fmean16_vis"): Likewise.
("fp<plusminus_insn>64_vis"): Likewise.
("<plusminus_insn>v8qi3"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
("<vis4_minmax_patname><VMMAX:mode>3"): Likewise.
("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise.
("<vis3_addsub_ss_patname>v8qi3"): Likewise.
("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise.
("*movqi_insn"): Likewise.
("*movhi_insn"): Likewise.
("*movsi_insn"): Likewise.
("movsi_pic_gotdata_op"): Likewise.
("*movdi_insn_sp32"): Likewise.
("*movdi_insn_sp64"): Likewise.
("movdi_pic_gotdata_op"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendhisi2_insn"): Likewise.
("*zero_extendqihi2_insn"): Likewise.
("*zero_extendqisi2_insn"): Likewise.
("*zero_extendqidi2_insn"): Likewise.
("*zero_extendhidi2_insn"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("ldfsr"): Likewise.
("prefetch_64"): Likewise.
("prefetch_32"): Likewise.
("tie_ld32"): Likewise.
("tie_ld64"): Likewise.
("*tldo_ldub_sp32"): Likewise.
("*tldo_ldub1_sp32"): Likewise.
("*tldo_ldub2_sp32"): Likewise.
("*tldo_ldub_sp64"): Likewise.
("*tldo_ldub1_sp64"): Likewise.
("*tldo_ldub2_sp64"): Likewise.
("*tldo_ldub3_sp64"): Likewise.
("*tldo_lduh_sp32"): Likewise.
("*tldo_lduh1_sp32"): Likewise.
("*tldo_lduh_sp64"): Likewise.
("*tldo_lduh1_sp64"): Likewise.
("*tldo_lduh2_sp64"): Likewise.
("*tldo_lduw_sp32"): Likewise.
("*tldo_lduw_sp64"): Likewise.
("*tldo_lduw1_sp64"): Likewise.
("*tldo_ldx_sp64"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.
* config/sparc/sparc.md ("type"): New insn type viscmp.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to
viscmp.
("fpcmp<gcond:code>8<P:mode>_vis"): Likewise.
("fucmp<gcond:code>8<P:mode>_vis"): Likewise.
("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
* config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle
viscmp.
("n7_vis_logical_11cycle"): Likewise.
* config/sparc/niagara4.md ("n4_vis_logical"): Likewise.
* config/sparc/niagara2.md ("niag3_vis": Likewise.
* config/sparc/niagara.md ("niag_vis"): Likewise.
* config/sparc/ultra3.md ("us3_fga"): Likewise.
* config/sparc/ultra1_2.md ("us1_fga_double"): Likewise.
* config/sparc/sparc.md: New instruction type `bmask'.
(bmaskdi_vis): Use the `bmask' type.
(bmasksi_vis): Likewise.
* config/sparc/ultra3.md (us3_array): Likewise.
* config/sparc/niagara7.md (n7_array): Likewise.
* config/sparc/niagara4.md (n4_array): Likewise.
* config/sparc/niagara2.md (niag2_vis): Likewise.
(niag3_vis): Likewise.
* config/sparc/niagara.md (niag_vis): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/sparc/dictunpack.c: New file.
* gcc.target/sparc/fpcmpdeshl.c: Likewise.
* gcc.target/sparc/fpcmpshl.c: Likewise.
* gcc.target/sparc/fpcmpurshl.c: Likewise.
* gcc.target/sparc/fpcmpushl.c: Likewise.
From-SVN: r250050
PR target/81300
* config/i386/i386.md (setcc + movzbl/and to xor + setcc peepholes):
Require dead FLAGS_REG at the beginning of a peephole.
PR target/81294
* config/i386/adxintrin.h (_subborrow_u32): Swap _X and _Y
arguments in the call to __builtin_ia32_sbb_u32.
(_subborrow_u64): Swap _X and _Y arguments in the call to
__builtin_ia32_sbb_u64.
testsuite/ChangeLog:
PR target/81300
* gcc.target/i386/pr81300.c: New test.
PR target/81294
* gcc.target/i386/adx-addcarryx32-2.c (adx_test): Swap
x and y arguments in the call to _subborrow_u32.
* gcc.target/i386/adx-addcarryx64-2.c (adx_test): Swap
x and y arguments in the call to _subborrow_u64.
* gcc.target/i386/pr81294-1.c: New test.
* gcc.target/i386/pr81294-2.c: Ditto.
From-SVN: r249978
2017-07-03 Tom de Vries <tom@codesourcery.com>
backport from mainline:
2017-07-03 Tom de Vries <tom@codesourcery.com>
PR tree-optimization/81192
* tree-ssa-tail-merge.c (same_succ_flush_bb): Handle
BB_SAME_SUCC (bb) == NULL.
* gcc.dg/pr81192.c: New test.
From-SVN: r249898
[gcc]
2017-06-29 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from mainline
2017-06-23 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80510
* config/rs6000/rs6000.md (ALTIVEC_DFORM): Do not allow DImode in
32-bit, since indexed is not valid for DImode.
(mov<mode>_hardfloat32): Reorder ISA 2.07 load/stores before ISA
3.0 d-form load/stores to be the same as mov<mode>_hardfloat64.
(define_peephole2 for Altivec d-form load): Add 32-bit support.
(define_peephole2 for Altivec d-form store): Likewise.
Backport from mainline
2017-06-20 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79799
* config/rs6000/rs6000.c (rs6000_expand_vector_init): Add support
for doing vector set of SFmode on ISA 3.0.
* config/rs6000/vsx.md (vsx_set_v4sf_p9): Likewise.
(vsx_set_v4sf_p9_zero): Special case setting 0.0f to a V4SF
element.
(vsx_insert_extract_v4sf_p9): Add an optimization for inserting a
SFmode value into a V4SF variable that was extracted from another
V4SF variable without converting the element to double precision
and back to single precision vector format.
(vsx_insert_extract_v4sf_p9_2): Likewise.
[gcc/testsuite]
2017-06-29 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from mainline
2017-06-23 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80510
* gcc.target/powerpc/pr80510-1.c: Allow test to run on 32-bit.
* gcc.target/powerpc/pr80510-2.c: Likewise.
Backport from mainline
2017-06-20 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/79799
* gcc.target/powerpc/pr79799-1.c: New test.
* gcc.target/powerpc/pr79799-2.c: Likewise.
* gcc.target/powerpc/pr79799-3.c: Likewise.
* gcc.target/powerpc/pr79799-4.c: Likewise.
* gcc.target/powerpc/pr79799-5.c: Likewise.
From-SVN: r249819
2017-06-28 Richard Biener <rguenther@suse.de>
Backport from mainline
2017-06-09 Richard Biener <rguenther@suse.de>
PR middle-end/81007
* ipa-polymorphic-call.c
(ipa_polymorphic_call_context::restrict_to_inner_class):
Skip FIELD_DECLs with error_mark_node type.
* passes.def (all_lowering_passes): Run pass_build_cgraph_edges
last again.
* g++.dg/pr81007.C: New testcase.
2017-06-14 Richard Biener <rguenther@suse.de>
PR tree-optimization/81083
* tree-ssa-sccvn.c (vn_reference_lookup_3): Do not use abnormals
as values.
* gcc.dg/torture/pr81083.c: New testcase.
2017-06-21 Richard Biener <rguenther@suse.de>
PR gcov-profile/81080
* configure.ac: Add AC_SYS_LARGEFILE.
* libgcov.h: Include auto-target.h before tsystem.h to pick
up _FILE_OFFSET_BITS which might differ for multilibs.
* config.in: Regenerate.
* configure: Likewise.
From-SVN: r249738
2017-06-27 Jerry DeLisle <jvdelisle@gcc.gnu.org>
Backport from trunk
PR libgfortran/53029
* io/list_read.c(list_formatted_read_scalar: Set the err return
value to the common.flags error values.
* gfortran.dg/read_5.f90: New test.
From-SVN: r249719
2017-06-22 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-05-26 Martin Liska <mliska@suse.cz>
PR ipa/80663
* params.def: Bound partial-inlining-entry-probability param.
2017-06-22 Martin Liska <mliska@suse.cz>
Backport from mainline
2017-05-26 Martin Liska <mliska@suse.cz>
PR ipa/80663
* g++.dg/ipa/pr80212.C: Remove the test as it does not longer
split at the problematic spot.
* gcc.dg/ipa/pr48195.c: Change 101 to 100 as 101 is no longer
a valid value of the param.
From-SVN: r249548
2017-06-21 Michael Meissner <meissner@linux.vnet.ibm.com>
Back port from mainline
PR target/80510
* gcc.target/powerpc/pr80510-1.c: Restrict test to 64-bit until
32-bit support is added. Change ITYPE size to 64-bit integer.
* gcc.target/powerpc/pr80510-2.c: Likewise.
From-SVN: r249488
PR c++/81154
* semantics.c (handle_omp_array_sections_1, finish_omp_clauses):
Complain about t not being a variable if t is OVERLOAD even
when processing_template_decl.
* g++.dg/gomp/pr81154.C: New test.
From-SVN: r249483
Backported from mainline
2017-06-20 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/81125
* ubsan.h (ubsan_encode_value): Workaround buggy clang++ parser
by removing enum keyword.
(ubsan_type_descriptor): Likewise. Formatting fix.
2017-06-19 Jakub Jelinek <jakub@redhat.com>
PR sanitizer/81125
* ubsan.h (enum ubsan_encode_value_phase): New.
(ubsan_encode_value): Change second argument to
enum ubsan_encode_value_phase with default value of
UBSAN_ENCODE_VALUE_GENERIC.
* ubsan.c (ubsan_encode_value): Change second argument to
enum ubsan_encode_value_phase PHASE from bool IN_EXPAND_P,
adjust uses, for UBSAN_ENCODE_VALUE_GENERIC use just
create_tmp_var_raw instead of create_tmp_var and use a
TARGET_EXPR.
(ubsan_expand_bounds_ifn, ubsan_build_overflow_builtin,
instrument_bool_enum_load, ubsan_instrument_float_cast): Adjust
ubsan_encode_value callers.
PR sanitizer/81111
* ubsan.c (ubsan_encode_value): If current_function_decl is NULL,
use create_tmp_var_raw instead of create_tmp_var, mark it addressable
just by setting TREE_ADDRESSABLE on the result and use a TARGET_EXPR.
PR sanitizer/81125
* g++.dg/ubsan/pr81125.C: New test.
PR sanitizer/81111
* g++.dg/ubsan/pr81111.C: New test.
From-SVN: r249480
Backported from mainline
2017-06-13 Jakub Jelinek <jakub@redhat.com>
PR c++/80973
* cp-gimplify.c (cp_genericize_r): Don't instrument MEM_REF second
argument even if it has REFERENCE_TYPE.
* g++.dg/ubsan/pr80973.C: New test.
From-SVN: r249479
Backported from mainline
2017-06-13 Jakub Jelinek <jakub@redhat.com>
PR c++/80984
* cp-gimplify.c (cp_genericize): Only look for VAR_DECLs in
BLOCK_VARS (outer) chain.
(cxx_omp_const_qual_no_mutable): Likewise.
* g++.dg/opt/nrv18.C: New test.
From-SVN: r249478
gcc/
PR target/71778
* config/arm/arm-builtins.c (arm_expand_builtin_args): Return TARGET
if given a non-constant argument for an intrinsic which requires a
constant.
gcc/testsuite/
PR target/71778
* gcc.target/arm/pr71778.c: New.
From-SVN: r249379
* config/sparc/sparc.h (MASK_ISA): Add MASK_LEON and MASK_LEON3.
(MASK_FEATURES): New macro.
* config/sparc/sparc.c (sparc_option_override): Remove the special
handling of -mfpu and generalize it to all MASK_FEATURES switches.
From-SVN: r249190
2017-06-09 Janus Weil <janus@gcc.gnu.org>
Backport from trunk
PR fortran/70601
* trans-expr.c (gfc_conv_procedure_call): Fix detection of allocatable
function results.
2017-06-09 Janus Weil <janus@gcc.gnu.org>
Backport from trunk
PR fortran/70601
* gfortran.dg/proc_ptr_comp_50.f90: New test.
From-SVN: r249066
PR c++/81011
* cp-gimplify.c (cxx_omp_finish_clause): When changing clause
to OMP_CLAUSE_SHARED, also clear OMP_CLAUSE_SHARED_FIRSTPRIVATE
and OMP_CLAUSE_SHARED_READONLY flags.
* g++.dg/gomp/pr81011.C: New test.
From-SVN: r249032
2017-06-07 Richard Biener <rguenther@suse.de>
Backport from mainline
2017-05-02 Richard Biener <rguenther@suse.de>
PR tree-optimization/80549
* tree-cfgcleanup.c (mfb_keep_latches): New helper.
(cleanup_tree_cfg_noloop): Create forwarders to known loop
headers if they do not have a preheader.
* gcc.dg/torture/pr80549.c: New testcase.
2017-05-19 Richard Biener <rguenther@suse.de>
PR c++/80593
* c-warn.c (strict_aliasing_warning): Do not warn for accesses
to alias-set zero memory.
* g++.dg/warn/Wstrict-aliasing-bogus-char-2.C: New testcase.
* g++.dg/warn/Wstrict-aliasing-6.C: Adjust expected outcome.
2017-05-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/80842
* tree-ssa-ccp.c (set_lattice_value): Always meet with the old
value.
* gcc.dg/torture/pr80842.c: New testcase.
2017-05-31 Richard Biener <rguenther@suse.de>
PR tree-optimization/80906
* graphite-isl-ast-to-gimple.c (copy_loop_close_phi_nodes): Get
and pass through iv_map.
(copy_bb_and_scalar_dependences): Adjust.
(translate_pending_phi_nodes): Likewise.
(copy_loop_close_phi_args): Handle code-generating IVs instead
of ICEing.
* gcc.dg/graphite/pr80906.c: New testcase.
2017-05-11 Richard Biener <rguenther@suse.de>
PR tree-optimization/80705
* tree-vect-data-refs.c (vect_analyze_data_refs): DECL_NONALIASED
bases are not vectorizable.
* gcc.dg/vect/bb-slp-pr80705.c: New testcase.
From-SVN: r248970
PR c/80919
* c-format.c (matching_type_p): Return false if any of the types
requires structural equality.
* gcc.dg/format/pr80919.c: New test.
From-SVN: r248963
Back port from mainline
[gcc]
2017-05-19 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80718
* config/rs6000/vsx.md (vsx_splat_<mode>, VSX_D iterator): Prefer
VSX registers over GPRs, particularly on ISA 2.07 which does not
have the MTVSRDD instruction.
[gcc/testsuite]
2017-05-19 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80718
* gcc.target/powerpc/pr80718.c: New test.
From-SVN: r248936
2017-06-05 Janus Weil <janus@gcc.gnu.org>
Backport from trunk
PR fortran/80766
* resolve.c (resolve_fl_derived): Make sure that vtype symbols are
properly resolved.
2017-06-05 Janus Weil <janus@gcc.gnu.org>
Backport from trunk
PR fortran/80766
* gfortran.dg/typebound_call_28.f90: New test.
From-SVN: r248873
2017-05-31 Martin Jambor <mjambor@suse.cz>
Backport from mainline
2017-04-24 Martin Jambor <mjambor@suse.cz>
PR tree-optimization/80293
* tree-sra.c (scalarizable_type_p): New parameter const_decl, make
char arrays not totally scalarizable if it is false.
(analyze_all_variable_accesses): Pass correct value in the new
parameter. Add a statistics counter.
testsuite/
* g++.dg/tree-ssa/pr80293.C: New test.
From-SVN: r248724
PR sanitizer/80659
* c-decl.c (build_compound_literal): Set DECL_ARTIFICIAL and
DECL_IGNORED_P even for non-static compound literals.
* gcc.dg/asan/pr80659.c: New test.
From-SVN: r248491
PR sanitizer/80875
* fold-const.c (fold_binary_loc) <case MULT_EXPR>: Check if OP1
can be negated.
* c-c++-common/ubsan/pr80875.c: New test.
From-SVN: r248490
[gcc]
2017-05-25 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from trunk
2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80510
* config/rs6000/predicates.md (simple_offsettable_mem_operand):
New predicate.
* config/rs6000/rs6000.md (ALTIVEC_DFORM): New iterator.
(define_peephole2 for Altivec d-form load): Add peepholes to catch
cases where the register allocator uses a move and an offsettable
memory operation to/from a FPR register on ISA 2.06/2.07.
(define_peephole2 for Altivec d-form store): Likewise.
Backport from trunk
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* config/rs6000/rs6000.md (f32_lr): Delete mode attributes that
are now unused after splitting mov{sf,sd}_hardfloat.
(f32_lr2): Likewise.
(f32_lm): Likewise.
(f32_lm2): Likewise.
(f32_li): Likewise.
(f32_li2): Likewise.
(f32_lv): Likewise.
(f32_sr): Likewise.
(f32_sr2): Likewise.
(f32_sm): Likewise.
(f32_sm2): Likewise.
(f32_si): Likewise.
(f32_si2): Likewise.
(f32_sv): Likewise.
(f32_dm): Likewise.
(f32_vsx): Likewise.
(f32_av): Likewise.
(mov<mode>_hardfloat): Split into separate movsf and movsd pieces.
For movsf, order stores so the VSX stores occur before the GPR
store which encourages the register allocator to use a traditional
FPR instead of a GPR. For movsd, order the stores so that the GPR
store comes before the VSX stores to allow the power6 to work.
This is due to the power6 not having a 32-bit integer store
instruction from a FPR.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
[gcc/testsuite]
2017-05-25 Michael Meissner <meissner@linux.vnet.ibm.com>
Backport from trunk
2017-05-18 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/80510
* gcc.target/powerpc/pr80510-1.c: New test.
* gcc.target/powerpc/pr80510-2.c: Likewise.
Backport from trunk
2017-05-09 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/68163
* gcc.target/powerpc/pr68163.c: New test.
From-SVN: r248480
2017-05-23 Paul Thomas <pault@gcc.gnu.org>
Backport from trunk
PR fortran/80333
* trans-io.c (nml_get_addr_expr): If we are dealing with class
type data set tmp tree to get that address.
(transfer_namelist_element): Set the array spec to point to the
the class data.
* gfortran.dg/dtio_30.f03: New test.
* list_read.c (nml_read_obj): Compute pointer into class/type
arrays from the nl->dim information. Update it for each iteration
of the loop for the given object.
From-SVN: r248388
Backport from mainline
2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
* config/sparc/sparc.c (sparc_option_override): Set function
alignment for -mcpu=niagara7 to 64 to match the I$ line.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC M7 branch
latency to 1.
* config/sparc/sparc.h (BRANCH_COST): Set the SPARC T4 branch
latency to 2.
* config/sparc/sol2.h: Fix a ASM_CPU32_DEFAULT_SPEC typo.
Backport from mainline
2017-05-18 Sheldon Lobo <sheldon.lobo@oracle.com>
* gcc.target/sparc/niagara7-align.c: New test.
From-SVN: r248380
2017-05-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
Backport from mainline
2017-05-22 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
* gcc.target/powerpc/p8-vec-xl-xst.c: Fix target string to
LE-only.
From-SVN: r248349
Uros Bizjak
Michael Meissner
Jose E. Marchesi
Georg-Johann Lay
Tom de Vries
Richard Biener
Eric Botcazou
Jerry DeLisle
Segher Boessenkool
Jakub Jelinek
Marek Polacek
Thomas Preud'homme
Martin Liska
James Greenhalgh
Janus Weil
Uros Bizjak
Thomas Koenig
David S. Miller
Prakhar Bahuguna
Martin Jambor
Andreas Krebbel
Sheldon Lobo
Bill Schmidt