2005-07-10 20:58:15 +02:00
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/*
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* Support functions for OMAP GPIO
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*
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2005-09-07 18:20:26 +02:00
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* Copyright (C) 2003-2005 Nokia Corporation
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2007-10-19 23:21:04 +02:00
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* Written by Juha Yrjölä <juha.yrjola@nokia.com>
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2005-07-10 20:58:15 +02:00
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*
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2009-05-28 23:16:04 +02:00
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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2005-07-10 20:58:15 +02:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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2011-04-22 22:02:46 +02:00
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#include <linux/syscore_ops.h>
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2005-09-07 18:20:26 +02:00
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#include <linux/err.h>
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2006-01-07 17:15:52 +01:00
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#include <linux/clk.h>
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2008-09-06 13:10:45 +02:00
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#include <linux/io.h>
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2010-12-08 01:26:57 +01:00
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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2005-07-10 20:58:15 +02:00
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2008-08-05 17:14:15 +02:00
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#include <mach/hardware.h>
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2005-07-10 20:58:15 +02:00
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#include <asm/irq.h>
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2008-08-05 17:14:15 +02:00
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#include <mach/irqs.h>
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#include <mach/gpio.h>
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2005-07-10 20:58:15 +02:00
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#include <asm/mach/irq.h>
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struct gpio_bank {
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2009-10-20 00:25:20 +02:00
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unsigned long pbase;
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2005-09-07 18:20:26 +02:00
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void __iomem *base;
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2005-07-10 20:58:15 +02:00
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u16 irq;
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u16 virtual_irq_start;
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2005-09-07 18:20:26 +02:00
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int method;
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2010-02-12 21:26:48 +01:00
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#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
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2005-09-07 18:20:26 +02:00
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u32 suspend_wakeup;
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u32 saved_wakeup;
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2006-12-07 02:13:52 +01:00
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#endif
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u32 non_wakeup_gpios;
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u32 enabled_non_wakeup_gpios;
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u32 saved_datain;
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u32 saved_fallingdetect;
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u32 saved_risingdetect;
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2008-01-17 06:56:15 +01:00
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u32 level_mask;
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omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
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u32 toggle_mask;
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2005-07-10 20:58:15 +02:00
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spinlock_t lock;
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2008-03-03 21:43:23 +01:00
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struct gpio_chip chip;
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2008-12-11 02:35:24 +01:00
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struct clk *dbck;
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2009-11-22 19:11:25 +01:00
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u32 mod_usage;
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2009-01-27 20:15:34 +01:00
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u32 dbck_enable_mask;
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2010-12-08 01:26:57 +01:00
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struct device *dev;
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bool dbck_flag;
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2010-12-08 01:26:58 +01:00
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int stride;
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2011-04-21 18:23:00 +02:00
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u32 width;
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2011-04-21 01:31:23 +02:00
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void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
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struct omap_gpio_reg_offs *regs;
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2005-07-10 20:58:15 +02:00
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};
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2010-02-12 21:26:48 +01:00
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#ifdef CONFIG_ARCH_OMAP3
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2008-09-26 14:17:48 +02:00
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struct omap3_gpio_regs {
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u32 irqenable1;
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u32 irqenable2;
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u32 wake_en;
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u32 ctrl;
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u32 oe;
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u32 leveldetect0;
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u32 leveldetect1;
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u32 risingdetect;
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u32 fallingdetect;
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u32 dataout;
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2007-11-30 01:15:11 +01:00
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};
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2008-09-26 14:17:48 +02:00
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static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
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2007-11-30 01:15:11 +01:00
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#endif
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2010-12-08 01:26:57 +01:00
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/*
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* TODO: Cleanup gpio_bank usage as it is having information
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* related to all instances of the device
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*/
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static struct gpio_bank *gpio_bank;
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2009-05-28 23:16:04 +02:00
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2010-12-08 01:26:56 +01:00
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/* TODO: Analyze removing gpio_bank_count usage from driver code */
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int gpio_bank_count;
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2005-07-10 20:58:15 +02:00
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2011-04-22 16:59:07 +02:00
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#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
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#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
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2005-07-10 20:58:15 +02:00
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static inline int gpio_valid(int gpio)
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{
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if (gpio < 0)
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return -1;
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2008-01-13 00:35:04 +01:00
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if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
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2006-09-25 11:41:30 +02:00
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if (gpio >= OMAP_MAX_GPIO_LINES + 16)
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2005-07-10 20:58:15 +02:00
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return -1;
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return 0;
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}
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2006-04-02 18:46:23 +02:00
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if (cpu_is_omap15xx() && gpio < 16)
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2005-07-10 20:58:15 +02:00
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return 0;
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if ((cpu_is_omap16xx()) && gpio < 64)
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return 0;
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2009-03-24 02:07:40 +01:00
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if (cpu_is_omap7xx() && gpio < 192)
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2005-07-10 20:58:15 +02:00
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return 0;
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2010-08-02 13:21:39 +02:00
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if (cpu_is_omap2420() && gpio < 128)
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return 0;
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if (cpu_is_omap2430() && gpio < 160)
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2005-09-07 18:20:26 +02:00
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return 0;
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2009-05-28 23:16:04 +02:00
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if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
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2007-11-30 01:15:11 +01:00
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return 0;
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2005-07-10 20:58:15 +02:00
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return -1;
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}
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static int check_gpio(int gpio)
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{
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2009-11-17 23:39:03 +01:00
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if (unlikely(gpio_valid(gpio) < 0)) {
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2005-07-10 20:58:15 +02:00
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printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
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dump_stack();
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return -1;
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}
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return 0;
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}
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static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
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{
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2005-09-07 18:20:26 +02:00
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void __iomem *reg = bank->base;
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2005-07-10 20:58:15 +02:00
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u32 l;
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2011-04-21 01:31:23 +02:00
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reg += bank->regs->direction;
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2005-07-10 20:58:15 +02:00
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l = __raw_readl(reg);
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if (is_input)
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l |= 1 << gpio;
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else
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l &= ~(1 << gpio);
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__raw_writel(l, reg);
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}
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2011-04-21 01:31:23 +02:00
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/* set data out value using dedicate set/clear register */
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static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
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2005-07-10 20:58:15 +02:00
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{
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2005-09-07 18:20:26 +02:00
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void __iomem *reg = bank->base;
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2011-04-21 01:31:23 +02:00
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u32 l = GPIO_BIT(bank, gpio);
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2005-07-10 20:58:15 +02:00
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2011-04-21 01:31:23 +02:00
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if (enable)
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reg += bank->regs->set_dataout;
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else
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reg += bank->regs->clr_dataout;
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__raw_writel(l, reg);
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}
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/* set data out value using mask register */
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static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
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{
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void __iomem *reg = bank->base + bank->regs->dataout;
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u32 gpio_bit = GPIO_BIT(bank, gpio);
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u32 l;
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l = __raw_readl(reg);
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if (enable)
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l |= gpio_bit;
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else
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l &= ~gpio_bit;
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2005-07-10 20:58:15 +02:00
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__raw_writel(l, reg);
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}
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2009-08-05 15:53:24 +02:00
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static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
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2005-07-10 20:58:15 +02:00
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{
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2011-04-21 01:31:23 +02:00
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void __iomem *reg = bank->base + bank->regs->datain;
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2005-07-10 20:58:15 +02:00
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if (check_gpio(gpio) < 0)
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2006-12-07 02:13:59 +01:00
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return -EINVAL;
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2011-04-21 01:31:23 +02:00
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return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
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2005-07-10 20:58:15 +02:00
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}
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2009-08-05 15:53:24 +02:00
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static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
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{
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2011-04-21 01:31:23 +02:00
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void __iomem *reg = bank->base + bank->regs->dataout;
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2009-08-05 15:53:24 +02:00
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if (check_gpio(gpio) < 0)
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return -EINVAL;
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2011-04-22 16:59:07 +02:00
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return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
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2009-08-05 15:53:24 +02:00
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}
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2005-09-07 18:20:26 +02:00
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#define MOD_REG_BIT(reg, bit_mask, set) \
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do { \
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int l = __raw_readl(base + reg); \
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if (set) l |= bit_mask; \
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else l &= ~bit_mask; \
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__raw_writel(l, base + reg); \
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} while(0)
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2010-05-26 23:42:23 +02:00
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/**
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* _set_gpio_debounce - low level gpio debounce time
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* @bank: the gpio bank we're acting upon
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* @gpio: the gpio number on this @gpio
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* @debounce: debounce time to use
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*
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* OMAP's debounce time is in 31us steps so we need
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* to convert and round up to the closest unit.
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*/
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static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
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unsigned debounce)
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{
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void __iomem *reg = bank->base;
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u32 val;
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u32 l;
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2010-12-08 01:26:57 +01:00
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if (!bank->dbck_flag)
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return;
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2010-05-26 23:42:23 +02:00
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if (debounce < 32)
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debounce = 0x01;
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else if (debounce > 7936)
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debounce = 0xff;
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else
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debounce = (debounce / 0x1f) - 1;
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|
2011-04-22 16:59:07 +02:00
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l = GPIO_BIT(bank, gpio);
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2010-05-26 23:42:23 +02:00
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2010-12-08 01:26:57 +01:00
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if (bank->method == METHOD_GPIO_44XX)
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2010-05-26 23:42:23 +02:00
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reg += OMAP4_GPIO_DEBOUNCINGTIME;
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else
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reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
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__raw_writel(debounce, reg);
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reg = bank->base;
|
2010-12-08 01:26:57 +01:00
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if (bank->method == METHOD_GPIO_44XX)
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2010-05-26 23:42:23 +02:00
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reg += OMAP4_GPIO_DEBOUNCENABLE;
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else
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reg += OMAP24XX_GPIO_DEBOUNCE_EN;
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val = __raw_readl(reg);
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if (debounce) {
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val |= l;
|
2010-12-08 01:26:57 +01:00
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clk_enable(bank->dbck);
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2010-05-26 23:42:23 +02:00
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} else {
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val &= ~l;
|
2010-12-08 01:26:57 +01:00
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clk_disable(bank->dbck);
|
2010-05-26 23:42:23 +02:00
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}
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2010-06-09 12:53:07 +02:00
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bank->dbck_enable_mask = val;
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2010-05-26 23:42:23 +02:00
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__raw_writel(val, reg);
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}
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|
2010-02-12 21:26:48 +01:00
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#ifdef CONFIG_ARCH_OMAP2PLUS
|
2007-05-05 20:40:29 +02:00
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static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
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int trigger)
|
2005-07-10 20:58:15 +02:00
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{
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2006-12-07 02:13:52 +01:00
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void __iomem *base = bank->base;
|
2005-09-07 18:20:26 +02:00
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u32 gpio_bit = 1 << gpio;
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|
2009-07-28 15:27:30 +02:00
|
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if (cpu_is_omap44xx()) {
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MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_LOW);
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MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_HIGH);
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MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
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trigger & IRQ_TYPE_EDGE_RISING);
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MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
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trigger & IRQ_TYPE_EDGE_FALLING);
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} else {
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MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
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trigger & IRQ_TYPE_LEVEL_LOW);
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MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
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|
|
trigger & IRQ_TYPE_LEVEL_HIGH);
|
|
|
|
MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_RISING);
|
|
|
|
MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_FALLING);
|
|
|
|
}
|
2006-12-07 02:13:52 +01:00
|
|
|
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
|
2009-07-28 15:27:30 +02:00
|
|
|
if (cpu_is_omap44xx()) {
|
2011-06-06 22:38:17 +02:00
|
|
|
MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
|
|
|
|
trigger != 0);
|
2009-07-28 15:27:30 +02:00
|
|
|
} else {
|
2009-06-24 19:13:39 +02:00
|
|
|
/*
|
|
|
|
* GPIO wakeup request can only be generated on edge
|
|
|
|
* transitions
|
|
|
|
*/
|
|
|
|
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
2009-07-28 15:27:30 +02:00
|
|
|
__raw_writel(1 << gpio, bank->base
|
2007-05-05 20:40:29 +02:00
|
|
|
+ OMAP24XX_GPIO_SETWKUENA);
|
2009-07-28 15:27:30 +02:00
|
|
|
else
|
|
|
|
__raw_writel(1 << gpio, bank->base
|
2007-05-05 20:40:29 +02:00
|
|
|
+ OMAP24XX_GPIO_CLEARWKUENA);
|
2009-07-28 15:27:30 +02:00
|
|
|
}
|
2008-12-22 13:27:12 +01:00
|
|
|
}
|
|
|
|
/* This part needs to be executed always for OMAP34xx */
|
|
|
|
if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
|
2009-06-24 19:13:39 +02:00
|
|
|
/*
|
|
|
|
* Log the edge gpio and manually trigger the IRQ
|
|
|
|
* after resume if the input level changes
|
|
|
|
* to avoid irq lost during PER RET/OFF mode
|
|
|
|
* Applies for omap2 non-wakeup gpio and all omap3 gpios
|
|
|
|
*/
|
|
|
|
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->enabled_non_wakeup_gpios |= gpio_bit;
|
|
|
|
else
|
|
|
|
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
|
|
|
|
}
|
2007-05-05 20:40:29 +02:00
|
|
|
|
2009-07-28 15:27:30 +02:00
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
bank->level_mask =
|
|
|
|
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
|
|
|
|
__raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
|
|
|
|
} else {
|
|
|
|
bank->level_mask =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2010-01-29 23:20:05 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
/*
|
|
|
|
* This only applies to chips that can't do both rising and falling edge
|
|
|
|
* detection at once. For all other chips, this function is a noop.
|
|
|
|
*/
|
|
|
|
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
u32 l = 0;
|
|
|
|
|
|
|
|
switch (bank->method) {
|
|
|
|
case METHOD_MPUIO:
|
2010-12-08 01:26:58 +01:00
|
|
|
reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
break;
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_INT_CONTROL;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_INT_CONTROL;
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
default:
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if ((l >> gpio) & 1)
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
else
|
|
|
|
l |= 1 << gpio;
|
|
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
2010-01-29 23:20:05 +01:00
|
|
|
#endif
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
u32 l = 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_MPUIO:
|
2010-12-08 01:26:58 +01:00
|
|
|
reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
|
2005-07-10 20:58:15 +02:00
|
|
|
l = __raw_readl(reg);
|
2010-04-05 13:38:06 +02:00
|
|
|
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
bank->toggle_mask |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l &= ~(1 << gpio);
|
2005-09-07 18:20:26 +02:00
|
|
|
else
|
|
|
|
goto bad;
|
2005-07-10 20:58:15 +02:00
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1510:
|
|
|
|
reg += OMAP1510_GPIO_INT_CONTROL;
|
|
|
|
l = __raw_readl(reg);
|
2010-04-05 13:38:06 +02:00
|
|
|
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
bank->toggle_mask |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l &= ~(1 << gpio);
|
2005-09-07 18:20:26 +02:00
|
|
|
else
|
|
|
|
goto bad;
|
2005-07-10 20:58:15 +02:00
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2006-12-07 02:13:52 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-07-10 20:58:15 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
if (gpio & 0x08)
|
|
|
|
reg += OMAP1610_GPIO_EDGE_CTRL2;
|
|
|
|
else
|
|
|
|
reg += OMAP1610_GPIO_EDGE_CTRL1;
|
|
|
|
gpio &= 0x07;
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
l &= ~(3 << (gpio << 1));
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2006-04-02 18:46:23 +02:00
|
|
|
l |= 2 << (gpio << 1);
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2006-04-02 18:46:23 +02:00
|
|
|
l |= 1 << (gpio << 1);
|
2006-12-07 02:13:52 +01:00
|
|
|
if (trigger)
|
|
|
|
/* Enable wake-up during idle for dynamic tick */
|
|
|
|
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
|
|
|
|
else
|
|
|
|
__raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
|
2005-07-10 20:58:15 +02:00
|
|
|
break;
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2009-09-23 19:56:19 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
|
2009-09-22 11:02:58 +02:00
|
|
|
case METHOD_GPIO_7XX:
|
|
|
|
reg += OMAP7XX_GPIO_INT_CONTROL;
|
2009-03-24 02:07:40 +01:00
|
|
|
l = __raw_readl(reg);
|
2010-04-05 13:38:06 +02:00
|
|
|
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
bank->toggle_mask |= 1 << gpio;
|
2009-03-24 02:07:40 +01:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
|
|
|
l |= 1 << gpio;
|
|
|
|
else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
else
|
|
|
|
goto bad;
|
|
|
|
break;
|
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2006-12-07 02:13:52 +01:00
|
|
|
set_24xx_gpio_triggering(bank, gpio, trigger);
|
2010-12-29 12:01:31 +01:00
|
|
|
return 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
default:
|
2005-09-07 18:20:26 +02:00
|
|
|
goto bad;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
__raw_writel(l, reg);
|
|
|
|
return 0;
|
|
|
|
bad:
|
|
|
|
return -EINVAL;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static int gpio_irq_type(struct irq_data *d, unsigned type)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
2005-09-07 18:20:26 +02:00
|
|
|
unsigned gpio;
|
|
|
|
int retval;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
|
|
|
|
gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
|
2005-09-07 18:20:26 +02:00
|
|
|
else
|
2010-11-29 11:17:17 +01:00
|
|
|
gpio = d->irq - IH_GPIO_BASE;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
if (check_gpio(gpio) < 0)
|
2005-09-07 18:20:26 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
if (type & ~IRQ_TYPE_SENSE_MASK)
|
2006-04-02 18:46:23 +02:00
|
|
|
return -EINVAL;
|
2006-12-07 02:13:59 +01:00
|
|
|
|
|
|
|
/* OMAP1 allows only only edge triggering */
|
2007-11-30 01:15:11 +01:00
|
|
|
if (!cpu_class_is_omap2()
|
2006-12-07 02:13:59 +01:00
|
|
|
&& (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
|
2005-09-07 18:20:26 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
bank = irq_data_get_irq_chip_data(d);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2011-04-22 16:59:07 +02:00
|
|
|
retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2008-01-17 06:56:16 +01:00
|
|
|
|
|
|
|
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
2011-03-24 13:25:22 +01:00
|
|
|
__irq_set_handler_locked(d->irq, handle_level_irq);
|
2008-01-17 06:56:16 +01:00
|
|
|
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
2011-03-24 13:25:22 +01:00
|
|
|
__irq_set_handler_locked(d->irq, handle_edge_irq);
|
2008-01-17 06:56:16 +01:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
return retval;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-04-21 18:17:35 +02:00
|
|
|
reg += bank->regs->irqstatus;
|
2005-07-10 20:58:15 +02:00
|
|
|
__raw_writel(gpio_mask, reg);
|
2006-09-25 11:41:46 +02:00
|
|
|
|
|
|
|
/* Workaround for clearing DSP GPIO interrupts to allow retention */
|
2011-04-21 18:17:35 +02:00
|
|
|
if (bank->regs->irqstatus2) {
|
|
|
|
reg = bank->base + bank->regs->irqstatus2;
|
2009-04-23 20:10:50 +02:00
|
|
|
__raw_writel(gpio_mask, reg);
|
2011-04-21 18:17:35 +02:00
|
|
|
}
|
2009-04-23 20:10:50 +02:00
|
|
|
|
|
|
|
/* Flush posted write for the irq status to avoid spurious interrupts */
|
|
|
|
__raw_readl(reg);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
2011-04-22 16:59:07 +02:00
|
|
|
_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
2006-06-27 01:16:07 +02:00
|
|
|
u32 l;
|
2011-04-21 18:33:36 +02:00
|
|
|
u32 mask = (1 << bank->width) - 1;
|
2006-06-27 01:16:00 +02:00
|
|
|
|
2011-04-21 18:53:06 +02:00
|
|
|
reg += bank->regs->irqenable;
|
2006-06-27 01:16:07 +02:00
|
|
|
l = __raw_readl(reg);
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->irqenable_inv)
|
2006-06-27 01:16:07 +02:00
|
|
|
l = ~l;
|
|
|
|
l &= mask;
|
|
|
|
return l;
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
|
|
|
|
2011-04-21 18:53:06 +02:00
|
|
|
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 l;
|
|
|
|
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->set_irqenable) {
|
|
|
|
reg += bank->regs->set_irqenable;
|
|
|
|
l = gpio_mask;
|
|
|
|
} else {
|
|
|
|
reg += bank->regs->irqenable;
|
2005-07-10 20:58:15 +02:00
|
|
|
l = __raw_readl(reg);
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->irqenable_inv)
|
|
|
|
l &= ~gpio_mask;
|
2005-07-10 20:58:15 +02:00
|
|
|
else
|
|
|
|
l |= gpio_mask;
|
2011-04-21 18:53:06 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
u32 l;
|
|
|
|
|
|
|
|
if (bank->regs->clr_irqenable) {
|
|
|
|
reg += bank->regs->clr_irqenable;
|
2005-07-10 20:58:15 +02:00
|
|
|
l = gpio_mask;
|
2011-04-21 18:53:06 +02:00
|
|
|
} else {
|
|
|
|
reg += bank->regs->irqenable;
|
2009-03-24 02:07:40 +01:00
|
|
|
l = __raw_readl(reg);
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->irqenable_inv)
|
2009-03-24 02:07:40 +01:00
|
|
|
l |= gpio_mask;
|
2009-07-28 15:27:30 +02:00
|
|
|
else
|
2011-04-21 18:53:06 +02:00
|
|
|
l &= ~gpio_mask;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2011-04-21 18:53:06 +02:00
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
|
|
|
|
{
|
2011-04-21 18:53:06 +02:00
|
|
|
_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/*
|
|
|
|
* Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
|
|
|
|
* 1510 does not seem to have a wake-up register. If JTAG is connected
|
|
|
|
* to the target, system will wake up always on GPIO events. While
|
|
|
|
* system is running all registered GPIO interrupts need to have wake-up
|
|
|
|
* enabled. When system is suspended, only selected GPIO interrupts need
|
|
|
|
* to have wake-up enabled.
|
|
|
|
*/
|
|
|
|
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
|
|
|
|
{
|
2010-01-08 19:29:05 +01:00
|
|
|
unsigned long uninitialized_var(flags);
|
2008-03-03 13:33:30 +01:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:52 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2006-12-07 02:14:11 +01:00
|
|
|
case METHOD_MPUIO:
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_1610:
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2009-04-23 20:10:49 +02:00
|
|
|
if (enable)
|
2005-09-07 18:20:26 +02:00
|
|
|
bank->suspend_wakeup |= (1 << gpio);
|
2009-04-23 20:10:49 +02:00
|
|
|
else
|
2005-09-07 18:20:26 +02:00
|
|
|
bank->suspend_wakeup &= ~(1 << gpio);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
return 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2006-12-07 02:13:52 +01:00
|
|
|
case METHOD_GPIO_24XX:
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2006-12-07 02:14:11 +01:00
|
|
|
if (bank->non_wakeup_gpios & (1 << gpio)) {
|
|
|
|
printk(KERN_ERR "Unable to modify wakeup on "
|
|
|
|
"non-wakeup GPIO%d\n",
|
2011-04-21 18:23:00 +02:00
|
|
|
(bank - gpio_bank) * bank->width + gpio);
|
2006-12-07 02:14:11 +01:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2009-04-23 20:10:49 +02:00
|
|
|
if (enable)
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->suspend_wakeup |= (1 << gpio);
|
2009-04-23 20:10:49 +02:00
|
|
|
else
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->suspend_wakeup &= ~(1 << gpio);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:13:52 +01:00
|
|
|
return 0;
|
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
default:
|
|
|
|
printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
|
|
|
|
bank->method);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-09-25 11:41:38 +02:00
|
|
|
static void _reset_gpio(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
|
2006-09-25 11:41:38 +02:00
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
|
2006-09-25 11:41:38 +02:00
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
|
2010-11-29 11:17:17 +01:00
|
|
|
static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
|
2005-09-07 18:20:26 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
2005-09-07 18:20:26 +02:00
|
|
|
struct gpio_bank *bank;
|
|
|
|
int retval;
|
|
|
|
|
|
|
|
if (check_gpio(gpio) < 0)
|
|
|
|
return -ENODEV;
|
2010-11-29 11:17:17 +01:00
|
|
|
bank = irq_data_get_irq_chip_data(d);
|
2011-04-22 16:59:07 +02:00
|
|
|
retval = _set_gpio_wakeup(bank, GPIO_INDEX(bank, gpio), enable);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:27 +01:00
|
|
|
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2008-12-11 02:35:27 +01:00
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2008-03-03 21:43:23 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2006-09-25 11:41:38 +02:00
|
|
|
/* Set trigger to none. You need to enable the desired trigger with
|
|
|
|
* request_irq() or set_irq_type().
|
|
|
|
*/
|
2008-12-11 02:35:27 +01:00
|
|
|
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2005-11-10 15:26:50 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP15XX
|
2005-07-10 20:58:15 +02:00
|
|
|
if (bank->method == METHOD_GPIO_1510) {
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Claim the pin for MPU */
|
2005-07-10 20:58:15 +02:00
|
|
|
reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
|
2008-12-11 02:35:27 +01:00
|
|
|
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
#endif
|
2009-11-22 19:11:25 +01:00
|
|
|
if (!cpu_class_is_omap1()) {
|
|
|
|
if (!bank->mod_usage) {
|
2010-05-14 21:05:27 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2009-11-22 19:11:25 +01:00
|
|
|
u32 ctrl;
|
2010-05-14 21:05:27 +02:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
|
|
reg += OMAP24XX_GPIO_CTRL;
|
|
|
|
else if (cpu_is_omap44xx())
|
|
|
|
reg += OMAP4_GPIO_CTRL;
|
|
|
|
ctrl = __raw_readl(reg);
|
2009-11-22 19:11:25 +01:00
|
|
|
/* Module is enabled, clocks are not gated */
|
2010-05-14 21:05:27 +02:00
|
|
|
ctrl &= 0xFFFFFFFE;
|
|
|
|
__raw_writel(ctrl, reg);
|
2009-11-22 19:11:25 +01:00
|
|
|
}
|
|
|
|
bank->mod_usage |= 1 << offset;
|
|
|
|
}
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:27 +01:00
|
|
|
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2008-12-11 02:35:27 +01:00
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
if (bank->method == METHOD_GPIO_1610) {
|
|
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
|
|
void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
2008-12-11 02:35:27 +01:00
|
|
|
__raw_writel(1 << offset, reg);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
#endif
|
2010-05-14 21:05:27 +02:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
|
|
|
if (bank->method == METHOD_GPIO_24XX) {
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
|
|
void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
2008-12-11 02:35:27 +01:00
|
|
|
__raw_writel(1 << offset, reg);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
2010-05-14 21:05:27 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
|
|
if (bank->method == METHOD_GPIO_44XX) {
|
|
|
|
/* Disable wake-up during idle for dynamic tick */
|
|
|
|
void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
__raw_writel(1 << offset, reg);
|
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
#endif
|
2009-11-22 19:11:25 +01:00
|
|
|
if (!cpu_class_is_omap1()) {
|
|
|
|
bank->mod_usage &= ~(1 << offset);
|
|
|
|
if (!bank->mod_usage) {
|
2010-05-14 21:05:27 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2009-11-22 19:11:25 +01:00
|
|
|
u32 ctrl;
|
2010-05-14 21:05:27 +02:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
|
|
|
reg += OMAP24XX_GPIO_CTRL;
|
|
|
|
else if (cpu_is_omap44xx())
|
|
|
|
reg += OMAP4_GPIO_CTRL;
|
|
|
|
ctrl = __raw_readl(reg);
|
2009-11-22 19:11:25 +01:00
|
|
|
/* Module is disabled, clocks are gated */
|
|
|
|
ctrl |= 1;
|
2010-05-14 21:05:27 +02:00
|
|
|
__raw_writel(ctrl, reg);
|
2009-11-22 19:11:25 +01:00
|
|
|
}
|
|
|
|
}
|
2008-12-11 02:35:27 +01:00
|
|
|
_reset_gpio(bank, bank->chip.base + offset);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to unmask the GPIO bank interrupt as soon as possible to
|
|
|
|
* avoid missing GPIO interrupts for other lines in the bank.
|
|
|
|
* Then we need to mask-read-clear-unmask the triggered GPIO lines
|
|
|
|
* in the bank to avoid missing nested interrupts for a GPIO line.
|
|
|
|
* If we wait to unmask individual GPIO lines in the bank after the
|
|
|
|
* line's interrupt handler has been run, we may miss some nested
|
|
|
|
* interrupts.
|
|
|
|
*/
|
2006-11-23 12:41:32 +01:00
|
|
|
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *isr_reg = NULL;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 isr;
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
unsigned int gpio_irq, gpio_index;
|
2005-07-10 20:58:15 +02:00
|
|
|
struct gpio_bank *bank;
|
2006-06-27 01:16:00 +02:00
|
|
|
u32 retrigger = 0;
|
|
|
|
int unmasked = 0;
|
2011-02-21 14:46:08 +01:00
|
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-02-21 14:46:08 +01:00
|
|
|
chained_irq_enter(chip, desc);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-03-24 13:25:22 +01:00
|
|
|
bank = irq_get_handler_data(irq);
|
2011-04-21 18:17:35 +02:00
|
|
|
isr_reg = bank->base + bank->regs->irqstatus;
|
2010-12-08 01:25:40 +01:00
|
|
|
|
|
|
|
if (WARN_ON(!isr_reg))
|
|
|
|
goto exit;
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
while(1) {
|
2006-04-02 18:46:23 +02:00
|
|
|
u32 isr_saved, level_mask = 0;
|
2006-06-27 01:16:00 +02:00
|
|
|
u32 enabled;
|
2006-04-02 18:46:23 +02:00
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
enabled = _get_gpio_irqbank_mask(bank);
|
|
|
|
isr_saved = isr = __raw_readl(isr_reg) & enabled;
|
2006-04-02 18:46:23 +02:00
|
|
|
|
|
|
|
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
|
|
|
|
isr &= 0x0000ffff;
|
|
|
|
|
2007-11-30 01:15:11 +01:00
|
|
|
if (cpu_class_is_omap2()) {
|
2008-01-17 06:56:15 +01:00
|
|
|
level_mask = bank->level_mask & enabled;
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
2006-04-02 18:46:23 +02:00
|
|
|
|
|
|
|
/* clear edge sensitive interrupts before handler(s) are
|
|
|
|
called so that we don't miss any interrupt occurred while
|
|
|
|
executing them */
|
2011-04-21 18:53:06 +02:00
|
|
|
_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
|
2006-04-02 18:46:23 +02:00
|
|
|
_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
|
2011-04-21 18:53:06 +02:00
|
|
|
_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
|
2006-04-02 18:46:23 +02:00
|
|
|
|
|
|
|
/* if there is only edge sensitive GPIO pin interrupts
|
|
|
|
configured, we could unmask GPIO bank interrupt immediately */
|
2006-06-27 01:16:00 +02:00
|
|
|
if (!level_mask && !unmasked) {
|
|
|
|
unmasked = 1;
|
2011-02-21 14:46:08 +01:00
|
|
|
chained_irq_exit(chip, desc);
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
isr |= retrigger;
|
|
|
|
retrigger = 0;
|
2005-09-07 18:20:26 +02:00
|
|
|
if (!isr)
|
|
|
|
break;
|
|
|
|
|
|
|
|
gpio_irq = bank->virtual_irq_start;
|
|
|
|
for (; isr != 0; isr >>= 1, gpio_irq++) {
|
2011-04-22 16:59:07 +02:00
|
|
|
gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq));
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
if (!(isr & 1))
|
|
|
|
continue;
|
2006-07-03 02:22:22 +02:00
|
|
|
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
/*
|
|
|
|
* Some chips can't respond to both rising and falling
|
|
|
|
* at the same time. If this irq was requested with
|
|
|
|
* both flags, we need to flip the ICR data for the IRQ
|
|
|
|
* to respond to the IRQ for the opposite direction.
|
|
|
|
* This will be indicated in the bank toggle_mask.
|
|
|
|
*/
|
|
|
|
if (bank->toggle_mask & (1 << gpio_index))
|
|
|
|
_toggle_gpio_edge_triggering(bank, gpio_index);
|
|
|
|
#endif
|
|
|
|
|
2008-10-09 14:36:24 +02:00
|
|
|
generic_handle_irq(gpio_irq);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
2005-11-10 15:26:50 +01:00
|
|
|
}
|
2006-06-27 01:16:00 +02:00
|
|
|
/* if bank has any level sensitive GPIO pin interrupt
|
|
|
|
configured, we must unmask the bank interrupt only after
|
|
|
|
handler(s) are executed in order to avoid spurious bank
|
|
|
|
interrupt */
|
2010-12-08 01:25:40 +01:00
|
|
|
exit:
|
2006-06-27 01:16:00 +02:00
|
|
|
if (!unmasked)
|
2011-02-21 14:46:08 +01:00
|
|
|
chained_irq_exit(chip, desc);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_irq_shutdown(struct irq_data *d)
|
2006-09-25 11:41:38 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2011-06-06 22:38:18 +02:00
|
|
|
unsigned long flags;
|
2006-09-25 11:41:38 +02:00
|
|
|
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2006-09-25 11:41:38 +02:00
|
|
|
_reset_gpio(bank, gpio);
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-09-25 11:41:38 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_ack_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_mask_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2011-06-06 22:38:18 +02:00
|
|
|
unsigned long flags;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_unmask_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
unsigned int gpio = d->irq - IH_GPIO_BASE;
|
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2011-04-22 16:59:07 +02:00
|
|
|
unsigned int irq_mask = GPIO_BIT(bank, gpio);
|
2011-03-24 12:40:15 +01:00
|
|
|
u32 trigger = irqd_get_trigger_type(d);
|
2011-06-06 22:38:18 +02:00
|
|
|
unsigned long flags;
|
2009-06-05 00:57:10 +02:00
|
|
|
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2009-06-05 00:57:10 +02:00
|
|
|
if (trigger)
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
|
2008-01-17 06:56:15 +01:00
|
|
|
|
|
|
|
/* For level-triggered GPIOs, the clearing must be done after
|
|
|
|
* the HW source is cleared, thus after the handler has run */
|
|
|
|
if (bank->level_mask & irq_mask) {
|
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-01-17 06:56:14 +01:00
|
|
|
_set_gpio_irqenable(bank, gpio, 1);
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
static struct irq_chip gpio_irq_chip = {
|
|
|
|
.name = "GPIO",
|
2010-11-29 11:17:17 +01:00
|
|
|
.irq_shutdown = gpio_irq_shutdown,
|
|
|
|
.irq_ack = gpio_ack_irq,
|
|
|
|
.irq_mask = gpio_mask_irq,
|
|
|
|
.irq_unmask = gpio_unmask_irq,
|
|
|
|
.irq_set_type = gpio_irq_type,
|
|
|
|
.irq_set_wake = gpio_wake_enable,
|
2006-12-07 02:13:59 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
|
|
|
|
/* MPUIO uses the always-on 32k clock */
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void mpuio_ack_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
|
|
|
/* The ISR is reset automatically, so do nothing here. */
|
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void mpuio_mask_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
|
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void mpuio_unmask_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
|
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_set_gpio_irqenable(bank, gpio, 1);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
static struct irq_chip mpuio_irq_chip = {
|
|
|
|
.name = "MPUIO",
|
2010-11-29 11:17:17 +01:00
|
|
|
.irq_ack = mpuio_ack_irq,
|
|
|
|
.irq_mask = mpuio_mask_irq,
|
|
|
|
.irq_unmask = mpuio_unmask_irq,
|
|
|
|
.irq_set_type = gpio_irq_type,
|
2006-12-07 02:14:11 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
/* REVISIT: assuming only 16xx supports MPUIO wake events */
|
2010-11-29 11:17:17 +01:00
|
|
|
.irq_set_wake = gpio_wake_enable,
|
2006-12-07 02:14:11 +01:00
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
};
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
|
|
|
|
#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
|
|
|
|
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
|
|
|
|
#include <linux/platform_device.h>
|
|
|
|
|
2009-07-08 13:22:04 +02:00
|
|
|
static int omap_mpuio_suspend_noirq(struct device *dev)
|
2006-12-07 02:14:11 +01:00
|
|
|
{
|
2009-07-08 13:22:04 +02:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2006-12-07 02:14:11 +01:00
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
2010-12-08 01:26:58 +01:00
|
|
|
void __iomem *mask_reg = bank->base +
|
|
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2006-12-07 02:14:11 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
bank->saved_wakeup = __raw_readl(mask_reg);
|
|
|
|
__raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-07-08 13:22:04 +02:00
|
|
|
static int omap_mpuio_resume_noirq(struct device *dev)
|
2006-12-07 02:14:11 +01:00
|
|
|
{
|
2009-07-08 13:22:04 +02:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2006-12-07 02:14:11 +01:00
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
2010-12-08 01:26:58 +01:00
|
|
|
void __iomem *mask_reg = bank->base +
|
|
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2006-12-07 02:14:11 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
__raw_writel(bank->saved_wakeup, mask_reg);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-15 03:00:08 +01:00
|
|
|
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
|
2009-07-08 13:22:04 +02:00
|
|
|
.suspend_noirq = omap_mpuio_suspend_noirq,
|
|
|
|
.resume_noirq = omap_mpuio_resume_noirq,
|
|
|
|
};
|
|
|
|
|
2011-04-22 22:02:46 +02:00
|
|
|
/* use platform_driver for this. */
|
2006-12-07 02:14:11 +01:00
|
|
|
static struct platform_driver omap_mpuio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "mpuio",
|
2009-07-08 13:22:04 +02:00
|
|
|
.pm = &omap_mpuio_dev_pm_ops,
|
2006-12-07 02:14:11 +01:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device omap_mpuio_device = {
|
|
|
|
.name = "mpuio",
|
|
|
|
.id = -1,
|
|
|
|
.dev = {
|
|
|
|
.driver = &omap_mpuio_driver.driver,
|
|
|
|
}
|
|
|
|
/* could list the /proc/iomem resources */
|
|
|
|
};
|
|
|
|
|
|
|
|
static inline void mpuio_init(void)
|
|
|
|
{
|
2011-04-22 13:08:16 +02:00
|
|
|
struct gpio_bank *bank = &gpio_bank[0];
|
2010-12-08 01:26:57 +01:00
|
|
|
platform_set_drvdata(&omap_mpuio_device, bank);
|
2007-04-02 21:46:47 +02:00
|
|
|
|
2006-12-07 02:14:11 +01:00
|
|
|
if (platform_driver_register(&omap_mpuio_driver) == 0)
|
|
|
|
(void) platform_device_register(&omap_mpuio_device);
|
|
|
|
}
|
|
|
|
|
|
|
|
#else
|
|
|
|
static inline void mpuio_init(void) {}
|
|
|
|
#endif /* 16xx */
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
#else
|
|
|
|
|
|
|
|
extern struct irq_chip mpuio_irq_chip;
|
|
|
|
|
|
|
|
#define bank_is_mpuio(bank) 0
|
2006-12-07 02:14:11 +01:00
|
|
|
static inline void mpuio_init(void) {}
|
2006-12-07 02:13:59 +01:00
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------*/
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
/* REVISIT these are stupid implementations! replace by ones that
|
|
|
|
* don't switch on METHOD_* and which mostly avoid spinlocks
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int gpio_input(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
_set_gpio_direction(bank, offset, 1);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-05 15:53:24 +02:00
|
|
|
static int gpio_is_input(struct gpio_bank *bank, int mask)
|
|
|
|
{
|
2011-04-21 01:31:23 +02:00
|
|
|
void __iomem *reg = bank->base + bank->regs->direction;
|
2009-08-05 15:53:24 +02:00
|
|
|
|
|
|
|
return __raw_readl(reg) & mask;
|
|
|
|
}
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
static int gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
2009-08-05 15:53:24 +02:00
|
|
|
struct gpio_bank *bank;
|
|
|
|
void __iomem *reg;
|
|
|
|
int gpio;
|
|
|
|
u32 mask;
|
|
|
|
|
|
|
|
gpio = chip->base + offset;
|
2011-04-22 13:08:16 +02:00
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
2009-08-05 15:53:24 +02:00
|
|
|
reg = bank->base;
|
2011-04-22 16:59:07 +02:00
|
|
|
mask = GPIO_BIT(bank, gpio);
|
2009-08-05 15:53:24 +02:00
|
|
|
|
|
|
|
if (gpio_is_input(bank, mask))
|
|
|
|
return _get_gpio_datain(bank, gpio);
|
|
|
|
else
|
|
|
|
return _get_gpio_dataout(bank, gpio);
|
2008-03-03 21:43:23 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2011-04-21 01:31:23 +02:00
|
|
|
bank->set_dataout(bank, offset, value);
|
2008-03-03 21:43:23 +01:00
|
|
|
_set_gpio_direction(bank, offset, 0);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-26 23:42:23 +02:00
|
|
|
static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
|
|
|
|
unsigned debounce)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
2010-12-08 01:26:57 +01:00
|
|
|
|
|
|
|
if (!bank->dbck) {
|
|
|
|
bank->dbck = clk_get(bank->dev, "dbclk");
|
|
|
|
if (IS_ERR(bank->dbck))
|
|
|
|
dev_err(bank->dev, "Could not get gpio dbck\n");
|
|
|
|
}
|
|
|
|
|
2010-05-26 23:42:23 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
_set_gpio_debounce(bank, offset, debounce);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2011-04-21 01:31:23 +02:00
|
|
|
bank->set_dataout(bank, offset, value);
|
2008-03-03 21:43:23 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:25 +01:00
|
|
|
static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
return bank->virtual_irq_start + offset;
|
|
|
|
}
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
2010-12-08 01:26:56 +01:00
|
|
|
static void __init omap_gpio_show_rev(struct gpio_bank *bank)
|
2009-10-20 00:25:20 +02:00
|
|
|
{
|
|
|
|
u32 rev;
|
|
|
|
|
2010-12-08 01:26:56 +01:00
|
|
|
if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
|
|
|
|
rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
|
2009-10-20 00:25:20 +02:00
|
|
|
else if (cpu_is_omap24xx() || cpu_is_omap34xx())
|
2010-12-08 01:26:56 +01:00
|
|
|
rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
|
2009-10-20 00:25:20 +02:00
|
|
|
else if (cpu_is_omap44xx())
|
2010-12-08 01:26:56 +01:00
|
|
|
rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
|
2009-10-20 00:25:20 +02:00
|
|
|
else
|
|
|
|
return;
|
|
|
|
|
|
|
|
printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
|
|
|
|
(rev >> 4) & 0x0f, rev & 0x0f);
|
|
|
|
}
|
|
|
|
|
2008-02-26 20:10:50 +01:00
|
|
|
/* This lock class tells lockdep that GPIO irqs are in a different
|
|
|
|
* category than their parents, so it won't report false recursion.
|
|
|
|
*/
|
|
|
|
static struct lock_class_key gpio_lock_class;
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
static inline int init_gpio_info(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
/* TODO: Analyze removing gpio_bank_count usage from driver code */
|
|
|
|
gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!gpio_bank) {
|
|
|
|
dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* TODO: Cleanup cpu_is_* checks */
|
2010-12-08 01:26:55 +01:00
|
|
|
static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
|
|
|
|
{
|
|
|
|
if (cpu_class_is_omap2()) {
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
__raw_writel(0xffffffff, bank->base +
|
|
|
|
OMAP4_GPIO_IRQSTATUSCLR0);
|
|
|
|
__raw_writel(0x00000000, bank->base +
|
|
|
|
OMAP4_GPIO_DEBOUNCENABLE);
|
|
|
|
/* Initialize interface clk ungated, module enabled */
|
|
|
|
__raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
|
|
|
|
} else if (cpu_is_omap34xx()) {
|
|
|
|
__raw_writel(0x00000000, bank->base +
|
|
|
|
OMAP24XX_GPIO_IRQENABLE1);
|
|
|
|
__raw_writel(0xffffffff, bank->base +
|
|
|
|
OMAP24XX_GPIO_IRQSTATUS1);
|
|
|
|
__raw_writel(0x00000000, bank->base +
|
|
|
|
OMAP24XX_GPIO_DEBOUNCE_EN);
|
|
|
|
|
|
|
|
/* Initialize interface clk ungated, module enabled */
|
|
|
|
__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
} else if (cpu_is_omap24xx()) {
|
|
|
|
static const u32 non_wakeup_gpios[] = {
|
|
|
|
0xe203ffc0, 0x08700040
|
|
|
|
};
|
|
|
|
if (id < ARRAY_SIZE(non_wakeup_gpios))
|
|
|
|
bank->non_wakeup_gpios = non_wakeup_gpios[id];
|
|
|
|
}
|
|
|
|
} else if (cpu_class_is_omap1()) {
|
|
|
|
if (bank_is_mpuio(bank))
|
2010-12-08 01:26:58 +01:00
|
|
|
__raw_writew(0xffff, bank->base +
|
|
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride);
|
2010-12-08 01:26:55 +01:00
|
|
|
if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
|
|
|
|
__raw_writew(0xffff, bank->base
|
|
|
|
+ OMAP1510_GPIO_INT_MASK);
|
|
|
|
__raw_writew(0x0000, bank->base
|
|
|
|
+ OMAP1510_GPIO_INT_STATUS);
|
|
|
|
}
|
|
|
|
if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
|
|
|
|
__raw_writew(0x0000, bank->base
|
|
|
|
+ OMAP1610_GPIO_IRQENABLE1);
|
|
|
|
__raw_writew(0xffff, bank->base
|
|
|
|
+ OMAP1610_GPIO_IRQSTATUS1);
|
|
|
|
__raw_writew(0x0014, bank->base
|
|
|
|
+ OMAP1610_GPIO_SYSCONFIG);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Enable system clock for GPIO module.
|
|
|
|
* The CAM_CLK_CTRL *is* really the right place.
|
|
|
|
*/
|
|
|
|
omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
|
|
|
|
ULPD_CAM_CLK_CTRL);
|
|
|
|
}
|
|
|
|
if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
|
|
|
|
__raw_writel(0xffffffff, bank->base
|
|
|
|
+ OMAP7XX_GPIO_INT_MASK);
|
|
|
|
__raw_writel(0x00000000, bank->base
|
|
|
|
+ OMAP7XX_GPIO_INT_STATUS);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-05-27 22:56:12 +02:00
|
|
|
static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
|
2010-12-08 01:26:55 +01:00
|
|
|
{
|
2010-12-08 01:26:57 +01:00
|
|
|
int j;
|
2010-12-08 01:26:55 +01:00
|
|
|
static int gpio;
|
|
|
|
|
|
|
|
bank->mod_usage = 0;
|
|
|
|
/*
|
|
|
|
* REVISIT eventually switch from OMAP-specific gpio structs
|
|
|
|
* over to the generic ones
|
|
|
|
*/
|
|
|
|
bank->chip.request = omap_gpio_request;
|
|
|
|
bank->chip.free = omap_gpio_free;
|
|
|
|
bank->chip.direction_input = gpio_input;
|
|
|
|
bank->chip.get = gpio_get;
|
|
|
|
bank->chip.direction_output = gpio_output;
|
|
|
|
bank->chip.set_debounce = gpio_debounce;
|
|
|
|
bank->chip.set = gpio_set;
|
|
|
|
bank->chip.to_irq = gpio_2irq;
|
|
|
|
if (bank_is_mpuio(bank)) {
|
|
|
|
bank->chip.label = "mpuio";
|
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
|
|
|
bank->chip.dev = &omap_mpuio_device.dev;
|
|
|
|
#endif
|
|
|
|
bank->chip.base = OMAP_MPUIO(0);
|
|
|
|
} else {
|
|
|
|
bank->chip.label = "gpio";
|
|
|
|
bank->chip.base = gpio;
|
2011-04-21 18:23:00 +02:00
|
|
|
gpio += bank->width;
|
2010-12-08 01:26:55 +01:00
|
|
|
}
|
2011-04-21 18:23:00 +02:00
|
|
|
bank->chip.ngpio = bank->width;
|
2010-12-08 01:26:55 +01:00
|
|
|
|
|
|
|
gpiochip_add(&bank->chip);
|
|
|
|
|
|
|
|
for (j = bank->virtual_irq_start;
|
2011-04-21 18:23:00 +02:00
|
|
|
j < bank->virtual_irq_start + bank->width; j++) {
|
2011-03-22 17:11:09 +01:00
|
|
|
irq_set_lockdep_class(j, &gpio_lock_class);
|
2011-03-24 13:25:22 +01:00
|
|
|
irq_set_chip_data(j, bank);
|
2010-12-08 01:26:55 +01:00
|
|
|
if (bank_is_mpuio(bank))
|
2011-03-24 13:25:22 +01:00
|
|
|
irq_set_chip(j, &mpuio_irq_chip);
|
2010-12-08 01:26:55 +01:00
|
|
|
else
|
2011-03-24 13:25:22 +01:00
|
|
|
irq_set_chip(j, &gpio_irq_chip);
|
|
|
|
irq_set_handler(j, handle_simple_irq);
|
2010-12-08 01:26:55 +01:00
|
|
|
set_irq_flags(j, IRQF_VALID);
|
|
|
|
}
|
2011-03-24 13:25:22 +01:00
|
|
|
irq_set_chained_handler(bank->irq, gpio_irq_handler);
|
|
|
|
irq_set_handler_data(bank->irq, bank);
|
2010-12-08 01:26:55 +01:00
|
|
|
}
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
static int __devinit omap_gpio_probe(struct platform_device *pdev)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-12-08 01:26:57 +01:00
|
|
|
static int gpio_init_done;
|
|
|
|
struct omap_gpio_platform_data *pdata;
|
|
|
|
struct resource *res;
|
|
|
|
int id;
|
2005-07-10 20:58:15 +02:00
|
|
|
struct gpio_bank *bank;
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
if (!pdev->dev.platform_data)
|
|
|
|
return -EINVAL;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
pdata = pdev->dev.platform_data;
|
2006-12-07 02:14:08 +01:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
if (!gpio_init_done) {
|
|
|
|
int ret;
|
2007-11-30 01:15:11 +01:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
ret = init_gpio_info(pdev);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2007-11-30 01:15:11 +01:00
|
|
|
}
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
id = pdev->id;
|
|
|
|
bank = &gpio_bank[id];
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
if (unlikely(!res)) {
|
|
|
|
dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
|
|
|
|
return -ENODEV;
|
2009-05-28 23:16:04 +02:00
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
bank->irq = res->start;
|
|
|
|
bank->virtual_irq_start = pdata->virtual_irq_start;
|
|
|
|
bank->method = pdata->bank_type;
|
|
|
|
bank->dev = &pdev->dev;
|
|
|
|
bank->dbck_flag = pdata->dbck_flag;
|
2010-12-08 01:26:58 +01:00
|
|
|
bank->stride = pdata->bank_stride;
|
2011-04-21 18:23:00 +02:00
|
|
|
bank->width = pdata->bank_width;
|
2009-10-20 00:25:20 +02:00
|
|
|
|
2011-04-21 01:31:23 +02:00
|
|
|
bank->regs = pdata->regs;
|
|
|
|
|
|
|
|
if (bank->regs->set_dataout && bank->regs->clr_dataout)
|
|
|
|
bank->set_dataout = _set_gpio_dataout_reg;
|
|
|
|
else
|
|
|
|
bank->set_dataout = _set_gpio_dataout_mask;
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
spin_lock_init(&bank->lock);
|
2009-10-20 00:25:20 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
/* Static mapping, never released */
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (unlikely(!res)) {
|
|
|
|
dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2008-12-11 02:35:24 +01:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
bank->base = ioremap(res->start, resource_size(res));
|
|
|
|
if (!bank->base) {
|
|
|
|
dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
|
|
|
|
return -ENOMEM;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
pm_runtime_enable(bank->dev);
|
|
|
|
pm_runtime_get_sync(bank->dev);
|
|
|
|
|
|
|
|
omap_gpio_mod_init(bank, id);
|
|
|
|
omap_gpio_chip_init(bank);
|
2010-12-08 01:26:56 +01:00
|
|
|
omap_gpio_show_rev(bank);
|
2009-10-20 00:25:20 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
if (!gpio_init_done)
|
|
|
|
gpio_init_done = 1;
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
2011-04-22 22:02:46 +02:00
|
|
|
static int omap_gpio_suspend(void)
|
2005-09-07 18:20:26 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2007-11-30 01:15:11 +01:00
|
|
|
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
2005-09-07 18:20:26 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (i = 0; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
void __iomem *wake_status;
|
|
|
|
void __iomem *wake_clear;
|
|
|
|
void __iomem *wake_set;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
|
|
|
|
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
|
|
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
2008-11-26 23:35:16 +01:00
|
|
|
wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
|
2005-09-07 18:20:26 +02:00
|
|
|
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
|
|
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
default:
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
bank->saved_wakeup = __raw_readl(wake_status);
|
|
|
|
__raw_writel(0xffffffff, wake_clear);
|
|
|
|
__raw_writel(bank->suspend_wakeup, wake_set);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-04-22 22:02:46 +02:00
|
|
|
static void omap_gpio_resume(void)
|
2005-09-07 18:20:26 +02:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2008-11-26 23:35:16 +01:00
|
|
|
if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
|
2011-04-22 22:02:46 +02:00
|
|
|
return;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
|
|
|
for (i = 0; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
void __iomem *wake_clear;
|
|
|
|
void __iomem *wake_set;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
|
|
|
switch (bank->method) {
|
2006-12-07 02:13:59 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP16XX
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_1610:
|
|
|
|
wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
|
|
|
|
wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
|
2005-09-07 18:20:26 +02:00
|
|
|
case METHOD_GPIO_24XX:
|
2006-09-25 11:41:45 +02:00
|
|
|
wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
|
|
|
|
wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
|
2005-09-07 18:20:26 +02:00
|
|
|
break;
|
2009-07-28 15:27:30 +02:00
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2010-02-15 18:27:25 +01:00
|
|
|
case METHOD_GPIO_44XX:
|
2009-07-28 15:27:30 +02:00
|
|
|
wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
|
|
|
|
break;
|
2006-12-07 02:13:59 +01:00
|
|
|
#endif
|
2005-09-07 18:20:26 +02:00
|
|
|
default:
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
__raw_writel(0xffffffff, wake_clear);
|
|
|
|
__raw_writel(bank->saved_wakeup, wake_set);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-04-22 22:02:46 +02:00
|
|
|
static struct syscore_ops omap_gpio_syscore_ops = {
|
2005-09-07 18:20:26 +02:00
|
|
|
.suspend = omap_gpio_suspend,
|
|
|
|
.resume = omap_gpio_resume,
|
|
|
|
};
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
#endif
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2006-12-07 02:13:52 +01:00
|
|
|
|
|
|
|
static int workaround_enabled;
|
|
|
|
|
2010-12-22 05:05:16 +01:00
|
|
|
void omap2_gpio_prepare_for_idle(int off_mode)
|
2006-12-07 02:13:52 +01:00
|
|
|
{
|
|
|
|
int i, c = 0;
|
2008-12-22 13:27:12 +01:00
|
|
|
int min = 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
|
2008-12-22 13:27:12 +01:00
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
min = 1;
|
2009-01-27 20:09:24 +01:00
|
|
|
|
2008-12-22 13:27:12 +01:00
|
|
|
for (i = min; i < gpio_bank_count; i++) {
|
2006-12-07 02:13:52 +01:00
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
2010-09-24 03:27:18 +02:00
|
|
|
u32 l1 = 0, l2 = 0;
|
2010-09-23 01:06:27 +02:00
|
|
|
int j;
|
2006-12-07 02:13:52 +01:00
|
|
|
|
2010-09-23 01:06:27 +02:00
|
|
|
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
2009-01-27 20:15:34 +01:00
|
|
|
clk_disable(bank->dbck);
|
|
|
|
|
2010-12-22 05:05:16 +01:00
|
|
|
if (!off_mode)
|
2009-01-27 20:09:24 +01:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* If going to OFF, remove triggering for all
|
|
|
|
* non-wakeup GPIOs. Otherwise spurious IRQs will be
|
|
|
|
* generated. See OMAP2420 Errata item 1.101. */
|
2006-12-07 02:13:52 +01:00
|
|
|
if (!(bank->enabled_non_wakeup_gpios))
|
|
|
|
continue;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
|
bank->saved_datain = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_DATAIN);
|
|
|
|
l1 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
l2 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
bank->saved_datain = __raw_readl(bank->base +
|
|
|
|
OMAP4_GPIO_DATAIN);
|
|
|
|
l1 = __raw_readl(bank->base +
|
|
|
|
OMAP4_GPIO_FALLINGDETECT);
|
|
|
|
l2 = __raw_readl(bank->base +
|
|
|
|
OMAP4_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->saved_fallingdetect = l1;
|
|
|
|
bank->saved_risingdetect = l2;
|
|
|
|
l1 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
|
l2 &= ~bank->enabled_non_wakeup_gpios;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
|
__raw_writel(l1, bank->base +
|
|
|
|
OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
__raw_writel(l2, bank->base +
|
|
|
|
OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
__raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
|
|
|
|
__raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
c++;
|
|
|
|
}
|
|
|
|
if (!c) {
|
|
|
|
workaround_enabled = 0;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
workaround_enabled = 1;
|
|
|
|
}
|
|
|
|
|
2009-01-27 20:09:24 +01:00
|
|
|
void omap2_gpio_resume_after_idle(void)
|
2006-12-07 02:13:52 +01:00
|
|
|
{
|
|
|
|
int i;
|
2008-12-22 13:27:12 +01:00
|
|
|
int min = 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
|
2008-12-22 13:27:12 +01:00
|
|
|
if (cpu_is_omap34xx())
|
|
|
|
min = 1;
|
|
|
|
for (i = min; i < gpio_bank_count; i++) {
|
2006-12-07 02:13:52 +01:00
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
2010-09-24 03:27:18 +02:00
|
|
|
u32 l = 0, gen, gen0, gen1;
|
2010-09-23 01:06:27 +02:00
|
|
|
int j;
|
2006-12-07 02:13:52 +01:00
|
|
|
|
2010-09-23 01:06:27 +02:00
|
|
|
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
|
2009-01-27 20:15:34 +01:00
|
|
|
clk_enable(bank->dbck);
|
|
|
|
|
2009-01-27 20:09:24 +01:00
|
|
|
if (!workaround_enabled)
|
|
|
|
continue;
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
if (!(bank->enabled_non_wakeup_gpios))
|
|
|
|
continue;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
|
|
|
__raw_writel(bank->saved_fallingdetect,
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(bank->saved_risingdetect,
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
__raw_writel(bank->saved_fallingdetect,
|
2009-07-28 15:27:30 +02:00
|
|
|
bank->base + OMAP4_GPIO_FALLINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(bank->saved_risingdetect,
|
2009-07-28 15:27:30 +02:00
|
|
|
bank->base + OMAP4_GPIO_RISINGDETECT);
|
2010-02-15 18:27:25 +01:00
|
|
|
l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:52 +01:00
|
|
|
/* Check if any of the non-wakeup interrupt GPIOs have changed
|
|
|
|
* state. If so, generate an IRQ by software. This is
|
|
|
|
* horribly racy, but it's the best we can do to work around
|
|
|
|
* this silicon bug. */
|
|
|
|
l ^= bank->saved_datain;
|
2008-12-22 13:27:12 +01:00
|
|
|
l &= bank->enabled_non_wakeup_gpios;
|
2009-08-28 19:51:36 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* No need to generate IRQs for the rising edge for gpio IRQs
|
|
|
|
* configured with falling edge only; and vice versa.
|
|
|
|
*/
|
|
|
|
gen0 = l & bank->saved_fallingdetect;
|
|
|
|
gen0 &= bank->saved_datain;
|
|
|
|
|
|
|
|
gen1 = l & bank->saved_risingdetect;
|
|
|
|
gen1 &= ~(bank->saved_datain);
|
|
|
|
|
|
|
|
/* FIXME: Consider GPIO IRQs with level detections properly! */
|
|
|
|
gen = l & (~(bank->saved_fallingdetect) &
|
|
|
|
~(bank->saved_risingdetect));
|
|
|
|
/* Consider all GPIO IRQs needed to be updated */
|
|
|
|
gen |= gen0 | gen1;
|
|
|
|
|
|
|
|
if (gen) {
|
2006-12-07 02:13:52 +01:00
|
|
|
u32 old0, old1;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2010-03-03 17:21:08 +01:00
|
|
|
if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
|
2010-02-15 18:27:25 +01:00
|
|
|
old0 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
|
old1 = __raw_readl(bank->base +
|
|
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old0 | gen, bank->base +
|
2009-08-28 19:51:36 +02:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old1 | gen, bank->base +
|
2009-08-28 19:51:36 +02:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old0, bank->base +
|
2010-02-15 18:27:25 +01:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT0);
|
2010-03-03 17:21:08 +01:00
|
|
|
__raw_writel(old1, bank->base +
|
2010-02-15 18:27:25 +01:00
|
|
|
OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpu_is_omap44xx()) {
|
|
|
|
old0 = __raw_readl(bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT0);
|
2010-02-15 18:27:25 +01:00
|
|
|
old1 = __raw_readl(bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT1);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old0 | l, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT0);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old1 | l, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT1);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old0, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT0);
|
2010-02-15 18:27:25 +01:00
|
|
|
__raw_writel(old1, bank->base +
|
2009-07-28 15:27:30 +02:00
|
|
|
OMAP4_GPIO_LEVELDETECT1);
|
2010-02-15 18:27:25 +01:00
|
|
|
}
|
2006-12-07 02:13:52 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
#endif
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
2008-09-26 14:17:48 +02:00
|
|
|
/* save the registers of bank 2-6 */
|
|
|
|
void omap_gpio_save_context(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* saving banks from 2-6 only since GPIO1 is in WKUP */
|
|
|
|
for (i = 1; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
gpio_context[i].irqenable1 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
|
|
|
|
gpio_context[i].irqenable2 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
|
|
|
|
gpio_context[i].wake_en =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
|
|
gpio_context[i].ctrl =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
gpio_context[i].oe =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_OE);
|
|
|
|
gpio_context[i].leveldetect0 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
|
gpio_context[i].leveldetect1 =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
gpio_context[i].risingdetect =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
gpio_context[i].fallingdetect =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
gpio_context[i].dataout =
|
|
|
|
__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* restore the required registers of bank 2-6 */
|
|
|
|
void omap_gpio_restore_context(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 1; i < gpio_bank_count; i++) {
|
|
|
|
struct gpio_bank *bank = &gpio_bank[i];
|
|
|
|
__raw_writel(gpio_context[i].irqenable1,
|
|
|
|
bank->base + OMAP24XX_GPIO_IRQENABLE1);
|
|
|
|
__raw_writel(gpio_context[i].irqenable2,
|
|
|
|
bank->base + OMAP24XX_GPIO_IRQENABLE2);
|
|
|
|
__raw_writel(gpio_context[i].wake_en,
|
|
|
|
bank->base + OMAP24XX_GPIO_WAKE_EN);
|
|
|
|
__raw_writel(gpio_context[i].ctrl,
|
|
|
|
bank->base + OMAP24XX_GPIO_CTRL);
|
|
|
|
__raw_writel(gpio_context[i].oe,
|
|
|
|
bank->base + OMAP24XX_GPIO_OE);
|
|
|
|
__raw_writel(gpio_context[i].leveldetect0,
|
|
|
|
bank->base + OMAP24XX_GPIO_LEVELDETECT0);
|
|
|
|
__raw_writel(gpio_context[i].leveldetect1,
|
|
|
|
bank->base + OMAP24XX_GPIO_LEVELDETECT1);
|
|
|
|
__raw_writel(gpio_context[i].risingdetect,
|
|
|
|
bank->base + OMAP24XX_GPIO_RISINGDETECT);
|
|
|
|
__raw_writel(gpio_context[i].fallingdetect,
|
|
|
|
bank->base + OMAP24XX_GPIO_FALLINGDETECT);
|
|
|
|
__raw_writel(gpio_context[i].dataout,
|
|
|
|
bank->base + OMAP24XX_GPIO_DATAOUT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
static struct platform_driver omap_gpio_driver = {
|
|
|
|
.probe = omap_gpio_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "omap_gpio",
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
/*
|
2010-12-08 01:26:57 +01:00
|
|
|
* gpio driver register needs to be done before
|
|
|
|
* machine_init functions access gpio APIs.
|
|
|
|
* Hence omap_gpio_drv_reg() is a postcore_initcall.
|
2005-07-10 20:58:15 +02:00
|
|
|
*/
|
2010-12-08 01:26:57 +01:00
|
|
|
static int __init omap_gpio_drv_reg(void)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-12-08 01:26:57 +01:00
|
|
|
return platform_driver_register(&omap_gpio_driver);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2010-12-08 01:26:57 +01:00
|
|
|
postcore_initcall(omap_gpio_drv_reg);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
static int __init omap_gpio_sysinit(void)
|
|
|
|
{
|
2006-12-07 02:14:11 +01:00
|
|
|
mpuio_init();
|
|
|
|
|
2010-02-12 21:26:48 +01:00
|
|
|
#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
|
2011-04-22 22:02:46 +02:00
|
|
|
if (cpu_is_omap16xx() || cpu_class_is_omap2())
|
|
|
|
register_syscore_ops(&omap_gpio_syscore_ops);
|
2005-09-07 18:20:26 +02:00
|
|
|
#endif
|
|
|
|
|
2011-04-22 22:02:46 +02:00
|
|
|
return 0;
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
arch_initcall(omap_gpio_sysinit);
|