2005-07-10 20:58:15 +02:00
|
|
|
/*
|
|
|
|
* Support functions for OMAP GPIO
|
|
|
|
*
|
2005-09-07 18:20:26 +02:00
|
|
|
* Copyright (C) 2003-2005 Nokia Corporation
|
2007-10-19 23:21:04 +02:00
|
|
|
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
|
2005-07-10 20:58:15 +02:00
|
|
|
*
|
2009-05-28 23:16:04 +02:00
|
|
|
* Copyright (C) 2009 Texas Instruments
|
|
|
|
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|
|
|
*
|
2005-07-10 20:58:15 +02:00
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/interrupt.h>
|
2011-04-22 22:02:46 +02:00
|
|
|
#include <linux/syscore_ops.h>
|
2005-09-07 18:20:26 +02:00
|
|
|
#include <linux/err.h>
|
2006-01-07 17:15:52 +01:00
|
|
|
#include <linux/clk.h>
|
2008-09-06 13:10:45 +02:00
|
|
|
#include <linux/io.h>
|
2012-02-01 16:01:39 +01:00
|
|
|
#include <linux/device.h>
|
2010-12-08 01:26:57 +01:00
|
|
|
#include <linux/pm_runtime.h>
|
2011-09-29 03:53:22 +02:00
|
|
|
#include <linux/pm.h>
|
2011-08-16 11:53:02 +02:00
|
|
|
#include <linux/of.h>
|
|
|
|
#include <linux/of_device.h>
|
|
|
|
#include <linux/irqdomain.h>
|
2013-01-18 16:31:37 +01:00
|
|
|
#include <linux/irqchip/chained_irq.h>
|
2012-08-31 00:37:24 +02:00
|
|
|
#include <linux/gpio.h>
|
|
|
|
#include <linux/platform_data/gpio-omap.h>
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
#define OFF_MODE 1
|
|
|
|
|
2011-05-05 16:28:01 +02:00
|
|
|
static LIST_HEAD(omap_gpio_list);
|
|
|
|
|
2011-04-18 17:06:51 +02:00
|
|
|
struct gpio_regs {
|
|
|
|
u32 irqenable1;
|
|
|
|
u32 irqenable2;
|
|
|
|
u32 wake_en;
|
|
|
|
u32 ctrl;
|
|
|
|
u32 oe;
|
|
|
|
u32 leveldetect0;
|
|
|
|
u32 leveldetect1;
|
|
|
|
u32 risingdetect;
|
|
|
|
u32 fallingdetect;
|
|
|
|
u32 dataout;
|
2011-09-09 15:38:58 +02:00
|
|
|
u32 debounce;
|
|
|
|
u32 debounce_en;
|
2011-04-18 17:06:51 +02:00
|
|
|
};
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
struct gpio_bank {
|
2011-05-05 16:28:01 +02:00
|
|
|
struct list_head node;
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *base;
|
2005-07-10 20:58:15 +02:00
|
|
|
u16 irq;
|
2011-08-16 11:53:02 +02:00
|
|
|
struct irq_domain *domain;
|
2006-12-07 02:13:52 +01:00
|
|
|
u32 non_wakeup_gpios;
|
|
|
|
u32 enabled_non_wakeup_gpios;
|
2011-04-18 17:06:51 +02:00
|
|
|
struct gpio_regs context;
|
2006-12-07 02:13:52 +01:00
|
|
|
u32 saved_datain;
|
2008-01-17 06:56:15 +01:00
|
|
|
u32 level_mask;
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
u32 toggle_mask;
|
2005-07-10 20:58:15 +02:00
|
|
|
spinlock_t lock;
|
2008-03-03 21:43:23 +01:00
|
|
|
struct gpio_chip chip;
|
2008-12-11 02:35:24 +01:00
|
|
|
struct clk *dbck;
|
2009-11-22 19:11:25 +01:00
|
|
|
u32 mod_usage;
|
2009-01-27 20:15:34 +01:00
|
|
|
u32 dbck_enable_mask;
|
2011-11-23 22:33:28 +01:00
|
|
|
bool dbck_enabled;
|
2010-12-08 01:26:57 +01:00
|
|
|
struct device *dev;
|
2011-08-30 20:32:21 +02:00
|
|
|
bool is_mpuio;
|
2010-12-08 01:26:57 +01:00
|
|
|
bool dbck_flag;
|
2011-05-05 16:45:16 +02:00
|
|
|
bool loses_context;
|
2013-04-15 20:06:54 +02:00
|
|
|
bool context_valid;
|
2010-12-08 01:26:58 +01:00
|
|
|
int stride;
|
2011-04-21 18:23:00 +02:00
|
|
|
u32 width;
|
2011-09-29 01:17:25 +02:00
|
|
|
int context_loss_count;
|
2011-11-23 22:14:29 +01:00
|
|
|
int power_mode;
|
|
|
|
bool workaround_enabled;
|
2011-04-21 01:31:23 +02:00
|
|
|
|
|
|
|
void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
|
2011-09-29 01:17:25 +02:00
|
|
|
int (*get_context_loss_count)(struct device *dev);
|
2011-04-21 01:31:23 +02:00
|
|
|
|
|
|
|
struct omap_gpio_reg_offs *regs;
|
2005-07-10 20:58:15 +02:00
|
|
|
};
|
|
|
|
|
2011-04-22 16:59:07 +02:00
|
|
|
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
|
|
|
|
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
|
2011-05-02 11:51:42 +02:00
|
|
|
#define GPIO_MOD_CTRL_BIT BIT(0)
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2012-02-23 21:50:10 +01:00
|
|
|
static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
|
|
|
|
{
|
2013-03-01 18:22:47 +01:00
|
|
|
return bank->chip.base + gpio_irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
|
|
|
|
return irq_find_mapping(bank->domain, offset);
|
2012-02-23 21:50:10 +01:00
|
|
|
}
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
|
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 l;
|
|
|
|
|
2011-04-21 01:31:23 +02:00
|
|
|
reg += bank->regs->direction;
|
2005-07-10 20:58:15 +02:00
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (is_input)
|
|
|
|
l |= 1 << gpio;
|
|
|
|
else
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
__raw_writel(l, reg);
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.oe = l;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2011-04-21 01:31:23 +02:00
|
|
|
|
|
|
|
/* set data out value using dedicate set/clear register */
|
|
|
|
static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2011-04-21 01:31:23 +02:00
|
|
|
u32 l = GPIO_BIT(bank, gpio);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2012-03-02 08:22:52 +01:00
|
|
|
if (enable) {
|
2011-04-21 01:31:23 +02:00
|
|
|
reg += bank->regs->set_dataout;
|
2012-03-02 08:22:52 +01:00
|
|
|
bank->context.dataout |= l;
|
|
|
|
} else {
|
2011-04-21 01:31:23 +02:00
|
|
|
reg += bank->regs->clr_dataout;
|
2012-03-02 08:22:52 +01:00
|
|
|
bank->context.dataout &= ~l;
|
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
2011-04-21 01:31:23 +02:00
|
|
|
/* set data out value using mask register */
|
|
|
|
static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2011-04-21 01:31:23 +02:00
|
|
|
void __iomem *reg = bank->base + bank->regs->dataout;
|
|
|
|
u32 gpio_bit = GPIO_BIT(bank, gpio);
|
|
|
|
u32 l;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-04-21 01:31:23 +02:00
|
|
|
l = __raw_readl(reg);
|
|
|
|
if (enable)
|
|
|
|
l |= gpio_bit;
|
|
|
|
else
|
|
|
|
l &= ~gpio_bit;
|
2005-07-10 20:58:15 +02:00
|
|
|
__raw_writel(l, reg);
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.dataout = l;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
gpio/omap: fix redundant decoding of gpio offset
In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.
Here is Russell's original comment:
Can someone explain to me this:
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
void __iomem *reg = bank->base + bank->regs->datain;
return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *reg = bank->base;
int gpio = chip->base + offset;
u32 mask = GPIO_BIT(bank, gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?
Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.
However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.
Surely this kind of behaviour is not intended?
Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-27 07:16:09 +01:00
|
|
|
static int _get_gpio_datain(struct gpio_bank *bank, int offset)
|
2009-08-05 15:53:24 +02:00
|
|
|
{
|
2011-04-21 01:31:23 +02:00
|
|
|
void __iomem *reg = bank->base + bank->regs->datain;
|
2009-08-05 15:53:24 +02:00
|
|
|
|
gpio/omap: fix redundant decoding of gpio offset
In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.
Here is Russell's original comment:
Can someone explain to me this:
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
void __iomem *reg = bank->base + bank->regs->datain;
return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *reg = bank->base;
int gpio = chip->base + offset;
u32 mask = GPIO_BIT(bank, gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?
Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.
However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.
Surely this kind of behaviour is not intended?
Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-27 07:16:09 +01:00
|
|
|
return (__raw_readl(reg) & (1 << offset)) != 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2009-08-05 15:53:24 +02:00
|
|
|
|
gpio/omap: fix redundant decoding of gpio offset
In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.
Here is Russell's original comment:
Can someone explain to me this:
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
void __iomem *reg = bank->base + bank->regs->datain;
return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *reg = bank->base;
int gpio = chip->base + offset;
u32 mask = GPIO_BIT(bank, gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?
Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.
However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.
Surely this kind of behaviour is not intended?
Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-27 07:16:09 +01:00
|
|
|
static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
|
2009-08-05 15:53:24 +02:00
|
|
|
{
|
2011-04-21 01:31:23 +02:00
|
|
|
void __iomem *reg = bank->base + bank->regs->dataout;
|
2009-08-05 15:53:24 +02:00
|
|
|
|
gpio/omap: fix redundant decoding of gpio offset
In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.
Here is Russell's original comment:
Can someone explain to me this:
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
void __iomem *reg = bank->base + bank->regs->datain;
return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *reg = bank->base;
int gpio = chip->base + offset;
u32 mask = GPIO_BIT(bank, gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?
Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.
However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.
Surely this kind of behaviour is not intended?
Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-27 07:16:09 +01:00
|
|
|
return (__raw_readl(reg) & (1 << offset)) != 0;
|
2009-08-05 15:53:24 +02:00
|
|
|
}
|
|
|
|
|
2011-07-12 17:18:15 +02:00
|
|
|
static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
|
|
|
|
{
|
|
|
|
int l = __raw_readl(base + reg);
|
|
|
|
|
2012-02-01 15:58:56 +01:00
|
|
|
if (set)
|
2011-07-12 17:18:15 +02:00
|
|
|
l |= mask;
|
|
|
|
else
|
|
|
|
l &= ~mask;
|
|
|
|
|
|
|
|
__raw_writel(l, base + reg);
|
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2011-11-23 22:33:28 +01:00
|
|
|
static inline void _gpio_dbck_enable(struct gpio_bank *bank)
|
|
|
|
{
|
|
|
|
if (bank->dbck_enable_mask && !bank->dbck_enabled) {
|
|
|
|
clk_enable(bank->dbck);
|
|
|
|
bank->dbck_enabled = true;
|
2012-06-16 21:01:25 +02:00
|
|
|
|
|
|
|
__raw_writel(bank->dbck_enable_mask,
|
|
|
|
bank->base + bank->regs->debounce_en);
|
2011-11-23 22:33:28 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void _gpio_dbck_disable(struct gpio_bank *bank)
|
|
|
|
{
|
|
|
|
if (bank->dbck_enable_mask && bank->dbck_enabled) {
|
2012-06-16 21:01:25 +02:00
|
|
|
/*
|
|
|
|
* Disable debounce before cutting it's clock. If debounce is
|
|
|
|
* enabled but the clock is not, GPIO module seems to be unable
|
|
|
|
* to detect events and generate interrupts at least on OMAP3.
|
|
|
|
*/
|
|
|
|
__raw_writel(0, bank->base + bank->regs->debounce_en);
|
|
|
|
|
2011-11-23 22:33:28 +01:00
|
|
|
clk_disable(bank->dbck);
|
|
|
|
bank->dbck_enabled = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-05-26 23:42:23 +02:00
|
|
|
/**
|
|
|
|
* _set_gpio_debounce - low level gpio debounce time
|
|
|
|
* @bank: the gpio bank we're acting upon
|
|
|
|
* @gpio: the gpio number on this @gpio
|
|
|
|
* @debounce: debounce time to use
|
|
|
|
*
|
|
|
|
* OMAP's debounce time is in 31us steps so we need
|
|
|
|
* to convert and round up to the closest unit.
|
|
|
|
*/
|
|
|
|
static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
|
|
|
|
unsigned debounce)
|
|
|
|
{
|
2011-04-22 21:02:05 +02:00
|
|
|
void __iomem *reg;
|
2010-05-26 23:42:23 +02:00
|
|
|
u32 val;
|
|
|
|
u32 l;
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
if (!bank->dbck_flag)
|
|
|
|
return;
|
|
|
|
|
2010-05-26 23:42:23 +02:00
|
|
|
if (debounce < 32)
|
|
|
|
debounce = 0x01;
|
|
|
|
else if (debounce > 7936)
|
|
|
|
debounce = 0xff;
|
|
|
|
else
|
|
|
|
debounce = (debounce / 0x1f) - 1;
|
|
|
|
|
2011-04-22 16:59:07 +02:00
|
|
|
l = GPIO_BIT(bank, gpio);
|
2010-05-26 23:42:23 +02:00
|
|
|
|
2011-11-23 23:28:54 +01:00
|
|
|
clk_enable(bank->dbck);
|
2011-04-22 21:02:05 +02:00
|
|
|
reg = bank->base + bank->regs->debounce;
|
2010-05-26 23:42:23 +02:00
|
|
|
__raw_writel(debounce, reg);
|
|
|
|
|
2011-04-22 21:02:05 +02:00
|
|
|
reg = bank->base + bank->regs->debounce_en;
|
2010-05-26 23:42:23 +02:00
|
|
|
val = __raw_readl(reg);
|
|
|
|
|
2011-11-23 23:28:54 +01:00
|
|
|
if (debounce)
|
2010-05-26 23:42:23 +02:00
|
|
|
val |= l;
|
2011-11-23 23:28:54 +01:00
|
|
|
else
|
2010-05-26 23:42:23 +02:00
|
|
|
val &= ~l;
|
2010-06-09 12:53:07 +02:00
|
|
|
bank->dbck_enable_mask = val;
|
2010-05-26 23:42:23 +02:00
|
|
|
|
|
|
|
__raw_writel(val, reg);
|
2011-11-23 23:28:54 +01:00
|
|
|
clk_disable(bank->dbck);
|
|
|
|
/*
|
|
|
|
* Enable debounce clock per module.
|
|
|
|
* This call is mandatory because in omap_gpio_request() when
|
|
|
|
* *_runtime_get_sync() is called, _gpio_dbck_enable() within
|
|
|
|
* runtime callbck fails to turn on dbck because dbck_enable_mask
|
|
|
|
* used within _gpio_dbck_enable() is still not initialized at
|
|
|
|
* that point. Therefore we have to enable dbck here.
|
|
|
|
*/
|
|
|
|
_gpio_dbck_enable(bank);
|
2011-09-09 15:38:58 +02:00
|
|
|
if (bank->dbck_enable_mask) {
|
|
|
|
bank->context.debounce = debounce;
|
|
|
|
bank->context.debounce_en = val;
|
|
|
|
}
|
2010-05-26 23:42:23 +02:00
|
|
|
}
|
|
|
|
|
gpio/omap: fix off-mode bug: clear debounce settings on free/reset
This change was originally titled "gpio/omap: fix off-mode bug: clear debounce
clock enable mask on free/reset". The title has been updated slightly to
reflect (what should be) the final fix.
When a GPIO is freed or shutdown, we need to ensure that any debounce settings
are cleared and if the GPIO is the only GPIO in the bank that is currently
using debounce, then disable the debounce clock as well to save power.
Currently, the debounce settings are not cleared on a GPIO free or shutdown and
so during a context restore on subsequent off-mode transition, the previous
debounce values are restored from the shadow copies (bank->context.debounce*)
leading to mismatch state between driver state and hardware state.
This was discovered when board code was doing
gpio_request_one()
gpio_set_debounce()
gpio_free()
which was leaving the GPIO debounce settings in a confused state. If that GPIO
bank is subsequently used with off-mode enabled, bogus state would be restored,
leaving GPIO debounce enabled which then prevented the CORE powerdomain from
transitioning.
To fix this, introduce a new function called _clear_gpio_debounce() to clear
any debounce settings when the GPIO is freed or shutdown. If this GPIO is the
last debounce-enabled GPIO in the bank, the debounce will also be cut.
Please note that we cannot use _gpio_dbck_disable() to disable the debounce
clock because this has been specifically created for the gpio suspend path
and is intended to shutdown the debounce clock while debounce is enabled.
Special thanks to Kevin Hilman for root causing the bug. This fix is a
collaborative effort with inputs from Kevin Hilman, Grazvydas Ignotas and
Santosh Shilimkar.
Testing:
- This has been unit tested on an OMAP3430 Beagle board, by requesting a gpio,
enabling debounce and then freeing the gpio and checking the register
contents, the saved register context and the debounce clock state.
- Kevin Hilman tested on 37xx/EVM board which configures GPIO debounce for the
ads7846 touchscreen in its board file using the above sequence, and so was
failing off-mode tests in dynamic idle. Verified that off-mode tests are
passing with this patch.
V5 changes:
- Corrected author
Reported-by: Paul Walmsley <paul@pwsan.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-26 21:26:04 +02:00
|
|
|
/**
|
|
|
|
* _clear_gpio_debounce - clear debounce settings for a gpio
|
|
|
|
* @bank: the gpio bank we're acting upon
|
|
|
|
* @gpio: the gpio number on this @gpio
|
|
|
|
*
|
|
|
|
* If a gpio is using debounce, then clear the debounce enable bit and if
|
|
|
|
* this is the only gpio in this bank using debounce, then clear the debounce
|
|
|
|
* time too. The debounce clock will also be disabled when calling this function
|
|
|
|
* if this is the only gpio in the bank using debounce.
|
|
|
|
*/
|
|
|
|
static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
|
|
|
|
{
|
|
|
|
u32 gpio_bit = GPIO_BIT(bank, gpio);
|
|
|
|
|
|
|
|
if (!bank->dbck_flag)
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!(bank->dbck_enable_mask & gpio_bit))
|
|
|
|
return;
|
|
|
|
|
|
|
|
bank->dbck_enable_mask &= ~gpio_bit;
|
|
|
|
bank->context.debounce_en &= ~gpio_bit;
|
|
|
|
__raw_writel(bank->context.debounce_en,
|
|
|
|
bank->base + bank->regs->debounce_en);
|
|
|
|
|
|
|
|
if (!bank->dbck_enable_mask) {
|
|
|
|
bank->context.debounce = 0;
|
|
|
|
__raw_writel(bank->context.debounce, bank->base +
|
|
|
|
bank->regs->debounce);
|
|
|
|
clk_disable(bank->dbck);
|
|
|
|
bank->dbck_enabled = false;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-09-13 11:32:14 +02:00
|
|
|
static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
|
gpio/omap: fix trigger type to unsigned
The GPIO trigger parameter is of type unsigned.
enum {
IRQ_TYPE_NONE = 0x00000000,
IRQ_TYPE_EDGE_RISING = 0x00000001,
IRQ_TYPE_EDGE_FALLING = 0x00000002,
IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
IRQ_TYPE_LEVEL_HIGH = 0x00000004,
IRQ_TYPE_LEVEL_LOW = 0x00000008,
IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
IRQ_TYPE_SENSE_MASK = 0x0000000f,
IRQ_TYPE_PROBE = 0x00000010,
...
};
Even though gpio_irq_type(struct irq_data *d, unsigned type) has the right type
of parameter, the subsequent called functions set_gpio_triggering() and
set_gpio_trigger() wrongly makes it signed integer. Fix this.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-11-25 11:11:06 +01:00
|
|
|
unsigned trigger)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2006-12-07 02:13:52 +01:00
|
|
|
void __iomem *base = bank->base;
|
2005-09-07 18:20:26 +02:00
|
|
|
u32 gpio_bit = 1 << gpio;
|
|
|
|
|
2011-09-13 11:32:14 +02:00
|
|
|
_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_LEVEL_LOW);
|
|
|
|
_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_LEVEL_HIGH);
|
|
|
|
_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_RISING);
|
|
|
|
_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
|
|
|
|
trigger & IRQ_TYPE_EDGE_FALLING);
|
|
|
|
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.leveldetect0 =
|
|
|
|
__raw_readl(bank->base + bank->regs->leveldetect0);
|
|
|
|
bank->context.leveldetect1 =
|
|
|
|
__raw_readl(bank->base + bank->regs->leveldetect1);
|
|
|
|
bank->context.risingdetect =
|
|
|
|
__raw_readl(bank->base + bank->regs->risingdetect);
|
|
|
|
bank->context.fallingdetect =
|
|
|
|
__raw_readl(bank->base + bank->regs->fallingdetect);
|
|
|
|
|
|
|
|
if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
|
2011-09-13 11:32:14 +02:00
|
|
|
_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.wake_en =
|
|
|
|
__raw_readl(bank->base + bank->regs->wkup_en);
|
|
|
|
}
|
2011-09-13 11:32:14 +02:00
|
|
|
|
2011-06-15 22:40:45 +02:00
|
|
|
/* This part needs to be executed always for OMAP{34xx, 44xx} */
|
2011-09-13 11:32:14 +02:00
|
|
|
if (!bank->regs->irqctrl) {
|
|
|
|
/* On omap24xx proceed only when valid GPIO bit is set */
|
|
|
|
if (bank->non_wakeup_gpios) {
|
|
|
|
if (!(bank->non_wakeup_gpios & gpio_bit))
|
|
|
|
goto exit;
|
|
|
|
}
|
|
|
|
|
2009-06-24 19:13:39 +02:00
|
|
|
/*
|
|
|
|
* Log the edge gpio and manually trigger the IRQ
|
|
|
|
* after resume if the input level changes
|
|
|
|
* to avoid irq lost during PER RET/OFF mode
|
|
|
|
* Applies for omap2 non-wakeup gpio and all omap3 gpios
|
|
|
|
*/
|
|
|
|
if (trigger & IRQ_TYPE_EDGE_BOTH)
|
2006-12-07 02:13:52 +01:00
|
|
|
bank->enabled_non_wakeup_gpios |= gpio_bit;
|
|
|
|
else
|
|
|
|
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
|
|
|
|
}
|
2007-05-05 20:40:29 +02:00
|
|
|
|
2011-09-13 11:32:14 +02:00
|
|
|
exit:
|
2011-08-30 11:35:44 +02:00
|
|
|
bank->level_mask =
|
|
|
|
__raw_readl(bank->base + bank->regs->leveldetect0) |
|
|
|
|
__raw_readl(bank->base + bank->regs->leveldetect1);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
|
2010-01-29 23:20:05 +01:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
/*
|
|
|
|
* This only applies to chips that can't do both rising and falling edge
|
|
|
|
* detection at once. For all other chips, this function is a noop.
|
|
|
|
*/
|
|
|
|
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
u32 l = 0;
|
|
|
|
|
2011-09-13 11:32:14 +02:00
|
|
|
if (!bank->regs->irqctrl)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
return;
|
2011-09-13 11:32:14 +02:00
|
|
|
|
|
|
|
reg += bank->regs->irqctrl;
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
if ((l >> gpio) & 1)
|
|
|
|
l &= ~(1 << gpio);
|
|
|
|
else
|
|
|
|
l |= 1 << gpio;
|
|
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
2011-09-13 11:32:14 +02:00
|
|
|
#else
|
|
|
|
static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
|
2010-01-29 23:20:05 +01:00
|
|
|
#endif
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
|
gpio/omap: fix trigger type to unsigned
The GPIO trigger parameter is of type unsigned.
enum {
IRQ_TYPE_NONE = 0x00000000,
IRQ_TYPE_EDGE_RISING = 0x00000001,
IRQ_TYPE_EDGE_FALLING = 0x00000002,
IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
IRQ_TYPE_LEVEL_HIGH = 0x00000004,
IRQ_TYPE_LEVEL_LOW = 0x00000008,
IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
IRQ_TYPE_SENSE_MASK = 0x0000000f,
IRQ_TYPE_PROBE = 0x00000010,
...
};
Even though gpio_irq_type(struct irq_data *d, unsigned type) has the right type
of parameter, the subsequent called functions set_gpio_triggering() and
set_gpio_trigger() wrongly makes it signed integer. Fix this.
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2011-11-25 11:11:06 +01:00
|
|
|
static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
|
|
|
|
unsigned trigger)
|
2005-09-07 18:20:26 +02:00
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
2011-09-13 11:32:14 +02:00
|
|
|
void __iomem *base = bank->base;
|
2005-09-07 18:20:26 +02:00
|
|
|
u32 l = 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-09-13 11:32:14 +02:00
|
|
|
if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
|
|
|
|
set_gpio_trigger(bank, gpio, trigger);
|
|
|
|
} else if (bank->regs->irqctrl) {
|
|
|
|
reg += bank->regs->irqctrl;
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
l = __raw_readl(reg);
|
2010-04-05 13:38:06 +02:00
|
|
|
if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
bank->toggle_mask |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l |= 1 << gpio;
|
2008-07-27 05:23:31 +02:00
|
|
|
else if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2005-07-10 20:58:15 +02:00
|
|
|
l &= ~(1 << gpio);
|
2005-09-07 18:20:26 +02:00
|
|
|
else
|
2011-09-13 11:32:14 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
} else if (bank->regs->edgectrl1) {
|
2005-07-10 20:58:15 +02:00
|
|
|
if (gpio & 0x08)
|
2011-09-13 11:32:14 +02:00
|
|
|
reg += bank->regs->edgectrl2;
|
2005-07-10 20:58:15 +02:00
|
|
|
else
|
2011-09-13 11:32:14 +02:00
|
|
|
reg += bank->regs->edgectrl1;
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
gpio &= 0x07;
|
|
|
|
l = __raw_readl(reg);
|
|
|
|
l &= ~(3 << (gpio << 1));
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_RISING)
|
2006-04-02 18:46:23 +02:00
|
|
|
l |= 2 << (gpio << 1);
|
2008-07-27 05:23:31 +02:00
|
|
|
if (trigger & IRQ_TYPE_EDGE_FALLING)
|
2006-04-02 18:46:23 +02:00
|
|
|
l |= 1 << (gpio << 1);
|
2011-09-13 11:32:14 +02:00
|
|
|
|
|
|
|
/* Enable wake-up during idle for dynamic tick */
|
|
|
|
_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.wake_en =
|
|
|
|
__raw_readl(bank->base + bank->regs->wkup_en);
|
2011-09-13 11:32:14 +02:00
|
|
|
__raw_writel(l, reg);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
return 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static int gpio_irq_type(struct irq_data *d, unsigned type)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2012-02-23 21:50:10 +01:00
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2012-08-31 00:37:24 +02:00
|
|
|
unsigned gpio = 0;
|
2005-09-07 18:20:26 +02:00
|
|
|
int retval;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2013-03-01 18:22:48 +01:00
|
|
|
if (WARN_ON(!bank->mod_usage))
|
|
|
|
return -EINVAL;
|
|
|
|
|
2012-08-31 00:37:24 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
if (d->irq > IH_MPUIO_BASE)
|
2010-11-29 11:17:17 +01:00
|
|
|
gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
|
2012-08-31 00:37:24 +02:00
|
|
|
#endif
|
|
|
|
|
|
|
|
if (!gpio)
|
2013-03-01 18:22:47 +01:00
|
|
|
gpio = irq_to_gpio(bank, d->hwirq);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
if (type & ~IRQ_TYPE_SENSE_MASK)
|
2006-04-02 18:46:23 +02:00
|
|
|
return -EINVAL;
|
2006-12-07 02:13:59 +01:00
|
|
|
|
2011-08-30 11:35:44 +02:00
|
|
|
if (!bank->regs->leveldetect0 &&
|
|
|
|
(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
|
2005-09-07 18:20:26 +02:00
|
|
|
return -EINVAL;
|
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2011-04-22 16:59:07 +02:00
|
|
|
retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2008-01-17 06:56:16 +01:00
|
|
|
|
|
|
|
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
|
2011-03-24 13:25:22 +01:00
|
|
|
__irq_set_handler_locked(d->irq, handle_level_irq);
|
2008-01-17 06:56:16 +01:00
|
|
|
else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
|
2011-03-24 13:25:22 +01:00
|
|
|
__irq_set_handler_locked(d->irq, handle_edge_irq);
|
2008-01-17 06:56:16 +01:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
return retval;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-04-21 18:17:35 +02:00
|
|
|
reg += bank->regs->irqstatus;
|
2005-07-10 20:58:15 +02:00
|
|
|
__raw_writel(gpio_mask, reg);
|
2006-09-25 11:41:46 +02:00
|
|
|
|
|
|
|
/* Workaround for clearing DSP GPIO interrupts to allow retention */
|
2011-04-21 18:17:35 +02:00
|
|
|
if (bank->regs->irqstatus2) {
|
|
|
|
reg = bank->base + bank->regs->irqstatus2;
|
2009-04-23 20:10:50 +02:00
|
|
|
__raw_writel(gpio_mask, reg);
|
2011-04-21 18:17:35 +02:00
|
|
|
}
|
2009-04-23 20:10:50 +02:00
|
|
|
|
|
|
|
/* Flush posted write for the irq status to avoid spurious interrupts */
|
|
|
|
__raw_readl(reg);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
2011-04-22 16:59:07 +02:00
|
|
|
_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
2006-06-27 01:16:07 +02:00
|
|
|
u32 l;
|
2011-04-21 18:33:36 +02:00
|
|
|
u32 mask = (1 << bank->width) - 1;
|
2006-06-27 01:16:00 +02:00
|
|
|
|
2011-04-21 18:53:06 +02:00
|
|
|
reg += bank->regs->irqenable;
|
2006-06-27 01:16:07 +02:00
|
|
|
l = __raw_readl(reg);
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->irqenable_inv)
|
2006-06-27 01:16:07 +02:00
|
|
|
l = ~l;
|
|
|
|
l &= mask;
|
|
|
|
return l;
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
|
|
|
|
2011-04-21 18:53:06 +02:00
|
|
|
static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *reg = bank->base;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 l;
|
|
|
|
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->set_irqenable) {
|
|
|
|
reg += bank->regs->set_irqenable;
|
|
|
|
l = gpio_mask;
|
2012-03-06 07:38:16 +01:00
|
|
|
bank->context.irqenable1 |= gpio_mask;
|
2011-04-21 18:53:06 +02:00
|
|
|
} else {
|
|
|
|
reg += bank->regs->irqenable;
|
2005-07-10 20:58:15 +02:00
|
|
|
l = __raw_readl(reg);
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->irqenable_inv)
|
|
|
|
l &= ~gpio_mask;
|
2005-07-10 20:58:15 +02:00
|
|
|
else
|
|
|
|
l |= gpio_mask;
|
2012-03-06 07:38:16 +01:00
|
|
|
bank->context.irqenable1 = l;
|
2011-04-21 18:53:06 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
|
|
|
|
{
|
|
|
|
void __iomem *reg = bank->base;
|
|
|
|
u32 l;
|
|
|
|
|
|
|
|
if (bank->regs->clr_irqenable) {
|
|
|
|
reg += bank->regs->clr_irqenable;
|
2005-07-10 20:58:15 +02:00
|
|
|
l = gpio_mask;
|
2012-03-06 07:38:16 +01:00
|
|
|
bank->context.irqenable1 &= ~gpio_mask;
|
2011-04-21 18:53:06 +02:00
|
|
|
} else {
|
|
|
|
reg += bank->regs->irqenable;
|
2009-03-24 02:07:40 +01:00
|
|
|
l = __raw_readl(reg);
|
2011-04-21 18:53:06 +02:00
|
|
|
if (bank->regs->irqenable_inv)
|
2009-03-24 02:07:40 +01:00
|
|
|
l |= gpio_mask;
|
2005-09-07 18:20:26 +02:00
|
|
|
else
|
2011-04-21 18:53:06 +02:00
|
|
|
l &= ~gpio_mask;
|
2012-03-06 07:38:16 +01:00
|
|
|
bank->context.irqenable1 = l;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2011-04-21 18:53:06 +02:00
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
__raw_writel(l, reg);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
|
|
|
|
{
|
2011-11-25 10:57:37 +01:00
|
|
|
if (enable)
|
|
|
|
_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
|
|
|
|
else
|
|
|
|
_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/*
|
|
|
|
* Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
|
|
|
|
* 1510 does not seem to have a wake-up register. If JTAG is connected
|
|
|
|
* to the target, system will wake up always on GPIO events. While
|
|
|
|
* system is running all registered GPIO interrupts need to have wake-up
|
|
|
|
* enabled. When system is suspended, only selected GPIO interrupts need
|
|
|
|
* to have wake-up enabled.
|
|
|
|
*/
|
|
|
|
static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
|
|
|
|
{
|
2011-04-22 18:45:27 +02:00
|
|
|
u32 gpio_bit = GPIO_BIT(bank, gpio);
|
|
|
|
unsigned long flags;
|
2008-03-03 13:33:30 +01:00
|
|
|
|
2011-04-22 18:45:27 +02:00
|
|
|
if (bank->non_wakeup_gpios & gpio_bit) {
|
2012-02-01 15:58:56 +01:00
|
|
|
dev_err(bank->dev,
|
2011-04-22 18:45:27 +02:00
|
|
|
"Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
|
2005-09-07 18:20:26 +02:00
|
|
|
return -EINVAL;
|
|
|
|
}
|
2011-04-22 18:45:27 +02:00
|
|
|
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
if (enable)
|
2012-04-27 16:13:33 +02:00
|
|
|
bank->context.wake_en |= gpio_bit;
|
2011-04-22 18:45:27 +02:00
|
|
|
else
|
2012-04-27 16:13:33 +02:00
|
|
|
bank->context.wake_en &= ~gpio_bit;
|
2011-04-22 18:45:27 +02:00
|
|
|
|
2012-04-27 16:13:33 +02:00
|
|
|
__raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
|
2011-04-22 18:45:27 +02:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
|
2006-09-25 11:41:38 +02:00
|
|
|
static void _reset_gpio(struct gpio_bank *bank, int gpio)
|
|
|
|
{
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
|
2006-09-25 11:41:38 +02:00
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
|
gpio/omap: fix off-mode bug: clear debounce settings on free/reset
This change was originally titled "gpio/omap: fix off-mode bug: clear debounce
clock enable mask on free/reset". The title has been updated slightly to
reflect (what should be) the final fix.
When a GPIO is freed or shutdown, we need to ensure that any debounce settings
are cleared and if the GPIO is the only GPIO in the bank that is currently
using debounce, then disable the debounce clock as well to save power.
Currently, the debounce settings are not cleared on a GPIO free or shutdown and
so during a context restore on subsequent off-mode transition, the previous
debounce values are restored from the shadow copies (bank->context.debounce*)
leading to mismatch state between driver state and hardware state.
This was discovered when board code was doing
gpio_request_one()
gpio_set_debounce()
gpio_free()
which was leaving the GPIO debounce settings in a confused state. If that GPIO
bank is subsequently used with off-mode enabled, bogus state would be restored,
leaving GPIO debounce enabled which then prevented the CORE powerdomain from
transitioning.
To fix this, introduce a new function called _clear_gpio_debounce() to clear
any debounce settings when the GPIO is freed or shutdown. If this GPIO is the
last debounce-enabled GPIO in the bank, the debounce will also be cut.
Please note that we cannot use _gpio_dbck_disable() to disable the debounce
clock because this has been specifically created for the gpio suspend path
and is intended to shutdown the debounce clock while debounce is enabled.
Special thanks to Kevin Hilman for root causing the bug. This fix is a
collaborative effort with inputs from Kevin Hilman, Grazvydas Ignotas and
Santosh Shilimkar.
Testing:
- This has been unit tested on an OMAP3430 Beagle board, by requesting a gpio,
enabling debounce and then freeing the gpio and checking the register
contents, the saved register context and the debounce clock state.
- Kevin Hilman tested on 37xx/EVM board which configures GPIO debounce for the
ads7846 touchscreen in its board file using the above sequence, and so was
failing off-mode tests in dynamic idle. Verified that off-mode tests are
passing with this patch.
V5 changes:
- Corrected author
Reported-by: Paul Walmsley <paul@pwsan.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2012-10-26 21:26:04 +02:00
|
|
|
_clear_gpio_debounce(bank, gpio);
|
2006-09-25 11:41:38 +02:00
|
|
|
}
|
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
|
2010-11-29 11:17:17 +01:00
|
|
|
static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
|
2005-09-07 18:20:26 +02:00
|
|
|
{
|
2012-02-23 21:50:10 +01:00
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2013-03-01 18:22:47 +01:00
|
|
|
unsigned int gpio = irq_to_gpio(bank, d->hwirq);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2012-02-23 21:50:10 +01:00
|
|
|
return _set_gpio_wakeup(bank, gpio, enable);
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:27 +01:00
|
|
|
static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2008-12-11 02:35:27 +01:00
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2008-03-03 21:43:23 +01:00
|
|
|
|
2011-09-29 03:53:22 +02:00
|
|
|
/*
|
|
|
|
* If this is the first gpio_request for the bank,
|
|
|
|
* enable the bank module.
|
|
|
|
*/
|
|
|
|
if (!bank->mod_usage)
|
|
|
|
pm_runtime_get_sync(bank->dev);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2011-09-29 03:53:22 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2006-09-25 11:41:38 +02:00
|
|
|
/* Set trigger to none. You need to enable the desired trigger with
|
|
|
|
* request_irq() or set_irq_type().
|
|
|
|
*/
|
2008-12-11 02:35:27 +01:00
|
|
|
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2011-05-25 07:53:50 +02:00
|
|
|
if (bank->regs->pinctrl) {
|
|
|
|
void __iomem *reg = bank->base + bank->regs->pinctrl;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2005-09-07 18:20:26 +02:00
|
|
|
/* Claim the pin for MPU */
|
2008-12-11 02:35:27 +01:00
|
|
|
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2011-05-25 07:53:50 +02:00
|
|
|
|
2011-05-02 11:51:42 +02:00
|
|
|
if (bank->regs->ctrl && !bank->mod_usage) {
|
|
|
|
void __iomem *reg = bank->base + bank->regs->ctrl;
|
|
|
|
u32 ctrl;
|
|
|
|
|
|
|
|
ctrl = __raw_readl(reg);
|
|
|
|
/* Module is enabled, clocks are not gated */
|
|
|
|
ctrl &= ~GPIO_MOD_CTRL_BIT;
|
|
|
|
__raw_writel(ctrl, reg);
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.ctrl = ctrl;
|
2009-11-22 19:11:25 +01:00
|
|
|
}
|
2011-05-02 11:51:42 +02:00
|
|
|
|
|
|
|
bank->mod_usage |= 1 << offset;
|
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-11 02:35:27 +01:00
|
|
|
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2008-12-11 02:35:27 +01:00
|
|
|
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
|
2011-09-13 11:11:44 +02:00
|
|
|
void __iomem *base = bank->base;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2011-09-13 11:11:44 +02:00
|
|
|
|
2011-11-15 08:22:38 +01:00
|
|
|
if (bank->regs->wkup_en) {
|
2010-05-14 21:05:27 +02:00
|
|
|
/* Disable wake-up during idle for dynamic tick */
|
2011-09-13 11:11:44 +02:00
|
|
|
_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.wake_en =
|
|
|
|
__raw_readl(bank->base + bank->regs->wkup_en);
|
|
|
|
}
|
2011-09-13 11:11:44 +02:00
|
|
|
|
2011-05-02 11:51:42 +02:00
|
|
|
bank->mod_usage &= ~(1 << offset);
|
|
|
|
|
|
|
|
if (bank->regs->ctrl && !bank->mod_usage) {
|
|
|
|
void __iomem *reg = bank->base + bank->regs->ctrl;
|
|
|
|
u32 ctrl;
|
|
|
|
|
|
|
|
ctrl = __raw_readl(reg);
|
|
|
|
/* Module is disabled, clocks are gated */
|
|
|
|
ctrl |= GPIO_MOD_CTRL_BIT;
|
|
|
|
__raw_writel(ctrl, reg);
|
2011-11-15 08:22:38 +01:00
|
|
|
bank->context.ctrl = ctrl;
|
2009-11-22 19:11:25 +01:00
|
|
|
}
|
2011-05-02 11:51:42 +02:00
|
|
|
|
2008-12-11 02:35:27 +01:00
|
|
|
_reset_gpio(bank, bank->chip.base + offset);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2011-09-29 03:53:22 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* If this is the last gpio to be freed in the bank,
|
|
|
|
* disable the bank module.
|
|
|
|
*/
|
|
|
|
if (!bank->mod_usage)
|
|
|
|
pm_runtime_put(bank->dev);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to unmask the GPIO bank interrupt as soon as possible to
|
|
|
|
* avoid missing GPIO interrupts for other lines in the bank.
|
|
|
|
* Then we need to mask-read-clear-unmask the triggered GPIO lines
|
|
|
|
* in the bank to avoid missing nested interrupts for a GPIO line.
|
|
|
|
* If we wait to unmask individual GPIO lines in the bank after the
|
|
|
|
* line's interrupt handler has been run, we may miss some nested
|
|
|
|
* interrupts.
|
|
|
|
*/
|
2006-11-23 12:41:32 +01:00
|
|
|
static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2005-09-07 18:20:26 +02:00
|
|
|
void __iomem *isr_reg = NULL;
|
2005-07-10 20:58:15 +02:00
|
|
|
u32 isr;
|
2013-04-04 22:16:14 +02:00
|
|
|
unsigned int bit;
|
2005-07-10 20:58:15 +02:00
|
|
|
struct gpio_bank *bank;
|
2006-06-27 01:16:00 +02:00
|
|
|
int unmasked = 0;
|
2011-02-21 14:46:08 +01:00
|
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-02-21 14:46:08 +01:00
|
|
|
chained_irq_enter(chip, desc);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-03-24 13:25:22 +01:00
|
|
|
bank = irq_get_handler_data(irq);
|
2011-04-21 18:17:35 +02:00
|
|
|
isr_reg = bank->base + bank->regs->irqstatus;
|
2011-09-29 03:53:22 +02:00
|
|
|
pm_runtime_get_sync(bank->dev);
|
2010-12-08 01:25:40 +01:00
|
|
|
|
|
|
|
if (WARN_ON(!isr_reg))
|
|
|
|
goto exit;
|
|
|
|
|
2013-03-20 13:15:57 +01:00
|
|
|
while (1) {
|
2006-04-02 18:46:23 +02:00
|
|
|
u32 isr_saved, level_mask = 0;
|
2006-06-27 01:16:00 +02:00
|
|
|
u32 enabled;
|
2006-04-02 18:46:23 +02:00
|
|
|
|
2006-06-27 01:16:00 +02:00
|
|
|
enabled = _get_gpio_irqbank_mask(bank);
|
|
|
|
isr_saved = isr = __raw_readl(isr_reg) & enabled;
|
2006-04-02 18:46:23 +02:00
|
|
|
|
2011-08-30 11:35:44 +02:00
|
|
|
if (bank->level_mask)
|
2008-01-17 06:56:15 +01:00
|
|
|
level_mask = bank->level_mask & enabled;
|
2006-04-02 18:46:23 +02:00
|
|
|
|
|
|
|
/* clear edge sensitive interrupts before handler(s) are
|
|
|
|
called so that we don't miss any interrupt occurred while
|
|
|
|
executing them */
|
2011-04-21 18:53:06 +02:00
|
|
|
_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
|
2006-04-02 18:46:23 +02:00
|
|
|
_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
|
2011-04-21 18:53:06 +02:00
|
|
|
_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
|
2006-04-02 18:46:23 +02:00
|
|
|
|
|
|
|
/* if there is only edge sensitive GPIO pin interrupts
|
|
|
|
configured, we could unmask GPIO bank interrupt immediately */
|
2006-06-27 01:16:00 +02:00
|
|
|
if (!level_mask && !unmasked) {
|
|
|
|
unmasked = 1;
|
2011-02-21 14:46:08 +01:00
|
|
|
chained_irq_exit(chip, desc);
|
2006-06-27 01:16:00 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
|
|
|
|
if (!isr)
|
|
|
|
break;
|
|
|
|
|
2013-04-04 22:16:14 +02:00
|
|
|
while (isr) {
|
|
|
|
bit = __ffs(isr);
|
|
|
|
isr &= ~(1 << bit);
|
2012-02-23 21:50:10 +01:00
|
|
|
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
/*
|
|
|
|
* Some chips can't respond to both rising and falling
|
|
|
|
* at the same time. If this irq was requested with
|
|
|
|
* both flags, we need to flip the ICR data for the IRQ
|
|
|
|
* to respond to the IRQ for the opposite direction.
|
|
|
|
* This will be indicated in the bank toggle_mask.
|
|
|
|
*/
|
2013-04-04 22:16:14 +02:00
|
|
|
if (bank->toggle_mask & (1 << bit))
|
|
|
|
_toggle_gpio_edge_triggering(bank, bit);
|
omap: gpio: Simultaneously requested rising and falling edge
Some chips, namely any OMAP1 chips using METHOD_MPUIO,
OMAP15xx and OMAP7xx, cannot be setup to respond to on-chip GPIO
interrupts in both rising and falling edge directions -- they can
only respond to one direction or the other, depending on how the
ICR is configured.
Additionally, current code forces rising edge detection if both
flags are specified:
if (trigger & IRQ_TYPE_EDGE_RISING)
l |= 1 << gpio;
else if (trigger & IRQ_TYPE_EDGE_FALLING)
l &= ~(1 << gpio);
else
goto bad;
This change implements a toggle function that will modify the ICR
to flip the direction of interrupt for IRQs that are requested with
both rising and falling flags. The toggle function is not called
for chips and GPIOs it does not apply to through the use of a flip_mask
that's added on a per-bank basis. The mask is only set for those
GPIOs where a toggle is necessary. Edge detection starts out the
same as above with FALLING mode first.
The toggle happens on EACH interrupt; without it, we have the
following sequence of actions on GPIO transition:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt
0x1 1 -> 0 (falling) No interrupt
(set ICR to 0x0 manually)
0x0 0 -> 1 (rising) No interrupt
0x0 1 -> 0 (falling) Interrupt
That is, with the ICR set to 1 for a gpio, only rising edge interrupts
are caught, and with it set to 0, only falling edge interrupts are
caught. If we add in the toggle, we get this:
ICR GPIO Result
0x1 0 -> 1 (rising) Interrupt (ICR set to 0x0)
0x0 1 -> 0 (falling) Interrupt (ICR set to 0x1)
0x1 0 -> 1 ...
so, both rising and falling are caught, per the request for both
(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING).
Signed-off-by: Cory Maccarrone <darkstar6262@gmail.com>
Acked-by: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2010-01-08 19:29:04 +01:00
|
|
|
|
2013-04-04 22:16:14 +02:00
|
|
|
generic_handle_irq(irq_find_mapping(bank->domain, bit));
|
2005-09-07 18:20:26 +02:00
|
|
|
}
|
2005-11-10 15:26:50 +01:00
|
|
|
}
|
2006-06-27 01:16:00 +02:00
|
|
|
/* if bank has any level sensitive GPIO pin interrupt
|
|
|
|
configured, we must unmask the bank interrupt only after
|
|
|
|
handler(s) are executed in order to avoid spurious bank
|
|
|
|
interrupt */
|
2010-12-08 01:25:40 +01:00
|
|
|
exit:
|
2006-06-27 01:16:00 +02:00
|
|
|
if (!unmasked)
|
2011-02-21 14:46:08 +01:00
|
|
|
chained_irq_exit(chip, desc);
|
2011-09-29 03:53:22 +02:00
|
|
|
pm_runtime_put(bank->dev);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_irq_shutdown(struct irq_data *d)
|
2006-09-25 11:41:38 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2013-03-01 18:22:47 +01:00
|
|
|
unsigned int gpio = irq_to_gpio(bank, d->hwirq);
|
2011-06-06 22:38:18 +02:00
|
|
|
unsigned long flags;
|
2006-09-25 11:41:38 +02:00
|
|
|
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2006-09-25 11:41:38 +02:00
|
|
|
_reset_gpio(bank, gpio);
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-09-25 11:41:38 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_ack_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2013-03-01 18:22:47 +01:00
|
|
|
unsigned int gpio = irq_to_gpio(bank, d->hwirq);
|
2005-07-10 20:58:15 +02:00
|
|
|
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_mask_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2013-03-01 18:22:47 +01:00
|
|
|
unsigned int gpio = irq_to_gpio(bank, d->hwirq);
|
2011-06-06 22:38:18 +02:00
|
|
|
unsigned long flags;
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2010-11-29 11:17:17 +01:00
|
|
|
static void gpio_unmask_irq(struct irq_data *d)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-11-29 11:17:17 +01:00
|
|
|
struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
|
2013-03-01 18:22:47 +01:00
|
|
|
unsigned int gpio = irq_to_gpio(bank, d->hwirq);
|
2011-04-22 16:59:07 +02:00
|
|
|
unsigned int irq_mask = GPIO_BIT(bank, gpio);
|
2011-03-24 12:40:15 +01:00
|
|
|
u32 trigger = irqd_get_trigger_type(d);
|
2011-06-06 22:38:18 +02:00
|
|
|
unsigned long flags;
|
2009-06-05 00:57:10 +02:00
|
|
|
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2009-06-05 00:57:10 +02:00
|
|
|
if (trigger)
|
2011-04-22 16:59:07 +02:00
|
|
|
_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
|
2008-01-17 06:56:15 +01:00
|
|
|
|
|
|
|
/* For level-triggered GPIOs, the clearing must be done after
|
|
|
|
* the HW source is cleared, thus after the handler has run */
|
|
|
|
if (bank->level_mask & irq_mask) {
|
|
|
|
_set_gpio_irqenable(bank, gpio, 0);
|
|
|
|
_clear_gpio_irqstatus(bank, gpio);
|
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-01-17 06:56:14 +01:00
|
|
|
_set_gpio_irqenable(bank, gpio, 1);
|
2011-06-06 22:38:18 +02:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
static struct irq_chip gpio_irq_chip = {
|
|
|
|
.name = "GPIO",
|
2010-11-29 11:17:17 +01:00
|
|
|
.irq_shutdown = gpio_irq_shutdown,
|
|
|
|
.irq_ack = gpio_ack_irq,
|
|
|
|
.irq_mask = gpio_mask_irq,
|
|
|
|
.irq_unmask = gpio_unmask_irq,
|
|
|
|
.irq_set_type = gpio_irq_type,
|
|
|
|
.irq_set_wake = gpio_wake_enable,
|
2006-12-07 02:13:59 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
2009-07-08 13:22:04 +02:00
|
|
|
static int omap_mpuio_suspend_noirq(struct device *dev)
|
2006-12-07 02:14:11 +01:00
|
|
|
{
|
2009-07-08 13:22:04 +02:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2006-12-07 02:14:11 +01:00
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
2010-12-08 01:26:58 +01:00
|
|
|
void __iomem *mask_reg = bank->base +
|
|
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2006-12-07 02:14:11 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2012-04-27 16:13:33 +02:00
|
|
|
__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-07-08 13:22:04 +02:00
|
|
|
static int omap_mpuio_resume_noirq(struct device *dev)
|
2006-12-07 02:14:11 +01:00
|
|
|
{
|
2009-07-08 13:22:04 +02:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
2006-12-07 02:14:11 +01:00
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
2010-12-08 01:26:58 +01:00
|
|
|
void __iomem *mask_reg = bank->base +
|
|
|
|
OMAP_MPUIO_GPIO_MASKIT / bank->stride;
|
2008-03-03 13:33:30 +01:00
|
|
|
unsigned long flags;
|
2006-12-07 02:14:11 +01:00
|
|
|
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2012-04-27 16:13:34 +02:00
|
|
|
__raw_writel(bank->context.wake_en, mask_reg);
|
2008-03-03 13:33:30 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2006-12-07 02:14:11 +01:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-15 03:00:08 +01:00
|
|
|
static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
|
2009-07-08 13:22:04 +02:00
|
|
|
.suspend_noirq = omap_mpuio_suspend_noirq,
|
|
|
|
.resume_noirq = omap_mpuio_resume_noirq,
|
|
|
|
};
|
|
|
|
|
2011-04-22 22:02:46 +02:00
|
|
|
/* use platform_driver for this. */
|
2006-12-07 02:14:11 +01:00
|
|
|
static struct platform_driver omap_mpuio_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "mpuio",
|
2009-07-08 13:22:04 +02:00
|
|
|
.pm = &omap_mpuio_dev_pm_ops,
|
2006-12-07 02:14:11 +01:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct platform_device omap_mpuio_device = {
|
|
|
|
.name = "mpuio",
|
|
|
|
.id = -1,
|
|
|
|
.dev = {
|
|
|
|
.driver = &omap_mpuio_driver.driver,
|
|
|
|
}
|
|
|
|
/* could list the /proc/iomem resources */
|
|
|
|
};
|
|
|
|
|
2011-05-05 16:28:01 +02:00
|
|
|
static inline void mpuio_init(struct gpio_bank *bank)
|
2006-12-07 02:14:11 +01:00
|
|
|
{
|
2010-12-08 01:26:57 +01:00
|
|
|
platform_set_drvdata(&omap_mpuio_device, bank);
|
2007-04-02 21:46:47 +02:00
|
|
|
|
2006-12-07 02:14:11 +01:00
|
|
|
if (platform_driver_register(&omap_mpuio_driver) == 0)
|
|
|
|
(void) platform_device_register(&omap_mpuio_device);
|
|
|
|
}
|
|
|
|
|
2006-12-07 02:13:59 +01:00
|
|
|
/*---------------------------------------------------------------------*/
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
static int gpio_input(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
_set_gpio_direction(bank, offset, 1);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-05 15:53:24 +02:00
|
|
|
static int gpio_is_input(struct gpio_bank *bank, int mask)
|
|
|
|
{
|
2011-04-21 01:31:23 +02:00
|
|
|
void __iomem *reg = bank->base + bank->regs->direction;
|
2009-08-05 15:53:24 +02:00
|
|
|
|
|
|
|
return __raw_readl(reg) & mask;
|
|
|
|
}
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
static int gpio_get(struct gpio_chip *chip, unsigned offset)
|
|
|
|
{
|
2009-08-05 15:53:24 +02:00
|
|
|
struct gpio_bank *bank;
|
|
|
|
u32 mask;
|
|
|
|
|
2011-04-22 13:08:16 +02:00
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
gpio/omap: fix redundant decoding of gpio offset
In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.
Here is Russell's original comment:
Can someone explain to me this:
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
void __iomem *reg = bank->base + bank->regs->datain;
return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *reg = bank->base;
int gpio = chip->base + offset;
u32 mask = GPIO_BIT(bank, gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?
Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.
However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.
Surely this kind of behaviour is not intended?
Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-27 07:16:09 +01:00
|
|
|
mask = (1 << offset);
|
2009-08-05 15:53:24 +02:00
|
|
|
|
|
|
|
if (gpio_is_input(bank, mask))
|
gpio/omap: fix redundant decoding of gpio offset
In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.
Here is Russell's original comment:
Can someone explain to me this:
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
void __iomem *reg = bank->base + bank->regs->datain;
return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *reg = bank->base;
int gpio = chip->base + offset;
u32 mask = GPIO_BIT(bank, gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?
Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.
However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.
Surely this kind of behaviour is not intended?
Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-27 07:16:09 +01:00
|
|
|
return _get_gpio_datain(bank, offset);
|
2009-08-05 15:53:24 +02:00
|
|
|
else
|
gpio/omap: fix redundant decoding of gpio offset
In gpio_get(), _get_gpio_datain() and _get_gpio_dataout() get rid of
un-necessary operation to compute gpio mask. The gpio offset passed
to gpio_get() is sufficient to do that.
Here is Russell's original comment:
Can someone explain to me this:
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
{
void __iomem *reg = bank->base + bank->regs->datain;
return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0;
}
static int gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
void __iomem *reg = bank->base;
int gpio = chip->base + offset;
u32 mask = GPIO_BIT(bank, gpio);
if (gpio_is_input(bank, mask))
return _get_gpio_datain(bank, gpio);
else
return _get_gpio_dataout(bank, gpio);
}
Given that bank->width on OMAP is either 32 or 16, and GPIO numbers for
any GPIO chip are always aligned to 32 or 16, why does this code bother
adding the chips base gpio number and then modulo the width?
Surely this means if - for argument sake - you registered a GPIO chip
with 8 lines followed by one with 16 lines, GPIO0..7 would be chip 0
bit 0..7, GPIO8..15 would be chip 1 bit 8..15, GPIO16..23 would be
chip 1 bit 0..7.
However, if you registered a GPIO chip with 16 lines first, it would
mean GPIO0..15 would be chip 0 bit 0..15, and GPIO16..31 would be
chip 1 bit 0..15.
Surely this kind of behaviour is not intended?
Is there a reason why the bitmask can't just be (1 << offset) where
offset is passed into these functions as GPIO number - chip->base ?
Reported-by: Russell King - ARM Linux <linux@arm.linux.org.uk>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
2012-02-27 07:16:09 +01:00
|
|
|
return _get_gpio_dataout(bank, offset);
|
2008-03-03 21:43:23 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2011-04-21 01:31:23 +02:00
|
|
|
bank->set_dataout(bank, offset, value);
|
2008-03-03 21:43:23 +01:00
|
|
|
_set_gpio_direction(bank, offset, 0);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-05-26 23:42:23 +02:00
|
|
|
static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
|
|
|
|
unsigned debounce)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
2010-12-08 01:26:57 +01:00
|
|
|
|
2010-05-26 23:42:23 +02:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
|
|
|
_set_gpio_debounce(bank, offset, debounce);
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-03-03 21:43:23 +01:00
|
|
|
static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
bank = container_of(chip, struct gpio_bank, chip);
|
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2011-04-21 01:31:23 +02:00
|
|
|
bank->set_dataout(bank, offset, value);
|
2008-03-03 21:43:23 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*---------------------------------------------------------------------*/
|
|
|
|
|
2010-12-08 01:26:56 +01:00
|
|
|
static void __init omap_gpio_show_rev(struct gpio_bank *bank)
|
2009-10-20 00:25:20 +02:00
|
|
|
{
|
2011-04-22 23:37:16 +02:00
|
|
|
static bool called;
|
2009-10-20 00:25:20 +02:00
|
|
|
u32 rev;
|
|
|
|
|
2011-04-22 23:37:16 +02:00
|
|
|
if (called || bank->regs->revision == USHRT_MAX)
|
2009-10-20 00:25:20 +02:00
|
|
|
return;
|
|
|
|
|
2011-04-22 23:37:16 +02:00
|
|
|
rev = __raw_readw(bank->base + bank->regs->revision);
|
|
|
|
pr_info("OMAP GPIO hardware version %d.%d\n",
|
2009-10-20 00:25:20 +02:00
|
|
|
(rev >> 4) & 0x0f, rev & 0x0f);
|
2011-04-22 23:37:16 +02:00
|
|
|
|
|
|
|
called = true;
|
2009-10-20 00:25:20 +02:00
|
|
|
}
|
|
|
|
|
2008-02-26 20:10:50 +01:00
|
|
|
/* This lock class tells lockdep that GPIO irqs are in a different
|
|
|
|
* category than their parents, so it won't report false recursion.
|
|
|
|
*/
|
|
|
|
static struct lock_class_key gpio_lock_class;
|
|
|
|
|
2011-05-05 16:28:01 +02:00
|
|
|
static void omap_gpio_mod_init(struct gpio_bank *bank)
|
2010-12-08 01:26:55 +01:00
|
|
|
{
|
2011-09-13 11:42:05 +02:00
|
|
|
void __iomem *base = bank->base;
|
|
|
|
u32 l = 0xffffffff;
|
2010-12-08 01:26:55 +01:00
|
|
|
|
2011-09-13 11:42:05 +02:00
|
|
|
if (bank->width == 16)
|
|
|
|
l = 0xffff;
|
|
|
|
|
2011-08-30 20:32:21 +02:00
|
|
|
if (bank->is_mpuio) {
|
2011-09-13 11:42:05 +02:00
|
|
|
__raw_writel(l, bank->base + bank->regs->irqenable);
|
|
|
|
return;
|
2010-12-08 01:26:55 +01:00
|
|
|
}
|
2011-09-13 11:42:05 +02:00
|
|
|
|
|
|
|
_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
|
2012-04-30 09:20:12 +02:00
|
|
|
_gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
|
2011-09-13 11:42:05 +02:00
|
|
|
if (bank->regs->debounce_en)
|
2012-04-30 09:20:12 +02:00
|
|
|
__raw_writel(0, base + bank->regs->debounce_en);
|
2011-09-13 11:42:05 +02:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
/* Save OE default value (0xffffffff) in the context */
|
|
|
|
bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
|
2011-09-13 11:42:05 +02:00
|
|
|
/* Initialize interface clk ungated, module enabled */
|
|
|
|
if (bank->regs->ctrl)
|
2012-04-30 09:20:12 +02:00
|
|
|
__raw_writel(0, base + bank->regs->ctrl);
|
2012-07-11 11:13:14 +02:00
|
|
|
|
|
|
|
bank->dbck = clk_get(bank->dev, "dbclk");
|
|
|
|
if (IS_ERR(bank->dbck))
|
|
|
|
dev_err(bank->dev, "Could not get gpio dbck\n");
|
2010-12-08 01:26:55 +01:00
|
|
|
}
|
|
|
|
|
2012-11-19 19:22:34 +01:00
|
|
|
static void
|
2011-04-21 22:23:34 +02:00
|
|
|
omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
|
|
|
|
unsigned int num)
|
|
|
|
{
|
|
|
|
struct irq_chip_generic *gc;
|
|
|
|
struct irq_chip_type *ct;
|
|
|
|
|
|
|
|
gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
|
|
|
|
handle_simple_irq);
|
2011-07-18 16:43:14 +02:00
|
|
|
if (!gc) {
|
|
|
|
dev_err(bank->dev, "Memory alloc failed for gc\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-04-21 22:23:34 +02:00
|
|
|
ct = gc->chip_types;
|
|
|
|
|
|
|
|
/* NOTE: No ack required, reading IRQ status clears it. */
|
|
|
|
ct->chip.irq_mask = irq_gc_mask_set_bit;
|
|
|
|
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
|
|
|
|
ct->chip.irq_set_type = gpio_irq_type;
|
2011-09-13 11:11:44 +02:00
|
|
|
|
|
|
|
if (bank->regs->wkup_en)
|
2013-08-13 09:16:56 +02:00
|
|
|
ct->chip.irq_set_wake = gpio_wake_enable;
|
2011-04-21 22:23:34 +02:00
|
|
|
|
|
|
|
ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
|
|
|
|
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
|
|
|
|
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
|
|
|
}
|
|
|
|
|
2012-11-19 19:22:34 +01:00
|
|
|
static void omap_gpio_chip_init(struct gpio_bank *bank)
|
2010-12-08 01:26:55 +01:00
|
|
|
{
|
2010-12-08 01:26:57 +01:00
|
|
|
int j;
|
2010-12-08 01:26:55 +01:00
|
|
|
static int gpio;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* REVISIT eventually switch from OMAP-specific gpio structs
|
|
|
|
* over to the generic ones
|
|
|
|
*/
|
|
|
|
bank->chip.request = omap_gpio_request;
|
|
|
|
bank->chip.free = omap_gpio_free;
|
|
|
|
bank->chip.direction_input = gpio_input;
|
|
|
|
bank->chip.get = gpio_get;
|
|
|
|
bank->chip.direction_output = gpio_output;
|
|
|
|
bank->chip.set_debounce = gpio_debounce;
|
|
|
|
bank->chip.set = gpio_set;
|
2013-03-01 18:22:47 +01:00
|
|
|
bank->chip.to_irq = omap_gpio_to_irq;
|
2011-08-30 20:32:21 +02:00
|
|
|
if (bank->is_mpuio) {
|
2010-12-08 01:26:55 +01:00
|
|
|
bank->chip.label = "mpuio";
|
2011-09-13 11:11:44 +02:00
|
|
|
if (bank->regs->wkup_en)
|
|
|
|
bank->chip.dev = &omap_mpuio_device.dev;
|
2010-12-08 01:26:55 +01:00
|
|
|
bank->chip.base = OMAP_MPUIO(0);
|
|
|
|
} else {
|
|
|
|
bank->chip.label = "gpio";
|
|
|
|
bank->chip.base = gpio;
|
2011-04-21 18:23:00 +02:00
|
|
|
gpio += bank->width;
|
2010-12-08 01:26:55 +01:00
|
|
|
}
|
2011-04-21 18:23:00 +02:00
|
|
|
bank->chip.ngpio = bank->width;
|
2010-12-08 01:26:55 +01:00
|
|
|
|
|
|
|
gpiochip_add(&bank->chip);
|
|
|
|
|
2013-03-01 18:22:47 +01:00
|
|
|
for (j = 0; j < bank->width; j++) {
|
|
|
|
int irq = irq_create_mapping(bank->domain, j);
|
|
|
|
irq_set_lockdep_class(irq, &gpio_lock_class);
|
|
|
|
irq_set_chip_data(irq, bank);
|
2011-08-30 20:32:21 +02:00
|
|
|
if (bank->is_mpuio) {
|
2013-03-01 18:22:47 +01:00
|
|
|
omap_mpuio_alloc_gc(bank, irq, bank->width);
|
2011-04-21 22:23:34 +02:00
|
|
|
} else {
|
2013-03-01 18:22:47 +01:00
|
|
|
irq_set_chip_and_handler(irq, &gpio_irq_chip,
|
|
|
|
handle_simple_irq);
|
|
|
|
set_irq_flags(irq, IRQF_VALID);
|
2011-04-21 22:23:34 +02:00
|
|
|
}
|
2010-12-08 01:26:55 +01:00
|
|
|
}
|
2011-03-24 13:25:22 +01:00
|
|
|
irq_set_chained_handler(bank->irq, gpio_irq_handler);
|
|
|
|
irq_set_handler_data(bank->irq, bank);
|
2010-12-08 01:26:55 +01:00
|
|
|
}
|
|
|
|
|
2011-08-16 11:53:02 +02:00
|
|
|
static const struct of_device_id omap_gpio_match[];
|
|
|
|
|
2012-11-19 19:22:34 +01:00
|
|
|
static int omap_gpio_probe(struct platform_device *pdev)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2012-02-01 15:58:56 +01:00
|
|
|
struct device *dev = &pdev->dev;
|
2011-08-16 11:53:02 +02:00
|
|
|
struct device_node *node = dev->of_node;
|
|
|
|
const struct of_device_id *match;
|
2012-05-21 21:57:39 +02:00
|
|
|
const struct omap_gpio_platform_data *pdata;
|
2010-12-08 01:26:57 +01:00
|
|
|
struct resource *res;
|
2005-07-10 20:58:15 +02:00
|
|
|
struct gpio_bank *bank;
|
2013-06-24 17:13:23 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
int irq_base;
|
|
|
|
#endif
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2011-08-16 11:53:02 +02:00
|
|
|
match = of_match_device(of_match_ptr(omap_gpio_match), dev);
|
|
|
|
|
2013-07-30 10:08:05 +02:00
|
|
|
pdata = match ? match->data : dev_get_platdata(dev);
|
2011-08-16 11:53:02 +02:00
|
|
|
if (!pdata)
|
2012-02-01 16:01:39 +01:00
|
|
|
return -EINVAL;
|
2007-11-30 01:15:11 +01:00
|
|
|
|
2012-10-05 11:37:38 +02:00
|
|
|
bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
|
2011-05-05 16:28:01 +02:00
|
|
|
if (!bank) {
|
2012-02-01 15:58:56 +01:00
|
|
|
dev_err(dev, "Memory alloc failed\n");
|
2012-02-01 16:01:39 +01:00
|
|
|
return -ENOMEM;
|
2011-05-05 16:28:01 +02:00
|
|
|
}
|
2005-09-07 18:20:26 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
|
|
|
if (unlikely(!res)) {
|
2012-02-01 15:58:56 +01:00
|
|
|
dev_err(dev, "Invalid IRQ resource\n");
|
2012-02-01 16:01:39 +01:00
|
|
|
return -ENODEV;
|
2009-05-28 23:16:04 +02:00
|
|
|
}
|
2005-07-10 20:58:15 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
bank->irq = res->start;
|
2012-02-01 15:58:56 +01:00
|
|
|
bank->dev = dev;
|
2010-12-08 01:26:57 +01:00
|
|
|
bank->dbck_flag = pdata->dbck_flag;
|
2010-12-08 01:26:58 +01:00
|
|
|
bank->stride = pdata->bank_stride;
|
2011-04-21 18:23:00 +02:00
|
|
|
bank->width = pdata->bank_width;
|
2011-08-30 20:32:21 +02:00
|
|
|
bank->is_mpuio = pdata->is_mpuio;
|
2011-05-05 13:34:12 +02:00
|
|
|
bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
|
2011-04-21 01:31:23 +02:00
|
|
|
bank->regs = pdata->regs;
|
2011-08-16 11:53:02 +02:00
|
|
|
#ifdef CONFIG_OF_GPIO
|
|
|
|
bank->chip.of_node = of_node_get(node);
|
|
|
|
#endif
|
2013-04-04 22:16:15 +02:00
|
|
|
if (node) {
|
|
|
|
if (!of_property_read_bool(node, "ti,gpio-always-on"))
|
|
|
|
bank->loses_context = true;
|
|
|
|
} else {
|
|
|
|
bank->loses_context = pdata->loses_context;
|
2013-04-15 20:06:54 +02:00
|
|
|
|
|
|
|
if (bank->loses_context)
|
|
|
|
bank->get_context_loss_count =
|
|
|
|
pdata->get_context_loss_count;
|
2011-08-16 11:53:02 +02:00
|
|
|
}
|
|
|
|
|
2013-06-24 17:13:23 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP1
|
|
|
|
/*
|
|
|
|
* REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
|
|
|
|
* irq_alloc_descs() and irq_domain_add_legacy() and just use a
|
|
|
|
* linear IRQ domain mapping for all OMAP platforms.
|
|
|
|
*/
|
|
|
|
irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
|
|
|
|
if (irq_base < 0) {
|
|
|
|
dev_err(dev, "Couldn't allocate IRQ numbers\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
2011-08-16 11:53:02 +02:00
|
|
|
|
2013-06-24 17:13:23 +02:00
|
|
|
bank->domain = irq_domain_add_legacy(node, bank->width, irq_base,
|
|
|
|
0, &irq_domain_simple_ops, NULL);
|
|
|
|
#else
|
2013-03-01 18:22:47 +01:00
|
|
|
bank->domain = irq_domain_add_linear(node, bank->width,
|
|
|
|
&irq_domain_simple_ops, NULL);
|
2013-06-24 17:13:23 +02:00
|
|
|
#endif
|
|
|
|
if (!bank->domain) {
|
|
|
|
dev_err(dev, "Couldn't register an IRQ domain\n");
|
2011-08-16 11:53:02 +02:00
|
|
|
return -ENODEV;
|
2013-06-24 17:13:23 +02:00
|
|
|
}
|
2011-04-21 01:31:23 +02:00
|
|
|
|
|
|
|
if (bank->regs->set_dataout && bank->regs->clr_dataout)
|
|
|
|
bank->set_dataout = _set_gpio_dataout_reg;
|
|
|
|
else
|
|
|
|
bank->set_dataout = _set_gpio_dataout_mask;
|
2009-10-20 00:25:20 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
spin_lock_init(&bank->lock);
|
2009-10-20 00:25:20 +02:00
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
/* Static mapping, never released */
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (unlikely(!res)) {
|
2012-02-01 15:58:56 +01:00
|
|
|
dev_err(dev, "Invalid mem resource\n");
|
2013-04-04 22:16:12 +02:00
|
|
|
irq_domain_remove(bank->domain);
|
2012-02-01 16:01:39 +01:00
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!devm_request_mem_region(dev, res->start, resource_size(res),
|
|
|
|
pdev->name)) {
|
|
|
|
dev_err(dev, "Region already claimed\n");
|
2013-04-04 22:16:12 +02:00
|
|
|
irq_domain_remove(bank->domain);
|
2012-02-01 16:01:39 +01:00
|
|
|
return -EBUSY;
|
2010-12-08 01:26:57 +01:00
|
|
|
}
|
2008-12-11 02:35:24 +01:00
|
|
|
|
2012-02-01 16:01:39 +01:00
|
|
|
bank->base = devm_ioremap(dev, res->start, resource_size(res));
|
2010-12-08 01:26:57 +01:00
|
|
|
if (!bank->base) {
|
2012-02-01 15:58:56 +01:00
|
|
|
dev_err(dev, "Could not ioremap\n");
|
2013-04-04 22:16:12 +02:00
|
|
|
irq_domain_remove(bank->domain);
|
2012-02-01 16:01:39 +01:00
|
|
|
return -ENOMEM;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2011-11-23 21:18:52 +01:00
|
|
|
platform_set_drvdata(pdev, bank);
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
pm_runtime_enable(bank->dev);
|
2011-09-29 03:53:22 +02:00
|
|
|
pm_runtime_irq_safe(bank->dev);
|
2010-12-08 01:26:57 +01:00
|
|
|
pm_runtime_get_sync(bank->dev);
|
|
|
|
|
2011-08-30 20:32:21 +02:00
|
|
|
if (bank->is_mpuio)
|
2011-09-13 11:42:05 +02:00
|
|
|
mpuio_init(bank);
|
|
|
|
|
2011-05-05 16:28:01 +02:00
|
|
|
omap_gpio_mod_init(bank);
|
2010-12-08 01:26:57 +01:00
|
|
|
omap_gpio_chip_init(bank);
|
2010-12-08 01:26:56 +01:00
|
|
|
omap_gpio_show_rev(bank);
|
2009-10-20 00:25:20 +02:00
|
|
|
|
2011-09-29 03:53:22 +02:00
|
|
|
pm_runtime_put(bank->dev);
|
|
|
|
|
2011-05-05 16:28:01 +02:00
|
|
|
list_add_tail(&bank->node, &omap_gpio_list);
|
2010-12-08 01:26:57 +01:00
|
|
|
|
2013-04-04 22:16:12 +02:00
|
|
|
return 0;
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
|
|
|
|
2011-09-29 03:53:22 +02:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
#if defined(CONFIG_PM_RUNTIME)
|
2011-09-29 01:17:25 +02:00
|
|
|
static void omap_gpio_restore_context(struct gpio_bank *bank);
|
2006-12-07 02:13:52 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
static int omap_gpio_runtime_suspend(struct device *dev)
|
2006-12-07 02:13:52 +01:00
|
|
|
{
|
2011-11-23 22:14:29 +01:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
|
u32 l1 = 0, l2 = 0;
|
|
|
|
unsigned long flags;
|
2012-03-06 00:10:04 +01:00
|
|
|
u32 wake_low, wake_hi;
|
2009-01-27 20:15:34 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2012-03-06 00:10:04 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Only edges can generate a wakeup event to the PRCM.
|
|
|
|
*
|
|
|
|
* Therefore, ensure any wake-up capable GPIOs have
|
|
|
|
* edge-detection enabled before going idle to ensure a wakeup
|
|
|
|
* to the PRCM is generated on a GPIO transition. (c.f. 34xx
|
|
|
|
* NDA TRM 25.5.3.1)
|
|
|
|
*
|
|
|
|
* The normal values will be restored upon ->runtime_resume()
|
|
|
|
* by writing back the values saved in bank->context.
|
|
|
|
*/
|
|
|
|
wake_low = bank->context.leveldetect0 & bank->context.wake_en;
|
|
|
|
if (wake_low)
|
|
|
|
__raw_writel(wake_low | bank->context.fallingdetect,
|
|
|
|
bank->base + bank->regs->fallingdetect);
|
|
|
|
wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
|
|
|
|
if (wake_hi)
|
|
|
|
__raw_writel(wake_hi | bank->context.risingdetect,
|
|
|
|
bank->base + bank->regs->risingdetect);
|
|
|
|
|
2012-05-18 01:42:16 +02:00
|
|
|
if (!bank->enabled_non_wakeup_gpios)
|
|
|
|
goto update_gpio_context_count;
|
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
if (bank->power_mode != OFF_MODE) {
|
|
|
|
bank->power_mode = 0;
|
2011-11-15 08:22:38 +01:00
|
|
|
goto update_gpio_context_count;
|
2011-11-23 22:14:29 +01:00
|
|
|
}
|
|
|
|
/*
|
|
|
|
* If going to OFF, remove triggering for all
|
|
|
|
* non-wakeup GPIOs. Otherwise spurious IRQs will be
|
|
|
|
* generated. See OMAP2420 Errata item 1.101.
|
|
|
|
*/
|
|
|
|
bank->saved_datain = __raw_readl(bank->base +
|
|
|
|
bank->regs->datain);
|
2012-04-27 16:13:32 +02:00
|
|
|
l1 = bank->context.fallingdetect;
|
|
|
|
l2 = bank->context.risingdetect;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
l1 &= ~bank->enabled_non_wakeup_gpios;
|
|
|
|
l2 &= ~bank->enabled_non_wakeup_gpios;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
__raw_writel(l1, bank->base + bank->regs->fallingdetect);
|
|
|
|
__raw_writel(l2, bank->base + bank->regs->risingdetect);
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
bank->workaround_enabled = true;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2011-11-15 08:22:38 +01:00
|
|
|
update_gpio_context_count:
|
2011-11-23 22:14:29 +01:00
|
|
|
if (bank->get_context_loss_count)
|
|
|
|
bank->context_loss_count =
|
2011-09-29 01:17:25 +02:00
|
|
|
bank->get_context_loss_count(bank->dev);
|
|
|
|
|
2011-11-23 22:33:28 +01:00
|
|
|
_gpio_dbck_disable(bank);
|
2011-11-23 22:14:29 +01:00
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
2011-09-29 03:53:22 +02:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
return 0;
|
2006-12-07 02:13:52 +01:00
|
|
|
}
|
|
|
|
|
2013-04-15 20:06:54 +02:00
|
|
|
static void omap_gpio_init_context(struct gpio_bank *p);
|
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
static int omap_gpio_runtime_resume(struct device *dev)
|
2006-12-07 02:13:52 +01:00
|
|
|
{
|
2011-11-23 22:14:29 +01:00
|
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
|
|
struct gpio_bank *bank = platform_get_drvdata(pdev);
|
|
|
|
u32 l = 0, gen, gen0, gen1;
|
|
|
|
unsigned long flags;
|
2013-04-04 22:16:15 +02:00
|
|
|
int c;
|
2009-01-27 20:15:34 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
spin_lock_irqsave(&bank->lock, flags);
|
2013-04-15 20:06:54 +02:00
|
|
|
|
|
|
|
/*
|
|
|
|
* On the first resume during the probe, the context has not
|
|
|
|
* been initialised and so initialise it now. Also initialise
|
|
|
|
* the context loss count.
|
|
|
|
*/
|
|
|
|
if (bank->loses_context && !bank->context_valid) {
|
|
|
|
omap_gpio_init_context(bank);
|
|
|
|
|
|
|
|
if (bank->get_context_loss_count)
|
|
|
|
bank->context_loss_count =
|
|
|
|
bank->get_context_loss_count(bank->dev);
|
|
|
|
}
|
|
|
|
|
2011-11-23 22:33:28 +01:00
|
|
|
_gpio_dbck_enable(bank);
|
2012-03-06 00:10:04 +01:00
|
|
|
|
|
|
|
/*
|
|
|
|
* In ->runtime_suspend(), level-triggered, wakeup-enabled
|
|
|
|
* GPIOs were set to edge trigger also in order to be able to
|
|
|
|
* generate a PRCM wakeup. Here we restore the
|
|
|
|
* pre-runtime_suspend() values for edge triggering.
|
|
|
|
*/
|
|
|
|
__raw_writel(bank->context.fallingdetect,
|
|
|
|
bank->base + bank->regs->fallingdetect);
|
|
|
|
__raw_writel(bank->context.risingdetect,
|
|
|
|
bank->base + bank->regs->risingdetect);
|
|
|
|
|
2013-04-04 22:16:15 +02:00
|
|
|
if (bank->loses_context) {
|
|
|
|
if (!bank->get_context_loss_count) {
|
2011-11-23 22:14:29 +01:00
|
|
|
omap_gpio_restore_context(bank);
|
|
|
|
} else {
|
2013-04-04 22:16:15 +02:00
|
|
|
c = bank->get_context_loss_count(bank->dev);
|
|
|
|
if (c != bank->context_loss_count) {
|
|
|
|
omap_gpio_restore_context(bank);
|
|
|
|
} else {
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
2011-09-29 01:17:25 +02:00
|
|
|
}
|
2011-11-23 22:14:29 +01:00
|
|
|
}
|
2009-01-27 20:09:24 +01:00
|
|
|
|
2012-04-27 16:13:38 +02:00
|
|
|
if (!bank->workaround_enabled) {
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
l = __raw_readl(bank->base + bank->regs->datain);
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
/*
|
|
|
|
* Check if any of the non-wakeup interrupt GPIOs have changed
|
|
|
|
* state. If so, generate an IRQ by software. This is
|
|
|
|
* horribly racy, but it's the best we can do to work around
|
|
|
|
* this silicon bug.
|
|
|
|
*/
|
|
|
|
l ^= bank->saved_datain;
|
|
|
|
l &= bank->enabled_non_wakeup_gpios;
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
/*
|
|
|
|
* No need to generate IRQs for the rising edge for gpio IRQs
|
|
|
|
* configured with falling edge only; and vice versa.
|
|
|
|
*/
|
2012-04-27 16:13:32 +02:00
|
|
|
gen0 = l & bank->context.fallingdetect;
|
2011-11-23 22:14:29 +01:00
|
|
|
gen0 &= bank->saved_datain;
|
2009-08-28 19:51:36 +02:00
|
|
|
|
2012-04-27 16:13:32 +02:00
|
|
|
gen1 = l & bank->context.risingdetect;
|
2011-11-23 22:14:29 +01:00
|
|
|
gen1 &= ~(bank->saved_datain);
|
2009-08-28 19:51:36 +02:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
/* FIXME: Consider GPIO IRQs with level detections properly! */
|
2012-04-27 16:13:32 +02:00
|
|
|
gen = l & (~(bank->context.fallingdetect) &
|
|
|
|
~(bank->context.risingdetect));
|
2011-11-23 22:14:29 +01:00
|
|
|
/* Consider all GPIO IRQs needed to be updated */
|
|
|
|
gen |= gen0 | gen1;
|
2009-08-28 19:51:36 +02:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
if (gen) {
|
|
|
|
u32 old0, old1;
|
2009-08-28 19:51:36 +02:00
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
|
|
|
|
old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
|
2010-02-15 18:27:25 +01:00
|
|
|
|
2012-04-27 16:13:37 +02:00
|
|
|
if (!bank->regs->irqstatus_raw0) {
|
2011-11-23 22:14:29 +01:00
|
|
|
__raw_writel(old0 | gen, bank->base +
|
2011-08-30 11:35:44 +02:00
|
|
|
bank->regs->leveldetect0);
|
2011-11-23 22:14:29 +01:00
|
|
|
__raw_writel(old1 | gen, bank->base +
|
2011-08-30 11:35:44 +02:00
|
|
|
bank->regs->leveldetect1);
|
2011-11-23 22:14:29 +01:00
|
|
|
}
|
2011-08-30 11:35:44 +02:00
|
|
|
|
2012-04-27 16:13:37 +02:00
|
|
|
if (bank->regs->irqstatus_raw0) {
|
2011-11-23 22:14:29 +01:00
|
|
|
__raw_writel(old0 | l, bank->base +
|
2011-08-30 11:35:44 +02:00
|
|
|
bank->regs->leveldetect0);
|
2011-11-23 22:14:29 +01:00
|
|
|
__raw_writel(old1 | l, bank->base +
|
2011-08-30 11:35:44 +02:00
|
|
|
bank->regs->leveldetect1);
|
2006-12-07 02:13:52 +01:00
|
|
|
}
|
2011-11-23 22:14:29 +01:00
|
|
|
__raw_writel(old0, bank->base + bank->regs->leveldetect0);
|
|
|
|
__raw_writel(old1, bank->base + bank->regs->leveldetect1);
|
|
|
|
}
|
|
|
|
|
|
|
|
bank->workaround_enabled = false;
|
|
|
|
spin_unlock_irqrestore(&bank->lock, flags);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif /* CONFIG_PM_RUNTIME */
|
|
|
|
|
|
|
|
void omap2_gpio_prepare_for_idle(int pwr_mode)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
|
|
|
|
list_for_each_entry(bank, &omap_gpio_list, node) {
|
|
|
|
if (!bank->mod_usage || !bank->loses_context)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
bank->power_mode = pwr_mode;
|
|
|
|
|
|
|
|
pm_runtime_put_sync_suspend(bank->dev);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void omap2_gpio_resume_after_idle(void)
|
|
|
|
{
|
|
|
|
struct gpio_bank *bank;
|
|
|
|
|
|
|
|
list_for_each_entry(bank, &omap_gpio_list, node) {
|
|
|
|
if (!bank->mod_usage || !bank->loses_context)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
pm_runtime_get_sync(bank->dev);
|
2006-12-07 02:13:52 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-23 22:14:29 +01:00
|
|
|
#if defined(CONFIG_PM_RUNTIME)
|
2013-04-15 20:06:54 +02:00
|
|
|
static void omap_gpio_init_context(struct gpio_bank *p)
|
|
|
|
{
|
|
|
|
struct omap_gpio_reg_offs *regs = p->regs;
|
|
|
|
void __iomem *base = p->base;
|
|
|
|
|
|
|
|
p->context.ctrl = __raw_readl(base + regs->ctrl);
|
|
|
|
p->context.oe = __raw_readl(base + regs->direction);
|
|
|
|
p->context.wake_en = __raw_readl(base + regs->wkup_en);
|
|
|
|
p->context.leveldetect0 = __raw_readl(base + regs->leveldetect0);
|
|
|
|
p->context.leveldetect1 = __raw_readl(base + regs->leveldetect1);
|
|
|
|
p->context.risingdetect = __raw_readl(base + regs->risingdetect);
|
|
|
|
p->context.fallingdetect = __raw_readl(base + regs->fallingdetect);
|
|
|
|
p->context.irqenable1 = __raw_readl(base + regs->irqenable);
|
|
|
|
p->context.irqenable2 = __raw_readl(base + regs->irqenable2);
|
|
|
|
|
|
|
|
if (regs->set_dataout && p->regs->clr_dataout)
|
|
|
|
p->context.dataout = __raw_readl(base + regs->set_dataout);
|
|
|
|
else
|
|
|
|
p->context.dataout = __raw_readl(base + regs->dataout);
|
|
|
|
|
|
|
|
p->context_valid = true;
|
|
|
|
}
|
|
|
|
|
2011-09-29 01:17:25 +02:00
|
|
|
static void omap_gpio_restore_context(struct gpio_bank *bank)
|
2008-09-26 14:17:48 +02:00
|
|
|
{
|
2011-09-29 01:17:25 +02:00
|
|
|
__raw_writel(bank->context.wake_en,
|
2011-08-30 11:54:27 +02:00
|
|
|
bank->base + bank->regs->wkup_en);
|
|
|
|
__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
|
2011-09-29 01:17:25 +02:00
|
|
|
__raw_writel(bank->context.leveldetect0,
|
2011-08-30 11:54:27 +02:00
|
|
|
bank->base + bank->regs->leveldetect0);
|
2011-09-29 01:17:25 +02:00
|
|
|
__raw_writel(bank->context.leveldetect1,
|
2011-08-30 11:54:27 +02:00
|
|
|
bank->base + bank->regs->leveldetect1);
|
2011-09-29 01:17:25 +02:00
|
|
|
__raw_writel(bank->context.risingdetect,
|
2011-08-30 11:54:27 +02:00
|
|
|
bank->base + bank->regs->risingdetect);
|
2011-09-29 01:17:25 +02:00
|
|
|
__raw_writel(bank->context.fallingdetect,
|
2011-08-30 11:54:27 +02:00
|
|
|
bank->base + bank->regs->fallingdetect);
|
2011-09-09 15:44:08 +02:00
|
|
|
if (bank->regs->set_dataout && bank->regs->clr_dataout)
|
|
|
|
__raw_writel(bank->context.dataout,
|
|
|
|
bank->base + bank->regs->set_dataout);
|
|
|
|
else
|
|
|
|
__raw_writel(bank->context.dataout,
|
|
|
|
bank->base + bank->regs->dataout);
|
2011-08-29 15:24:50 +02:00
|
|
|
__raw_writel(bank->context.oe, bank->base + bank->regs->direction);
|
|
|
|
|
2011-09-09 15:38:58 +02:00
|
|
|
if (bank->dbck_enable_mask) {
|
|
|
|
__raw_writel(bank->context.debounce, bank->base +
|
|
|
|
bank->regs->debounce);
|
|
|
|
__raw_writel(bank->context.debounce_en,
|
|
|
|
bank->base + bank->regs->debounce_en);
|
|
|
|
}
|
2011-08-29 15:11:08 +02:00
|
|
|
|
|
|
|
__raw_writel(bank->context.irqenable1,
|
|
|
|
bank->base + bank->regs->irqenable);
|
|
|
|
__raw_writel(bank->context.irqenable2,
|
|
|
|
bank->base + bank->regs->irqenable2);
|
2008-09-26 14:17:48 +02:00
|
|
|
}
|
2011-11-23 22:14:29 +01:00
|
|
|
#endif /* CONFIG_PM_RUNTIME */
|
2011-09-29 03:53:22 +02:00
|
|
|
#else
|
2011-11-23 22:14:29 +01:00
|
|
|
#define omap_gpio_runtime_suspend NULL
|
|
|
|
#define omap_gpio_runtime_resume NULL
|
2013-05-31 17:59:46 +02:00
|
|
|
static inline void omap_gpio_init_context(struct gpio_bank *p) {}
|
2008-09-26 14:17:48 +02:00
|
|
|
#endif
|
|
|
|
|
2011-09-29 03:53:22 +02:00
|
|
|
static const struct dev_pm_ops gpio_pm_ops = {
|
2011-11-23 22:14:29 +01:00
|
|
|
SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
|
|
|
|
NULL)
|
2011-09-29 03:53:22 +02:00
|
|
|
};
|
|
|
|
|
2011-08-16 11:53:02 +02:00
|
|
|
#if defined(CONFIG_OF)
|
|
|
|
static struct omap_gpio_reg_offs omap2_gpio_regs = {
|
|
|
|
.revision = OMAP24XX_GPIO_REVISION,
|
|
|
|
.direction = OMAP24XX_GPIO_OE,
|
|
|
|
.datain = OMAP24XX_GPIO_DATAIN,
|
|
|
|
.dataout = OMAP24XX_GPIO_DATAOUT,
|
|
|
|
.set_dataout = OMAP24XX_GPIO_SETDATAOUT,
|
|
|
|
.clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
|
|
|
|
.irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
|
|
|
|
.irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
|
|
|
|
.irqenable = OMAP24XX_GPIO_IRQENABLE1,
|
|
|
|
.irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
|
|
|
|
.set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
|
|
|
|
.clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
|
|
|
|
.debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
|
|
|
|
.debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
|
|
|
|
.ctrl = OMAP24XX_GPIO_CTRL,
|
|
|
|
.wkup_en = OMAP24XX_GPIO_WAKE_EN,
|
|
|
|
.leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
|
|
|
|
.leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
|
|
|
|
.risingdetect = OMAP24XX_GPIO_RISINGDETECT,
|
|
|
|
.fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct omap_gpio_reg_offs omap4_gpio_regs = {
|
|
|
|
.revision = OMAP4_GPIO_REVISION,
|
|
|
|
.direction = OMAP4_GPIO_OE,
|
|
|
|
.datain = OMAP4_GPIO_DATAIN,
|
|
|
|
.dataout = OMAP4_GPIO_DATAOUT,
|
|
|
|
.set_dataout = OMAP4_GPIO_SETDATAOUT,
|
|
|
|
.clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
|
|
|
|
.irqstatus = OMAP4_GPIO_IRQSTATUS0,
|
|
|
|
.irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
|
|
|
|
.irqenable = OMAP4_GPIO_IRQSTATUSSET0,
|
|
|
|
.irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
|
|
|
|
.set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
|
|
|
|
.clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
|
|
|
|
.debounce = OMAP4_GPIO_DEBOUNCINGTIME,
|
|
|
|
.debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
|
|
|
|
.ctrl = OMAP4_GPIO_CTRL,
|
|
|
|
.wkup_en = OMAP4_GPIO_IRQWAKEN0,
|
|
|
|
.leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
|
|
|
|
.leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
|
|
|
|
.risingdetect = OMAP4_GPIO_RISINGDETECT,
|
|
|
|
.fallingdetect = OMAP4_GPIO_FALLINGDETECT,
|
|
|
|
};
|
|
|
|
|
2013-02-06 11:44:32 +01:00
|
|
|
static const struct omap_gpio_platform_data omap2_pdata = {
|
2011-08-16 11:53:02 +02:00
|
|
|
.regs = &omap2_gpio_regs,
|
|
|
|
.bank_width = 32,
|
|
|
|
.dbck_flag = false,
|
|
|
|
};
|
|
|
|
|
2013-02-06 11:44:32 +01:00
|
|
|
static const struct omap_gpio_platform_data omap3_pdata = {
|
2011-08-16 11:53:02 +02:00
|
|
|
.regs = &omap2_gpio_regs,
|
|
|
|
.bank_width = 32,
|
|
|
|
.dbck_flag = true,
|
|
|
|
};
|
|
|
|
|
2013-02-06 11:44:32 +01:00
|
|
|
static const struct omap_gpio_platform_data omap4_pdata = {
|
2011-08-16 11:53:02 +02:00
|
|
|
.regs = &omap4_gpio_regs,
|
|
|
|
.bank_width = 32,
|
|
|
|
.dbck_flag = true,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct of_device_id omap_gpio_match[] = {
|
|
|
|
{
|
|
|
|
.compatible = "ti,omap4-gpio",
|
|
|
|
.data = &omap4_pdata,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,omap3-gpio",
|
|
|
|
.data = &omap3_pdata,
|
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "ti,omap2-gpio",
|
|
|
|
.data = &omap2_pdata,
|
|
|
|
},
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, omap_gpio_match);
|
|
|
|
#endif
|
|
|
|
|
2010-12-08 01:26:57 +01:00
|
|
|
static struct platform_driver omap_gpio_driver = {
|
|
|
|
.probe = omap_gpio_probe,
|
|
|
|
.driver = {
|
|
|
|
.name = "omap_gpio",
|
2011-09-29 03:53:22 +02:00
|
|
|
.pm = &gpio_pm_ops,
|
2011-08-16 11:53:02 +02:00
|
|
|
.of_match_table = of_match_ptr(omap_gpio_match),
|
2010-12-08 01:26:57 +01:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2005-07-10 20:58:15 +02:00
|
|
|
/*
|
2010-12-08 01:26:57 +01:00
|
|
|
* gpio driver register needs to be done before
|
|
|
|
* machine_init functions access gpio APIs.
|
|
|
|
* Hence omap_gpio_drv_reg() is a postcore_initcall.
|
2005-07-10 20:58:15 +02:00
|
|
|
*/
|
2010-12-08 01:26:57 +01:00
|
|
|
static int __init omap_gpio_drv_reg(void)
|
2005-07-10 20:58:15 +02:00
|
|
|
{
|
2010-12-08 01:26:57 +01:00
|
|
|
return platform_driver_register(&omap_gpio_driver);
|
2005-07-10 20:58:15 +02:00
|
|
|
}
|
2010-12-08 01:26:57 +01:00
|
|
|
postcore_initcall(omap_gpio_drv_reg);
|