Commit Graph

5067 Commits

Author SHA1 Message Date
Gabor Juhos 15b6dcba42 MIPS: add dummy pci_load_of_ranges
The pci_load_of_ranges function is only available if
CONFIG_OF is selected. If the function is used without
CONFIG_OF being enabled it will cause a build error.

Add a dummy inline function to avoid this.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4911/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:37 +01:00
Gabor Juhos 2228317877 MIPS: avoid possible resource conflict in register_pci_controller
The IO and memory resources of a PCI controller
might already have a parent resource set when
they are passed to 'register_pci_controller'.

If the parent resource is set, the request_resource
call will fail due to resource conflict and the
current code will not be able to register the
PCI controller.

Use the parent resource if it is available in the
request_resource call to avoid the isssue.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4910/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:37 +01:00
Gabor Juhos 6e783865b4 MIPS: ath79: remove unused ar7{1x,24}x_pcibios_init functions
The functions are unused now, so remove them.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4909/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:36 +01:00
Gabor Juhos 9fc1ca5b73 MIPS: ath79: register platform devices for the PCI controllers
The pci-ar71xx and pci-ar724x drivers were converted
into platform drivers. Register the corresponding
platform devices for the PCI controllers instead
of using the ar7{1x,24}x_pcibios_init functions.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4908/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:36 +01:00
Gabor Juhos ad4ce92e91 MIPS: ath79: move global PCI defines into a common header
The constants will be used by a subsequent patch.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4907/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:35 +01:00
Gabor Juhos fb167e891d MIPS: pci-ar71xx: convert into a platform driver
The patch converts the pci-ar71xx driver into a
platform driver. This makes it possible to register
the PCI controller as a plain platform device.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4906/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:35 +01:00
Gabor Juhos 58d2e9bcd6 MIPS: pci-ar724x: convert into a platform driver
The patch converts the pci-ar724x driver into a
platform driver. This makes it possible to register
the PCI controller as a plain platform device.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4905/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:35 +01:00
Gabor Juhos d3d2b4200b MIPS: ralink: add CPU interrupt controller to of_irq_ids
Convert the ralink IRQ code to make use of the new MIPS IRQ controller OF
mappings.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4900/
2013-02-17 01:25:34 +01:00
Gabor Juhos 0916b46962 MIPS: add irqdomain support for the CPU IRQ controller
Add code to load a irq_domain for the MIPS IRQ controller from a devicetree
file.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Signed-off-by: John Crispin <blogic@openwrt.org>
Acked-by: David Daney <david.daney@cavium.com>
Patchwork: http://patchwork.linux-mips.org/patch/4902/
2013-02-17 01:25:34 +01:00
John Crispin 6d63d70f9f MIPS: ralink: adds default config file
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:33 +01:00
John Crispin ae2b5bb657 MIPS: ralink: adds Kbuild files
Add the Kbuild symbols and Makefiles needed to actually build the ralink code
from this series

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4899/
2013-02-17 01:25:32 +01:00
John Crispin 5644da4f63 MIPS: ralink: adds rt305x devicetree
This adds the devicetree file that describes the rt305x evaluation kit.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4898/
2013-02-17 01:25:32 +01:00
John Crispin 2809b31770 MIPS: ralink: adds support for RT305x SoC family
Add support code for rt3050, rt3052, rt3350, rt3352 and rt5350 SOC.

The code detects the SoC and registers the clk / pinmux settings.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4896/
2013-02-17 01:25:31 +01:00
John Crispin 5fff610b7c MIPS: ralink: adds early_printk support
Add the code needed to make early printk work.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4897/
2013-02-17 01:25:31 +01:00
John Crispin 3a5bfe7bdb MIPS: ralink: adds OF code
Until there is a generic MIPS way of handing the DTB over from bootloader to
kernel we rely on a built in devicetrees. The OF code also remaps those register
ranges that we use global in our drivers.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4895/
2013-02-17 01:25:31 +01:00
John Crispin 3f0a06b036 MIPS: ralink: adds clkdev code
These SoCs have a limited number of fixed rate clocks. Add support for the
clk and clkdev api.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4894/
2013-02-17 01:25:30 +01:00
John Crispin 7e47cefa69 MIPS: ralink: adds prom and cmdline code
Add minimal code to handle commandlines.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4892/
2013-02-17 01:25:30 +01:00
John Crispin c06e836ada MIPS: ralink: adds reset code
Resetting these SoCs requires no real magic. The code is straight forward.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4891/
2013-02-17 01:25:29 +01:00
John Crispin 19d3814e7b MIPS: ralink: adds irq code
All of the Ralink Wifi SoC currently supported by this series share the same
interrupt controller (INTC).

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4890/
2013-02-17 01:25:29 +01:00
John Crispin 8563991026 MIPS: ralink: adds include files
Before we start adding the platform code we add the common include files.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4893/
2013-02-17 01:25:28 +01:00
Gabor Juhos 9c099c4e79 MIPS: ath79: simplify MISC IRQ handling
The current code uses multiple if statements for
demultiplexing the different interrupt sources.
Additionally, the MISC interrupt controller has
32 interrupt sources and the current code does not
handles all of them.

Get rid of the if statements and process all interrupt
sources in a loop to fix these issues.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4874/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:27 +01:00
Gabor Juhos f160a289e0 MIPS: ath79: simplify ath79_gpio_function_* routines
Make ath79_gpio_function_{en,dis}able to be wrappers
around ath79_gpio_function_setup.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4871/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:27 +01:00
Gabor Juhos 8838becdf5 MIPS: ath79: fix GPIO function selection for AR934x SoCs
GPIO function selection is not working on the AR934x
SoCs because the offset of the function selection
register is different on those.

Add a helper routine which returns the correct
register address based on the SoC type, and use
that in the 'ath79_gpio_function_*' routines.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4870/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:27 +01:00
Steven J. Hill 778eeb1b19 MIPS: Add new GIC clocksource.
Add new clocksource that uses the counter present on the MIPS
Global Interrupt Controller.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4681/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 01:25:21 +01:00
Steven J. Hill 4cb764b454 MIPS: dsp: Simplify the DSP macros.
Simplify the DSP macros for vanilla (non-microMIPS) kernels and
toolchains that do not support the DSP ASEs.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4687/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:24 +01:00
Steven J. Hill d0c1b478e0 MIPS: dsp: Support toolchains without DSP ASE and microMIPS.
Add macros to support the DSP ASE with microMIPS kernels when the
toolchain does not have support.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4686/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:24 +01:00
Steven J. Hill 32a7ede673 MIPS: dsp: Add assembler support for DSP ASEs.
Newer toolchains support the DSP and DSP Rev2 instructions. This patch
performs a check for that support and adds compiler and assembler
flags for only the files that need use those instructions.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: Florian Fainelli <florian@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4752/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:23 +01:00
Steven J. Hill f8fa4811db MIPS: Add support for the M14KEc core.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4682/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:23 +01:00
Steven J. Hill 127993e561 MIPS: Clean-ups for MIPS Technologies Inc. generic header file.
Clean up standard header text and remove unused #define.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Patchwork: http://patchwork.linux-mips.org/patch/4703/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:22 +01:00
Jayachandran C 7b53eb4d40 MIPS: PCI: Multi-node PCI support for Netlogic XLP
On a multi-chip XLP board, each node can have 4 PCIe links. Update
XLP PCI code to initialize PCIe on all the nodes.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4803/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:22 +01:00
Jayachandran C cba3b64303 MIPS: Netlogic: Fix for quad-XLP boot
On multi-chip boards, the first core on slave SoCs may take much
more time to wakeup. Add code to wait for the core to come up before
proceeding with the rest of the boot up.

Update xlp_wakeup_core to also skip the boot node and the boot CPU
initialization which is already complete.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4783/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:22 +01:00
Jayachandran C 37a7059bc4 MIPS: Netlogic: use preset loops per jiffy
Doing calibrate delay on a hardware thread will be inaccurate since
it depends on the load on other threads in the core. It will also
slow down the boot process when done for 128 hardware threads. Switch
to a pre-computed loops per jiffy based on the core frequency. The
value is computed based on the core frequency and roughly matches the
value calculated by calibrate_delay().

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4791/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:21 +01:00
Jayachandran C 5a4cbe3811 MIPS: Netlogic: No hazards needed for XLR/XLS
TLB and COP0 hazards are handled in hardware for Netlogic XLR/XLS
SoCs. Update hazards.h to pick more optimal set of definitions when
compiling for XLR/XLS.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4788/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:21 +01:00
Jayachandran C 8cd3d64c57 MIPS: PCI: Prevent hang on XLP reg read
Reading PCI extended register at 0x255 on a bridge will hang if there
is no device connected on the link. Make PCI read routine skip this
register.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4789/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:20 +01:00
Jayachandran C 4e45e542cd MIPS: Netlogic: Use PIC timer as a clocksource
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC
frequencey. One of these can be used as a clocksource to provide
timestamps that is common across cores. This can be used in place
of the count/compare clocksource which is per-CPU.

On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits
of the PIC counter. On XLP, the whole 64-bit can be used.

Provide common macros and functions for PIC timer registers on XLR/XLS
and XLP, and use them to register a PIC clocksource.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4786/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:20 +01:00
Jayachandran C a69ba6293d MIPS: Netlogic: Split XLP L1 i-cache among threads
Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.

The L1 dcache is already split among the threads in the core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:20 +01:00
Jayachandran C a264b5e8dc MIPS: PCI: Byteswap not needed in little-endian mode
Rename function xlp_enable_pci_bswap() to xlp_config_pci_bswap(), which
is a better description for its functionality.  When compiled in
big-endian mode, xlp_config_pci_bswap() will configure the PCIe links
to byteswap.  In little-endian mode, no swap configuration is needed
for the PCIe controller, and the function is empty.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4802/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:19 +01:00
Jayachandran C 220d9122e8 MIPS: Netlogic: Optimize EIMR/EIRR accesses in 32-bit
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr()
and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations
and update the interrupt handling code to use these functions.
Also, use the EIMR register functions to mask interrupts in the
irq code.

The 64-bit interrupt request and mask registers (EIRR and EIMR) are
accessed when the interrupts are off, and the common operations are
to set or clear a bit in these registers. Using the 64-bit c0 access
functions for these operations is not optimal in 32-bit, because it
will disable/restore interrupts and split/join the 64-bit value during
each register access.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4790/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:19 +01:00
Jayachandran C f0cb40e5c3 MIPS: Netlogic: add XLS6xx to FMN config
Add support for XLS6xx CPUs to the Fast Message Network (FMN)
configuration.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4785/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:18 +01:00
John Crispin 2636562594 MIPS: lantiq: rework external irq code
This code makes the irqs used by the EIU loadable from the DT. Additionally we
add a helper that allows the pinctrl layer to map external irqs to real irq
numbers.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4818/
2013-02-17 00:15:18 +01:00
John Crispin bae696a267 MIPS: lantiq: improve pci reset gpio handling
We need to make sure that the reset gpio is available and also set a sane
default state.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4817/
2013-02-17 00:15:17 +01:00
John Crispin d0c550dc36 MIPS: lantiq: add GPHY clock gate bits
Explicitly enable the clock gate of the internal GPHYs found on xrx200.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/
2013-02-17 00:15:17 +01:00
John Crispin 740c606e8e MIPS: lantiq: adds static clock for PP32
The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4815/
2013-02-17 00:15:17 +01:00
John Crispin 3d18c17e4f MIPS: lantiq: trivial typo fix
"nodes" is written with a single "s"

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4814/
2013-02-17 00:15:16 +01:00
John Crispin 42f3caef03 MIPS: show correct cpu name for 24KEc
Make sure 24KEc is properly identified inside /proc/cpuinfo

Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-17 00:15:16 +01:00
Ralf Baechle 5b003119ab MIPS: Cleanup break and trap codes.
Very ancient out-of-tree KDB versions were using BRK_KDB code but it's
unused in modern kernels since a long time.  Delete it.

The microMIPS encoding only reserves 4 bits for a trap code so it's time
for further weedkilling.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15 23:07:38 +01:00
Steven J. Hill 8e8dc33543 MIPS: Redefine value of BRK_BUG.
The BRK_BUG value is used in the BUG and __BUG_ON inline macros. For
standard MIPS cores the code in the 'tne' instruction is 10-bits long.
In microMIPS, the 'tne' instruction is recoded and the code can only be
4-bits long. We change the value to 12 instead of 512 so that both classic
and microMIPS kernels build.

[ralf@linux-mips.org: Many of the break codes starting from 0 are used
across many MIPS UNIX variants.  Codes starting from 512 are operating
system specific additions.  1023 again is also used by other operating
systems]

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15 23:07:38 +01:00
Steven J. Hill a96102be70 MIPS: Add printing of ISA version in cpuinfo.
Display the MIPS ISA version release in the /proc/cpuinfo file.

[ralf@linux-mips.org: Add support for MIPS I ... IV legacy architecture
revisions.  Also differenciate between MIPS32 and MIPS64 versions instead
of lumping them together as just r1 and r2.

Note to application programmers: this indicates the CPU's ISA level
It does not imply the current execution environment does support it.  For
example an O32 application seeing "mips64r2" would still be restricted by
by the execution environment to 32-bit - but the kernel could run mips64r2
code.  The same for a 32-bit kernel running on a 64-bit processor.  This
field doesn't include ASEs or optional architecture modules nor other
detailed flags such as the availability of an FPU.]

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4714/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15 23:07:38 +01:00
Venkat Subbiah 0e49caf661 MIPS: Octeon: Adding driver to measure interrupt latency on Octeon.
Signed-off-by: Venkat Subbiah <venkat.subbiah@cavium.com>
[Rewrote timeing calculations]
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4660/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15 23:07:37 +01:00
Julia Lawall 42913c7992 MIPS: Loongson2: Use clk API instead of direct dereferences
A struct clk value is intended to be an abstract pointer, so it should be
manipulated using the various API functions.

clk_put is additionally added on the failure paths.

The semantic match that finds the first problem is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@@
expression e,e1;
identifier i;
@@

*e = clk_get(...)
 ... when != e = e1
     when any
*e->i
// </smpl>

Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: kernel-janitors@vger.kernel.org
Cc: linux-mips@linux-mips.org,
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4751/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-15 23:07:37 +01:00
Hauke Mehrtens 6404b7cb83 MIPS: BCM47XX: use fallback sprom var for board_{rev,type}
An SoC normally do not define path variables for board_rev and
board_type and the Broadcom SDK also uses the nvram values without a
prefix in such cases. Do the same to fill these sprom attributes from
nvram and do not leave them empty, because brcmsmac do not like this.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4679/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:57 +01:00
Hauke Mehrtens dd54dedd94 MIPS: BCM47XX: select NO_EXCEPT_FILL
The kernel is loaded to 0x80001000 so there is some space left for the
exception handlers and the kernel do not have to reserve some extra
space for them.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4747/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:57 +01:00
Hauke Mehrtens fe08f8c2c5 MIPS: BCM47XX: select BOOT_RAW
All the boot loaders I have seen are booting the kernel in raw mode by
default. CFE seems to support elf kernel images too, but the default
case is raw for the devices I know of. Select this option to make the
kernel boot on most of the devices with the default options.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4746/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:57 +01:00
Hauke Mehrtens 924ffb7dba MIPS: BCM47XX: trim the nvram values for parsing
Some nvram values on some devices have a newline character at the end
of the value, that caused read errors. Trim the string before reading
the number.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4745/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:57 +01:00
Hauke Mehrtens 111bd981e2 MIPS: BCM47XX: add bcm47xx prefix in front of nvram function names
The nvram functions are exported and used by some normal drivers. To
prevent name clashes with ofter parts of the kernel code add a bcm47xx_
prefix in front of the function names and the header file name.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4744/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:57 +01:00
Hauke Mehrtens f36738ddfe MIPS: BCM47XX: handle different nvram sizes
The old code just worked for nvram with a size of 0x8000 bytes. This
patch adds support for reading nvram from partitions of 0xF000 and
0x10000 bytes.

There is just 32KB space for the nvram, but most devices do not use the
full size and this code reads the first 32KB in that case and prints a
warning.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4743/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:56 +01:00
Hauke Mehrtens e58da16f71 MIPS: BCM47XX: rename early_nvram_init to nvram_init
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4742/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:56 +01:00
Hauke Mehrtens c4485671fb MIPS: BCM47XX: nvram add nand flash support
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4741/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:56 +01:00
Hauke Mehrtens cc4403e025 MIPS: BCM47XX: return error when init of nvram failed
This makes it possible to handle the case of not being able to read the
nvram ram. This could happen when the code searching for the specific
flash chip have not run jet.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4740/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:56 +01:00
Hauke Mehrtens ee7e2f3c23 MIPS: BCM47XX: use common error codes in nvram reads
Instead of using our own error codes use some common codes.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4739/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:56 +01:00
Rafał Miłecki bb76563214 MIPS: bcm47xx: separate functions finding flash window addr
Also check if parallel flash is present at all before accessing it and
add support for serial flash on BCMA bus.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Patchwork: http://patchwork.linux-mips.org/patch/4738/
Signed-off-by: John Crispin <blogic@openwrt.org>
2013-02-15 19:01:56 +01:00
Al Viro d64008a8f3 burying unused conditionals
__ARCH_WANT_SYS_RT_SIGACTION,
__ARCH_WANT_SYS_RT_SIGSUSPEND,
__ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND,
__ARCH_WANT_COMPAT_SYS_SCHED_RR_GET_INTERVAL - not used anymore
CONFIG_GENERIC_{SIGALTSTACK,COMPAT_RT_SIG{ACTION,QUEUEINFO,PENDING,PROCMASK}} -
can be assumed always set.
2013-02-14 09:21:15 -05:00
David S. Miller fd5023111c Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Synchronize with 'net' in order to sort out some l2tp, wireless, and
ipv6 GRE fixes that will be built on top of in 'net-next'.

Signed-off-by: David S. Miller <davem@davemloft.net>
2013-02-08 18:02:14 -05:00
James Hogan f7c819c020 arch Kconfig: Remove references to IRQ_PER_CPU
The IRQ_PER_CPU Kconfig symbol was removed in the following commit:

Commit 6a58fb3bad ("genirq: Remove
CONFIG_IRQ_PER_CPU") merged in v2.6.39-rc1.

But IRQ_PER_CPU wasn't removed from any of the architecture Kconfig
files where it was defined or selected. It's completely unused so remove
the remaining references.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: <uclinux-dist-devel@blackfin.uclinux.org>
Cc: <linux-mips@linux-mips.org>
Cc: <linuxppc-dev@lists.ozlabs.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: James E.J. Bottomley <jejb@parisc-linux.org>
Cc: Helge Deller <deller@gmx.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Acked-by: Tony Luck <tony.luck@intel.com>
Acked-by: Richard Kuo <rkuo@codeaurora.org>
Link: http://lkml.kernel.org/r/1359972583-17134-1-git-send-email-james.hogan@imgtec.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2013-02-04 18:53:20 +01:00
Al Viro 50150d2bb9 mips: switch to generic sys_fork() and sys_clone()
we still need the wrappers to store callee-saved registers in
pt_regs, but once that done we can jump to kernel/fork.c variants.

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:33:02 -05:00
Al Viro 64b3122df4 mips: take the "zero newsp means inherit the parent's one" to copy_thread()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:33:01 -05:00
Al Viro 974fdb3c20 mips: no magic arguments for sysm_pipe()
current_pt_regs() works just fine

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:33:01 -05:00
Al Viro 5e392b8db7 mips: don't bother with compat_sys_futex() wrappers
... it's COMPAT_SYSCALL_DEFINE now

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:33:01 -05:00
Al Viro aa584802e5 mips: switch to generic compat rt_sigaction()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:33:00 -05:00
Al Viro 0450d22f4b mips: switch to generic compat sched_rr_get_interval()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:33:00 -05:00
Al Viro 1910f4ab77 mips: sigsuspend() is essentially the same as rt_sigsuspend() here
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:32:59 -05:00
Al Viro ea5d83db67 mips: switch to generic compat rt_sigqueueinfo()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:32:59 -05:00
Al Viro 45cb66f797 mips: switch to generic compat rt_sigpending()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:32:59 -05:00
Al Viro 056a060803 mips: switch to generic compat rt_sigprocmask()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:32:58 -05:00
Al Viro bde208d2e1 switch mips to generic rt_sigsuspend(), make it unconditional
mips was the last architecture not using the generic variant.
Both native and compat variants switched to generic, which is
made unconditional now.

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:32:49 -05:00
Al Viro 1c37ea8277 mips: switch to compat_sys_waitid()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:32:24 -05:00
Al Viro ea536ad4f2 mips: switch to generic sigaltstack
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:32:24 -05:00
Al Viro c6489c147d Merge commit '12890d0f61fc' into arch-mips 2013-02-03 18:16:33 -05:00
Al Viro 709410a03e mips: use sane prototype for sys_rt_sigsuspend()
we want to do that before branchpoint for arch-* to be able to
consolidate sys_rt_sigsuspend() declarations.

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 18:14:17 -05:00
Al Viro 574c4866e3 consolidate kernel-side struct sigaction declarations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 15:09:22 -05:00
Al Viro 92a3ce4a1e consolidate declarations of k_sigaction
Only alpha and sparc are unusual - they have ka_restorer in it.
And nobody needs that exposed to userland.

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2013-02-03 15:09:22 -05:00
Ralf Baechle 0f3a05cb43 MIPS: MSP71xx: Move code.
Now that Yosemite's gone we can move the MSP71xx code one level up.

Shane McDonald <mcdonald.shane@gmail.com>'s
https://patchwork.linux-mips.org/patch/4736/ has been folded into this
patch.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:22 +01:00
Ralf Baechle 7034228792 MIPS: Whitespace cleanup.
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:22 +01:00
Ralf Baechle 405ab01c70 MIPS: Nuke empty lines at end of files.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:22 +01:00
Ralf Baechle 82de378caa MIPS: Nuke trailing whitespace.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:21 +01:00
Ralf Baechle e33b0451e9 MIPS: PNX8550: Remove support for SOC and JBS and STB810 boards.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:21 +01:00
Steven J. Hill 9b73100911 MIPS: SEAD3: Implement OF support.
Activate USE_OF for SEAD-3 platform. Add basic DTS file and convert memory
detection and reservations to use OF.

[ralf@linux-mips.org: Remove unnecessary #ifdef wrapper in generic.h.  Make
<asm/mips-boards/generic.h> inclusion work even without prior
<linux/of_fdt.h> inclusion.]

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4809/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:21 +01:00
Ralf Baechle 8fba1e588b MIPS: inst.h: Add MDMX and paired single instruction aka MIPS-3D formats.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:21 +01:00
Ralf Baechle 85dfaf0831 MIPS: inst.h: Eleminate per endianess structure definitions.
This makes space for further growth of the header without excessive bloat.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:20 +01:00
Ralf Baechle 90e8cacdbe MIPS: UAPI: Split inst.h into exported and kernel-only part.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:20 +01:00
Steven J. Hill b9688310d7 MIPS: Whitespace cleanups and reformatting.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Cc: Steven J. Hill <sjhill@mips.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/4781/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:20 +01:00
Ralf Baechle bc4f297554 MIPS: sysmips: Rewrite to use SYSCALL_DEFINE3().
Thanks to current_pt_regs() there is no need to use the dark MIPS magic.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:20 +01:00
Ralf Baechle 33722a2e73 MIPS: sysmips: Use unreachable().
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-02-01 10:00:20 +01:00
Al Cooper 58b69401c7 MIPS: Function tracer: Fix broken function tracing
Function tracing is currently broken for all 32 bit MIPS platforms.
When tracing is enabled, the kernel immediately hangs on boot.
This is a result of commit b732d439cb
that changes the kernel/trace/Kconfig file so that is no longer
forces FRAME_POINTER when FUNCTION_TRACING is enabled.

MIPS frame pointers are generally considered to be useless because
they cannot be used to unwind the stack. Unfortunately the MIPS
function tracing code has bugs that are masked by the use of frame
pointers. This commit fixes the bugs so that MIPS frame pointers
don't need to be enabled.

The bugs are a result of the odd calling sequence used to call the trace
routine. This calling sequence is inserted into every traceable function
when the tracing CONFIG option is enabled. This sequence is generated
for 32bit MIPS platforms by the compiler via the "-pg" flag.

Part of the sequence is "addiu sp,sp,-8" in the delay slot after every
call to the trace routine "_mcount" (some legacy thing where 2 arguments
used to be pushed on the stack). The _mcount routine is expected to
adjust the sp by +8 before returning.  So when not disabled, the original
jalr and addiu will be there, so _mcount has to adjust sp.

The problem is that when tracing is disabled for a function, the
"jalr _mcount" instruction is replaced with a nop, but the
"addiu sp,sp,-8" is still executed and the stack pointer is left
trashed. When frame pointers are enabled the problem is masked
because any access to the stack is done through the frame
pointer and the stack pointer is restored from the frame pointer when
the function returns.

This patch writes two nops starting at the address of the "jalr _mcount"
instruction whenever tracing is disabled. This means that the
"addiu sp,sp.-8" will be converted to a nop along with the "jalr".  When
disabled, there will be two nops.

This is SMP safe because the first time this happens is during
ftrace_init() which is before any other processor has been started.
Subsequent calls to enable/disable tracing when other CPUs ARE running
will still be safe because the enable will only change the first nop
to a "jalr" and the disable, while writing 2 nops, will only be changing
the "jalr". This patch also stops using stop_machine() to call the
tracer enable/disable routines and calls them directly because the
routines are SMP safe.

When the kernel first boots we have to be able to handle the gcc
generated jalr, addui sequence until ftrace_init gets a chance to run
and change the sequence. At this point mcount just adjusts the stack
and returns. When ftrace_init runs, we convert the jalr/addui to nops.
Then whenever tracing is enabled we convert the first nop to a "jalr
mcount+8". The mcount+8 entry point skips the stack adjust.

[ralf@linux-mips.org: Folded in  Steven Rostedt's build fix.]

Signed-off-by: Al Cooper <alcooperx@gmail.com>
Cc: rostedt@goodmis.org
Cc: ddaney.cavm@gmail.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4806/
Patchwork: https://patchwork.linux-mips.org/patch/4841/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-31 15:28:48 +01:00
Steven Rostedt 196897a297 mips: Move __virt_addr_valid() to a place for MIPS 64
Commit d3ce884318 "MIPS: Fix modpost error in modules attepting to use
virt_addr_valid()" moved __virt_addr_valid() from a macro in a header
file to a function in ioremap.c. But ioremap.c is only compiled for MIPS
32, and not for MIPS 64.

When compiling for my yeeloong2, which supposedly supports hibernation,
which compiles kernel/power/snapshot.c which calls virt_addr_valid(), I
got this error:

  LD      init/built-in.o
kernel/built-in.o: In function `memory_bm_free':
snapshot.c:(.text+0x4c9c4): undefined reference to `__virt_addr_valid'
snapshot.c:(.text+0x4ca58): undefined reference to `__virt_addr_valid'
kernel/built-in.o: In function `snapshot_write_next':
(.text+0x4e44c): undefined reference to `__virt_addr_valid'
kernel/built-in.o: In function `snapshot_write_next':
(.text+0x4e890): undefined reference to `__virt_addr_valid'
make[1]: *** [vmlinux] Error 1
make: *** [sub-make] Error 2

I suspect that __virt_addr_valid() is fine for mips 64. I moved it to
mmap.c such that it gets compiled for mips 64 and 32.

Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4842/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-31 15:14:59 +01:00
Jayachandran C 26f5ae865d MIPS: Netlogic: Fix UP compilation on XLR
The commit 2a37b1a "MIPS: Netlogic: Move from u32 cpumask to cpumask_t"
breaks uniprocessor compilation on XLR with:

arch/mips/netlogic/xlr/setup.c: In function 'prom_init':
arch/mips/netlogic/xlr/setup.c:196:6: error: unused variable 'i'

Fix by defining 'i' only when CONFIG_SMP is defined.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4760/
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-30 21:44:18 +01:00
Gabor Juhos fe950df700 MIPS: AR71xx: Fix AR71XX_PCI_MEM_SIZE
The base address of the PCI memory is 0x10000000 and the base address of the
PCI configuration space is 0x17000000 on the AR71xx SoCs.

The AR71XX_PCI_MEM_SIZE is defined as 0x08000000 which is wrong because that
overlaps with the configuration space.  This patch fixes the value of the
AR71XX_PCI_MEM_SIZE constant, in order to avoid this resource conflicts.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4873/
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-30 21:43:11 +01:00
Gabor Juhos 4c960910e2 MIPS: AR724x: Fix AR724X_PCI_MEM_SIZE
The base address of the PCI memory is
0x10000000 and the base address of the
PCI configuration space is 0x14000000
on the AR724x SoCs.

The AR724X_PCI_MEM_SIZE is defined as
0x08000000 which is wrong because that
overlaps  with the configuration space.

The patch fixes the value of the
AR724X_PCI_MEM_SIZE constant, in order
to avoid this resource conflicts.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4872/
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-30 21:42:41 +01:00
John Crispin 79d61a046b MIPS: Lantiq: Fix cp0_perfcount_irq mapping
The introduction of the OF support broke the cp0_perfcount_irq mapping. This
resulted in oprofile not working anymore.

Offending commit is :

commit 3645da0276
Author: John Crispin <blogic@openwrt.org>
Date:   Tue Apr 17 10:18:32 2012 +0200

OF: MIPS: lantiq: implement irq_domain support

Signed-off-by: Conor O'Gorman <i@conorogorman.net>
Signed-off-by: John Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4875/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-01-30 21:28:28 +01:00
Yinghai Lu ac2cbab21f x86: Don't panic if can not alloc buffer for swiotlb
Normal boot path on system with iommu support:
swiotlb buffer will be allocated early at first and then try to initialize
iommu, if iommu for intel or AMD could setup properly, swiotlb buffer
will be freed.

The early allocating is with bootmem, and could panic when we try to use
kdump with buffer above 4G only, or with memmap to limit mem under 4G.
for example: memmap=4095M$1M to remove memory under 4G.

According to Eric, add _nopanic version and no_iotlb_memory to fail
map single later if swiotlb is still needed.

-v2: don't pass nopanic, and use -ENOMEM return value according to Eric.
     panic early instead of using swiotlb_full to panic...according to Eric/Konrad.
-v3: make swiotlb_init to be notpanic, but will affect:
     arm64, ia64, powerpc, tile, unicore32, x86.
-v4: cleanup swiotlb_init by removing swiotlb_init_with_default_size.

Suggested-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Link: http://lkml.kernel.org/r/1359058816-7615-36-git-send-email-yinghai@kernel.org
Reviewed-and-tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Jeremy Fitzhardinge <jeremy@goop.org>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Cc: linux-mips@linux-mips.org
Cc: xen-devel@lists.xensource.com
Cc: virtualization@lists.linux-foundation.org
Cc: Shuah Khan <shuahkhan@gmail.com>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
2013-01-29 19:36:53 -08:00