2005-03-13 10:43:36 +01:00
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/*
|
2006-09-03 18:09:07 +02:00
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* QEMU ESP/NCR53C9x emulation
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2007-09-16 23:08:06 +02:00
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*
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2006-03-11 17:29:14 +01:00
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* Copyright (c) 2005-2006 Fabrice Bellard
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2012-07-09 12:02:31 +02:00
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* Copyright (c) 2012 Herve Poussineau
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2007-09-16 23:08:06 +02:00
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*
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2005-03-13 10:43:36 +01:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2008-04-09 18:32:48 +02:00
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2016-01-26 19:17:16 +01:00
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#include "qemu/osdep.h"
|
2013-02-04 15:40:22 +01:00
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#include "hw/sysbus.h"
|
2013-02-05 17:06:20 +01:00
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#include "hw/scsi/esp.h"
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2011-09-11 17:54:18 +02:00
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#include "trace.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
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#include "qapi/error.h"
|
2012-12-17 18:20:00 +01:00
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#include "qemu/log.h"
|
2005-03-13 10:43:36 +01:00
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2006-09-03 18:09:07 +02:00
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/*
|
2007-12-01 15:51:23 +01:00
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* On Sparc32, this is the ESP (NCR53C90) part of chip STP2000 (Master I/O),
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* also produced as NCR89C100. See
|
2006-09-03 18:09:07 +02:00
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
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* and
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* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt
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*/
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|
2008-04-24 19:20:25 +02:00
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static void esp_raise_irq(ESPState *s)
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|
|
{
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if (!(s->rregs[ESP_RSTAT] & STAT_INT)) {
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s->rregs[ESP_RSTAT] |= STAT_INT;
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|
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qemu_irq_raise(s->irq);
|
2011-09-11 17:54:18 +02:00
|
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|
trace_esp_raise_irq();
|
2008-04-24 19:20:25 +02:00
|
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|
}
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|
}
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static void esp_lower_irq(ESPState *s)
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|
|
|
{
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|
|
if (s->rregs[ESP_RSTAT] & STAT_INT) {
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|
s->rregs[ESP_RSTAT] &= ~STAT_INT;
|
|
|
|
qemu_irq_lower(s->irq);
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_lower_irq();
|
2008-04-24 19:20:25 +02:00
|
|
|
}
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|
|
}
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|
2012-08-04 21:10:03 +02:00
|
|
|
void esp_dma_enable(ESPState *s, int irq, int level)
|
2010-09-11 18:38:33 +02:00
|
|
|
{
|
|
|
|
if (level) {
|
|
|
|
s->dma_enabled = 1;
|
2011-09-11 17:54:18 +02:00
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|
trace_esp_dma_enable();
|
2010-09-11 18:38:33 +02:00
|
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|
if (s->dma_cb) {
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|
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|
s->dma_cb(s);
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|
s->dma_cb = NULL;
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|
}
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|
} else {
|
2011-09-11 17:54:18 +02:00
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|
trace_esp_dma_disable();
|
2010-09-11 18:38:33 +02:00
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|
s->dma_enabled = 0;
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|
}
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|
}
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|
2012-08-04 21:10:03 +02:00
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|
void esp_request_cancelled(SCSIRequest *req)
|
2011-04-18 22:53:08 +02:00
|
|
|
{
|
2012-07-09 12:02:27 +02:00
|
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|
ESPState *s = req->hba_private;
|
2011-04-18 22:53:08 +02:00
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|
|
if (req == s->current_req) {
|
|
|
|
scsi_req_unref(s->current_req);
|
|
|
|
s->current_req = NULL;
|
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|
|
s->current_dev = NULL;
|
|
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|
}
|
|
|
|
}
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|
2016-05-19 12:39:31 +02:00
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static uint32_t get_cmd(ESPState *s, uint8_t *buf, uint8_t buflen)
|
2005-04-06 22:31:50 +02:00
|
|
|
{
|
2006-08-29 06:52:16 +02:00
|
|
|
uint32_t dmalen;
|
2005-04-06 22:31:50 +02:00
|
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int target;
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|
2008-11-29 17:45:28 +01:00
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target = s->wregs[ESP_WBUSID] & BUSID_DID;
|
2005-10-30 18:24:05 +01:00
|
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|
if (s->dma) {
|
2012-08-02 15:43:39 +02:00
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dmalen = s->rregs[ESP_TCLO];
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dmalen |= s->rregs[ESP_TCMID] << 8;
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|
dmalen |= s->rregs[ESP_TCHI] << 16;
|
2016-05-19 12:39:31 +02:00
|
|
|
if (dmalen > buflen) {
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|
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|
return 0;
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|
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|
}
|
2008-03-02 09:48:47 +01:00
|
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s->dma_memory_read(s->dma_opaque, buf, dmalen);
|
2005-10-30 18:24:05 +01:00
|
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|
} else {
|
2008-11-29 17:51:02 +01:00
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dmalen = s->ti_size;
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memcpy(buf, s->ti_buf, dmalen);
|
2011-07-02 17:23:00 +02:00
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buf[0] = buf[2] >> 5;
|
2005-10-30 18:24:05 +01:00
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}
|
2011-09-11 17:54:18 +02:00
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trace_esp_get_cmd(dmalen, target);
|
2006-05-26 01:58:51 +02:00
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2005-04-06 22:31:50 +02:00
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s->ti_size = 0;
|
2005-10-30 18:24:05 +01:00
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s->ti_rptr = 0;
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s->ti_wptr = 0;
|
2005-04-06 22:31:50 +02:00
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|
2011-07-09 16:44:41 +02:00
|
|
|
if (s->current_req) {
|
2006-08-29 06:52:16 +02:00
|
|
|
/* Started a new command before the old one finished. Cancel it. */
|
2011-04-18 22:53:08 +02:00
|
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|
scsi_req_cancel(s->current_req);
|
2006-08-29 06:52:16 +02:00
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|
s->async_len = 0;
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|
}
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|
2011-07-27 23:24:50 +02:00
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|
s->current_dev = scsi_device_find(&s->bus, 0, target, 0);
|
2011-07-28 18:02:13 +02:00
|
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|
if (!s->current_dev) {
|
2006-05-26 01:58:51 +02:00
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|
// No such drive
|
2008-04-24 19:20:25 +02:00
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|
s->rregs[ESP_RSTAT] = 0;
|
2007-12-01 15:51:23 +01:00
|
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|
s->rregs[ESP_RINTR] = INTR_DC;
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s->rregs[ESP_RSEQ] = SEQ_0;
|
2008-04-24 19:20:25 +02:00
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|
esp_raise_irq(s);
|
2007-10-06 13:28:21 +02:00
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|
return 0;
|
2005-04-06 22:31:50 +02:00
|
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|
}
|
2006-06-03 16:19:19 +02:00
|
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|
return dmalen;
|
|
|
|
}
|
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|
2009-09-05 08:24:47 +02:00
|
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|
static void do_busid_cmd(ESPState *s, uint8_t *buf, uint8_t busid)
|
2006-06-03 16:19:19 +02:00
|
|
|
{
|
|
|
|
int32_t datalen;
|
|
|
|
int lun;
|
2011-07-28 18:02:13 +02:00
|
|
|
SCSIDevice *current_lun;
|
2006-06-03 16:19:19 +02:00
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|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_do_busid_cmd(busid);
|
2009-09-05 08:24:47 +02:00
|
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|
lun = busid & 7;
|
2011-07-27 23:24:50 +02:00
|
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|
current_lun = scsi_device_find(&s->bus, 0, s->current_dev->id, lun);
|
2012-07-09 12:02:27 +02:00
|
|
|
s->current_req = scsi_req_new(current_lun, 0, lun, buf, s);
|
2011-08-03 10:49:10 +02:00
|
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|
datalen = scsi_req_enqueue(s->current_req);
|
2006-09-03 18:09:07 +02:00
|
|
|
s->ti_size = datalen;
|
|
|
|
if (datalen != 0) {
|
2008-04-24 19:20:25 +02:00
|
|
|
s->rregs[ESP_RSTAT] = STAT_TC;
|
2006-08-29 06:52:16 +02:00
|
|
|
s->dma_left = 0;
|
2006-09-17 05:20:58 +02:00
|
|
|
s->dma_counter = 0;
|
2006-05-26 01:58:51 +02:00
|
|
|
if (datalen > 0) {
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RSTAT] |= STAT_DI;
|
2006-05-26 01:58:51 +02:00
|
|
|
} else {
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RSTAT] |= STAT_DO;
|
2005-12-05 21:30:36 +01:00
|
|
|
}
|
2011-04-18 15:28:11 +02:00
|
|
|
scsi_req_continue(s->current_req);
|
2005-04-06 22:31:50 +02:00
|
|
|
}
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
|
|
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
2008-04-24 19:20:25 +02:00
|
|
|
esp_raise_irq(s);
|
2005-04-06 22:31:50 +02:00
|
|
|
}
|
|
|
|
|
2009-09-05 08:24:47 +02:00
|
|
|
static void do_cmd(ESPState *s, uint8_t *buf)
|
|
|
|
{
|
|
|
|
uint8_t busid = buf[0];
|
|
|
|
|
|
|
|
do_busid_cmd(s, &buf[1], busid);
|
|
|
|
}
|
|
|
|
|
2006-06-03 16:19:19 +02:00
|
|
|
static void handle_satn(ESPState *s)
|
|
|
|
{
|
|
|
|
uint8_t buf[32];
|
|
|
|
int len;
|
|
|
|
|
2012-07-09 12:02:22 +02:00
|
|
|
if (s->dma && !s->dma_enabled) {
|
2010-09-11 18:38:33 +02:00
|
|
|
s->dma_cb = handle_satn;
|
|
|
|
return;
|
|
|
|
}
|
2016-05-19 12:39:31 +02:00
|
|
|
len = get_cmd(s, buf, sizeof(buf));
|
2006-06-03 16:19:19 +02:00
|
|
|
if (len)
|
|
|
|
do_cmd(s, buf);
|
|
|
|
}
|
|
|
|
|
2009-09-05 08:24:47 +02:00
|
|
|
static void handle_s_without_atn(ESPState *s)
|
|
|
|
{
|
|
|
|
uint8_t buf[32];
|
|
|
|
int len;
|
|
|
|
|
2012-07-09 12:02:22 +02:00
|
|
|
if (s->dma && !s->dma_enabled) {
|
2010-09-11 18:38:33 +02:00
|
|
|
s->dma_cb = handle_s_without_atn;
|
|
|
|
return;
|
|
|
|
}
|
2016-05-19 12:39:31 +02:00
|
|
|
len = get_cmd(s, buf, sizeof(buf));
|
2009-09-05 08:24:47 +02:00
|
|
|
if (len) {
|
|
|
|
do_busid_cmd(s, buf, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-06-03 16:19:19 +02:00
|
|
|
static void handle_satn_stop(ESPState *s)
|
|
|
|
{
|
2012-07-09 12:02:22 +02:00
|
|
|
if (s->dma && !s->dma_enabled) {
|
2010-09-11 18:38:33 +02:00
|
|
|
s->dma_cb = handle_satn_stop;
|
|
|
|
return;
|
|
|
|
}
|
2016-05-19 12:39:31 +02:00
|
|
|
s->cmdlen = get_cmd(s, s->cmdbuf, sizeof(s->cmdbuf));
|
2006-06-03 16:19:19 +02:00
|
|
|
if (s->cmdlen) {
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_handle_satn_stop(s->cmdlen);
|
2006-06-03 16:19:19 +02:00
|
|
|
s->do_cmd = 1;
|
2008-04-24 19:20:25 +02:00
|
|
|
s->rregs[ESP_RSTAT] = STAT_TC | STAT_CD;
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
|
|
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
2008-04-24 19:20:25 +02:00
|
|
|
esp_raise_irq(s);
|
2006-06-03 16:19:19 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-26 23:53:41 +02:00
|
|
|
static void write_response(ESPState *s)
|
2005-04-06 22:31:50 +02:00
|
|
|
{
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_write_response(s->status);
|
2011-05-20 20:10:02 +02:00
|
|
|
s->ti_buf[0] = s->status;
|
2006-05-26 23:53:41 +02:00
|
|
|
s->ti_buf[1] = 0;
|
2005-10-30 18:24:05 +01:00
|
|
|
if (s->dma) {
|
2008-03-02 09:48:47 +01:00
|
|
|
s->dma_memory_write(s->dma_opaque, s->ti_buf, 2);
|
2008-04-24 19:20:25 +02:00
|
|
|
s->rregs[ESP_RSTAT] = STAT_TC | STAT_ST;
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_BS | INTR_FC;
|
|
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
2005-10-30 18:24:05 +01:00
|
|
|
} else {
|
2007-10-06 13:28:21 +02:00
|
|
|
s->ti_size = 2;
|
|
|
|
s->ti_rptr = 0;
|
|
|
|
s->ti_wptr = 0;
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RFLAGS] = 2;
|
2005-10-30 18:24:05 +01:00
|
|
|
}
|
2008-04-24 19:20:25 +02:00
|
|
|
esp_raise_irq(s);
|
2005-04-06 22:31:50 +02:00
|
|
|
}
|
2005-10-30 18:24:05 +01:00
|
|
|
|
2006-08-29 06:52:16 +02:00
|
|
|
static void esp_dma_done(ESPState *s)
|
|
|
|
{
|
2008-04-24 19:20:25 +02:00
|
|
|
s->rregs[ESP_RSTAT] |= STAT_TC;
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_BS;
|
|
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
|
|
s->rregs[ESP_RFLAGS] = 0;
|
|
|
|
s->rregs[ESP_TCLO] = 0;
|
|
|
|
s->rregs[ESP_TCMID] = 0;
|
2012-08-02 15:43:39 +02:00
|
|
|
s->rregs[ESP_TCHI] = 0;
|
2008-04-24 19:20:25 +02:00
|
|
|
esp_raise_irq(s);
|
2006-08-29 06:52:16 +02:00
|
|
|
}
|
|
|
|
|
2006-08-12 03:04:27 +02:00
|
|
|
static void esp_do_dma(ESPState *s)
|
|
|
|
{
|
2006-09-03 18:09:07 +02:00
|
|
|
uint32_t len;
|
2006-08-12 03:04:27 +02:00
|
|
|
int to_device;
|
2006-08-29 06:52:16 +02:00
|
|
|
|
2006-09-03 18:09:07 +02:00
|
|
|
to_device = (s->ti_size < 0);
|
2006-08-29 06:52:16 +02:00
|
|
|
len = s->dma_left;
|
2006-08-12 03:04:27 +02:00
|
|
|
if (s->do_cmd) {
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_do_dma(s->cmdlen, len);
|
2008-03-02 09:48:47 +01:00
|
|
|
s->dma_memory_read(s->dma_opaque, &s->cmdbuf[s->cmdlen], len);
|
2006-08-12 03:04:27 +02:00
|
|
|
s->ti_size = 0;
|
|
|
|
s->cmdlen = 0;
|
|
|
|
s->do_cmd = 0;
|
|
|
|
do_cmd(s, s->cmdbuf);
|
|
|
|
return;
|
2006-08-29 06:52:16 +02:00
|
|
|
}
|
|
|
|
if (s->async_len == 0) {
|
|
|
|
/* Defer until data is available. */
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
if (len > s->async_len) {
|
|
|
|
len = s->async_len;
|
|
|
|
}
|
|
|
|
if (to_device) {
|
2008-03-02 09:48:47 +01:00
|
|
|
s->dma_memory_read(s->dma_opaque, s->async_buf, len);
|
2006-08-12 03:04:27 +02:00
|
|
|
} else {
|
2008-03-02 09:48:47 +01:00
|
|
|
s->dma_memory_write(s->dma_opaque, s->async_buf, len);
|
2006-08-29 06:52:16 +02:00
|
|
|
}
|
|
|
|
s->dma_left -= len;
|
|
|
|
s->async_buf += len;
|
|
|
|
s->async_len -= len;
|
2006-09-17 05:20:58 +02:00
|
|
|
if (to_device)
|
|
|
|
s->ti_size += len;
|
|
|
|
else
|
|
|
|
s->ti_size -= len;
|
2006-08-29 06:52:16 +02:00
|
|
|
if (s->async_len == 0) {
|
2011-04-18 15:28:11 +02:00
|
|
|
scsi_req_continue(s->current_req);
|
|
|
|
/* If there is still data to be read from the device then
|
|
|
|
complete the DMA operation immediately. Otherwise defer
|
|
|
|
until the scsi layer has completed. */
|
|
|
|
if (to_device || s->dma_left != 0 || s->ti_size == 0) {
|
|
|
|
return;
|
2006-08-12 03:04:27 +02:00
|
|
|
}
|
2006-08-29 06:52:16 +02:00
|
|
|
}
|
2011-04-18 15:28:11 +02:00
|
|
|
|
|
|
|
/* Partially filled a scsi buffer. Complete immediately. */
|
|
|
|
esp_dma_done(s);
|
2006-08-12 03:04:27 +02:00
|
|
|
}
|
|
|
|
|
2012-08-04 21:10:03 +02:00
|
|
|
void esp_command_complete(SCSIRequest *req, uint32_t status,
|
2011-07-06 11:55:37 +02:00
|
|
|
size_t resid)
|
2006-05-26 01:58:51 +02:00
|
|
|
{
|
2012-07-09 12:02:27 +02:00
|
|
|
ESPState *s = req->hba_private;
|
2006-05-26 01:58:51 +02:00
|
|
|
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_command_complete();
|
2011-04-22 12:27:30 +02:00
|
|
|
if (s->ti_size != 0) {
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_command_complete_unexpected();
|
2011-04-22 12:27:30 +02:00
|
|
|
}
|
|
|
|
s->ti_size = 0;
|
|
|
|
s->dma_left = 0;
|
|
|
|
s->async_len = 0;
|
2011-05-20 20:18:07 +02:00
|
|
|
if (status) {
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_command_complete_fail();
|
2011-04-22 12:27:30 +02:00
|
|
|
}
|
2011-05-20 20:18:07 +02:00
|
|
|
s->status = status;
|
2011-04-22 12:27:30 +02:00
|
|
|
s->rregs[ESP_RSTAT] = STAT_ST;
|
|
|
|
esp_dma_done(s);
|
|
|
|
if (s->current_req) {
|
|
|
|
scsi_req_unref(s->current_req);
|
|
|
|
s->current_req = NULL;
|
|
|
|
s->current_dev = NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-08-04 21:10:03 +02:00
|
|
|
void esp_transfer_data(SCSIRequest *req, uint32_t len)
|
2011-04-22 12:27:30 +02:00
|
|
|
{
|
2012-07-09 12:02:27 +02:00
|
|
|
ESPState *s = req->hba_private;
|
2011-04-22 12:27:30 +02:00
|
|
|
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_transfer_data(s->dma_left, s->ti_size);
|
2011-05-20 20:18:07 +02:00
|
|
|
s->async_len = len;
|
2011-04-22 12:27:30 +02:00
|
|
|
s->async_buf = scsi_req_get_buf(req);
|
|
|
|
if (s->dma_left) {
|
|
|
|
esp_do_dma(s);
|
|
|
|
} else if (s->dma_counter != 0 && s->ti_size <= 0) {
|
|
|
|
/* If this was the last part of a DMA transfer then the
|
|
|
|
completion interrupt is deferred to here. */
|
2006-08-29 06:52:16 +02:00
|
|
|
esp_dma_done(s);
|
2006-08-12 03:04:27 +02:00
|
|
|
}
|
2006-05-26 01:58:51 +02:00
|
|
|
}
|
|
|
|
|
2005-04-06 22:31:50 +02:00
|
|
|
static void handle_ti(ESPState *s)
|
|
|
|
{
|
2006-08-12 03:04:27 +02:00
|
|
|
uint32_t dmalen, minlen;
|
2005-04-06 22:31:50 +02:00
|
|
|
|
2012-07-09 12:02:23 +02:00
|
|
|
if (s->dma && !s->dma_enabled) {
|
|
|
|
s->dma_cb = handle_ti;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2012-08-02 15:43:39 +02:00
|
|
|
dmalen = s->rregs[ESP_TCLO];
|
|
|
|
dmalen |= s->rregs[ESP_TCMID] << 8;
|
|
|
|
dmalen |= s->rregs[ESP_TCHI] << 16;
|
2006-05-21 14:46:31 +02:00
|
|
|
if (dmalen==0) {
|
|
|
|
dmalen=0x10000;
|
|
|
|
}
|
2006-09-17 05:20:58 +02:00
|
|
|
s->dma_counter = dmalen;
|
2006-05-21 14:46:31 +02:00
|
|
|
|
2006-06-03 16:19:19 +02:00
|
|
|
if (s->do_cmd)
|
|
|
|
minlen = (dmalen < 32) ? dmalen : 32;
|
2006-09-03 18:09:07 +02:00
|
|
|
else if (s->ti_size < 0)
|
|
|
|
minlen = (dmalen < -s->ti_size) ? dmalen : -s->ti_size;
|
2006-06-03 16:19:19 +02:00
|
|
|
else
|
|
|
|
minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_handle_ti(minlen);
|
2005-10-30 18:24:05 +01:00
|
|
|
if (s->dma) {
|
2006-08-12 03:04:27 +02:00
|
|
|
s->dma_left = minlen;
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
2006-08-12 03:04:27 +02:00
|
|
|
esp_do_dma(s);
|
2006-06-03 16:19:19 +02:00
|
|
|
} else if (s->do_cmd) {
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_handle_ti_cmd(s->cmdlen);
|
2006-06-03 16:19:19 +02:00
|
|
|
s->ti_size = 0;
|
|
|
|
s->cmdlen = 0;
|
|
|
|
s->do_cmd = 0;
|
|
|
|
do_cmd(s, s->cmdbuf);
|
|
|
|
return;
|
|
|
|
}
|
2005-04-06 22:31:50 +02:00
|
|
|
}
|
|
|
|
|
2012-08-04 21:10:03 +02:00
|
|
|
void esp_hard_reset(ESPState *s)
|
2005-03-13 10:43:36 +01:00
|
|
|
{
|
2007-05-26 19:39:43 +02:00
|
|
|
memset(s->rregs, 0, ESP_REGS);
|
|
|
|
memset(s->wregs, 0, ESP_REGS);
|
2014-11-10 16:52:55 +01:00
|
|
|
s->tchi_written = 0;
|
2006-03-11 17:29:14 +01:00
|
|
|
s->ti_size = 0;
|
|
|
|
s->ti_rptr = 0;
|
|
|
|
s->ti_wptr = 0;
|
|
|
|
s->dma = 0;
|
2006-06-03 16:19:19 +02:00
|
|
|
s->do_cmd = 0;
|
2010-09-11 18:38:33 +02:00
|
|
|
s->dma_cb = NULL;
|
2008-11-29 17:45:28 +01:00
|
|
|
|
|
|
|
s->rregs[ESP_CFG1] = 7;
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
|
|
|
|
2012-07-09 12:02:28 +02:00
|
|
|
static void esp_soft_reset(ESPState *s)
|
2010-06-10 19:57:39 +02:00
|
|
|
{
|
|
|
|
qemu_irq_lower(s->irq);
|
2012-07-09 12:02:28 +02:00
|
|
|
esp_hard_reset(s);
|
2010-06-10 19:57:39 +02:00
|
|
|
}
|
|
|
|
|
2012-07-09 12:02:28 +02:00
|
|
|
static void parent_esp_reset(ESPState *s, int irq, int level)
|
2007-08-16 21:56:27 +02:00
|
|
|
{
|
2010-06-10 19:57:39 +02:00
|
|
|
if (level) {
|
2012-07-09 12:02:28 +02:00
|
|
|
esp_soft_reset(s);
|
2010-06-10 19:57:39 +02:00
|
|
|
}
|
2007-08-16 21:56:27 +02:00
|
|
|
}
|
|
|
|
|
2012-08-04 21:10:03 +02:00
|
|
|
uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
|
2010-09-11 18:38:33 +02:00
|
|
|
{
|
2012-07-09 12:02:28 +02:00
|
|
|
uint32_t old_val;
|
2010-09-11 18:38:33 +02:00
|
|
|
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_readb(saddr, s->rregs[saddr]);
|
2005-03-13 10:43:36 +01:00
|
|
|
switch (saddr) {
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_FIFO:
|
2007-10-06 13:28:21 +02:00
|
|
|
if (s->ti_size > 0) {
|
|
|
|
s->ti_size--;
|
2007-12-01 15:51:23 +01:00
|
|
|
if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
|
2008-11-29 17:45:28 +01:00
|
|
|
/* Data out. */
|
2012-07-09 12:02:29 +02:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"esp: PIO data read not implemented\n");
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_FIFO] = 0;
|
2006-05-26 01:58:51 +02:00
|
|
|
} else {
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
|
2006-05-26 01:58:51 +02:00
|
|
|
}
|
2008-04-24 19:20:25 +02:00
|
|
|
esp_raise_irq(s);
|
2007-10-06 13:28:21 +02:00
|
|
|
}
|
|
|
|
if (s->ti_size == 0) {
|
2005-10-30 18:24:05 +01:00
|
|
|
s->ti_rptr = 0;
|
|
|
|
s->ti_wptr = 0;
|
|
|
|
}
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_RINTR:
|
2009-07-31 09:26:44 +02:00
|
|
|
/* Clear sequence step, interrupt register and all status bits
|
|
|
|
except TC */
|
|
|
|
old_val = s->rregs[ESP_RINTR];
|
|
|
|
s->rregs[ESP_RINTR] = 0;
|
|
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
|
|
|
s->rregs[ESP_RSEQ] = SEQ_CD;
|
2008-04-24 19:20:25 +02:00
|
|
|
esp_lower_irq(s);
|
2009-07-31 09:26:44 +02:00
|
|
|
|
|
|
|
return old_val;
|
2014-11-10 16:52:55 +01:00
|
|
|
case ESP_TCHI:
|
|
|
|
/* Return the unique id if the value has never been written */
|
|
|
|
if (!s->tchi_written) {
|
|
|
|
return s->chip_id;
|
|
|
|
}
|
2005-03-13 10:43:36 +01:00
|
|
|
default:
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
2005-04-06 22:31:50 +02:00
|
|
|
return s->rregs[saddr];
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
|
|
|
|
2012-08-04 21:10:03 +02:00
|
|
|
void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
|
2005-03-13 10:43:36 +01:00
|
|
|
{
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb(saddr, s->wregs[saddr], val);
|
2005-03-13 10:43:36 +01:00
|
|
|
switch (saddr) {
|
2014-11-10 16:52:55 +01:00
|
|
|
case ESP_TCHI:
|
|
|
|
s->tchi_written = true;
|
|
|
|
/* fall through */
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_TCLO:
|
|
|
|
case ESP_TCMID:
|
|
|
|
s->rregs[ESP_RSTAT] &= ~STAT_TC;
|
2005-10-30 18:24:05 +01:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_FIFO:
|
2006-06-03 16:19:19 +02:00
|
|
|
if (s->do_cmd) {
|
2016-05-19 12:39:30 +02:00
|
|
|
if (s->cmdlen < TI_BUFSZ) {
|
|
|
|
s->cmdbuf[s->cmdlen++] = val & 0xff;
|
|
|
|
} else {
|
|
|
|
trace_esp_error_fifo_overrun();
|
|
|
|
}
|
2008-11-29 17:45:28 +01:00
|
|
|
} else if (s->ti_size == TI_BUFSZ - 1) {
|
2012-07-09 12:02:29 +02:00
|
|
|
trace_esp_error_fifo_overrun();
|
2006-05-26 01:58:51 +02:00
|
|
|
} else {
|
|
|
|
s->ti_size++;
|
|
|
|
s->ti_buf[s->ti_wptr++] = val & 0xff;
|
|
|
|
}
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_CMD:
|
2005-10-30 18:24:05 +01:00
|
|
|
s->rregs[saddr] = val;
|
2007-12-01 15:51:23 +01:00
|
|
|
if (val & CMD_DMA) {
|
2007-10-06 13:28:21 +02:00
|
|
|
s->dma = 1;
|
2006-09-17 05:20:58 +02:00
|
|
|
/* Reload DMA counter. */
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_TCLO] = s->wregs[ESP_TCLO];
|
|
|
|
s->rregs[ESP_TCMID] = s->wregs[ESP_TCMID];
|
2012-08-02 15:43:39 +02:00
|
|
|
s->rregs[ESP_TCHI] = s->wregs[ESP_TCHI];
|
2007-10-06 13:28:21 +02:00
|
|
|
} else {
|
|
|
|
s->dma = 0;
|
|
|
|
}
|
2007-12-01 15:51:23 +01:00
|
|
|
switch(val & CMD_CMD) {
|
|
|
|
case CMD_NOP:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_nop(val);
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_FLUSH:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_flush(val);
|
2005-11-11 01:24:58 +01:00
|
|
|
//s->ti_size = 0;
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
|
|
s->rregs[ESP_RSEQ] = 0;
|
2008-06-25 21:59:53 +02:00
|
|
|
s->rregs[ESP_RFLAGS] = 0;
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_RESET:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_reset(val);
|
2012-07-09 12:02:28 +02:00
|
|
|
esp_soft_reset(s);
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_BUSRESET:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_bus_reset(val);
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_RST;
|
|
|
|
if (!(s->wregs[ESP_CFG1] & CFG1_RESREPT)) {
|
2008-04-24 19:20:25 +02:00
|
|
|
esp_raise_irq(s);
|
2005-11-11 01:24:58 +01:00
|
|
|
}
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_TI:
|
2007-10-06 13:28:21 +02:00
|
|
|
handle_ti(s);
|
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_ICCS:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_iccs(val);
|
2007-10-06 13:28:21 +02:00
|
|
|
write_response(s);
|
2008-11-30 11:24:13 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
|
|
s->rregs[ESP_RSTAT] |= STAT_MI;
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_MSGACC:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_msgacc(val);
|
2007-12-01 15:51:23 +01:00
|
|
|
s->rregs[ESP_RINTR] = INTR_DC;
|
|
|
|
s->rregs[ESP_RSEQ] = 0;
|
2009-08-31 19:03:51 +02:00
|
|
|
s->rregs[ESP_RFLAGS] = 0;
|
|
|
|
esp_raise_irq(s);
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2009-08-22 15:55:05 +02:00
|
|
|
case CMD_PAD:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_pad(val);
|
2009-08-22 15:55:05 +02:00
|
|
|
s->rregs[ESP_RSTAT] = STAT_TC;
|
|
|
|
s->rregs[ESP_RINTR] = INTR_FC;
|
|
|
|
s->rregs[ESP_RSEQ] = 0;
|
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_SATN:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_satn(val);
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2012-07-09 12:02:25 +02:00
|
|
|
case CMD_RSTATN:
|
|
|
|
trace_esp_mem_writeb_cmd_rstatn(val);
|
|
|
|
break;
|
2009-08-22 15:54:31 +02:00
|
|
|
case CMD_SEL:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_sel(val);
|
2009-09-05 08:24:47 +02:00
|
|
|
handle_s_without_atn(s);
|
2009-08-22 15:54:31 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_SELATN:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_selatn(val);
|
2007-10-06 13:28:21 +02:00
|
|
|
handle_satn(s);
|
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_SELATNS:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_selatns(val);
|
2007-10-06 13:28:21 +02:00
|
|
|
handle_satn_stop(s);
|
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case CMD_ENSEL:
|
2011-09-11 17:54:18 +02:00
|
|
|
trace_esp_mem_writeb_cmd_ensel(val);
|
2008-11-29 17:51:42 +01:00
|
|
|
s->rregs[ESP_RINTR] = 0;
|
2007-08-11 09:58:41 +02:00
|
|
|
break;
|
2012-07-09 12:02:24 +02:00
|
|
|
case CMD_DISSEL:
|
|
|
|
trace_esp_mem_writeb_cmd_dissel(val);
|
|
|
|
s->rregs[ESP_RINTR] = 0;
|
|
|
|
esp_raise_irq(s);
|
|
|
|
break;
|
2007-10-06 13:28:21 +02:00
|
|
|
default:
|
2012-07-09 12:02:29 +02:00
|
|
|
trace_esp_error_unhandled_command(val);
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_WBUSID ... ESP_WSYNO:
|
2007-10-06 13:28:21 +02:00
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_CFG1:
|
2012-08-02 15:43:39 +02:00
|
|
|
case ESP_CFG2: case ESP_CFG3:
|
|
|
|
case ESP_RES3: case ESP_RES4:
|
2005-10-30 18:24:05 +01:00
|
|
|
s->rregs[saddr] = val;
|
|
|
|
break;
|
2007-12-01 15:51:23 +01:00
|
|
|
case ESP_WCCF ... ESP_WTEST:
|
2005-10-30 18:24:05 +01:00
|
|
|
break;
|
2005-03-13 10:43:36 +01:00
|
|
|
default:
|
2012-07-09 12:02:29 +02:00
|
|
|
trace_esp_error_invalid_write(val, saddr);
|
2008-11-29 17:45:28 +01:00
|
|
|
return;
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
2005-04-06 22:31:50 +02:00
|
|
|
s->wregs[saddr] = val;
|
2005-03-13 10:43:36 +01:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static bool esp_mem_accepts(void *opaque, hwaddr addr,
|
2011-11-13 12:07:04 +01:00
|
|
|
unsigned size, bool is_write)
|
|
|
|
{
|
|
|
|
return (size == 1) || (is_write && size == 4);
|
|
|
|
}
|
2005-03-13 10:43:36 +01:00
|
|
|
|
2012-08-04 21:10:03 +02:00
|
|
|
const VMStateDescription vmstate_esp = {
|
2009-09-19 17:44:50 +02:00
|
|
|
.name ="esp",
|
|
|
|
.version_id = 3,
|
|
|
|
.minimum_version_id = 3,
|
2014-04-16 16:01:33 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2009-09-19 17:44:50 +02:00
|
|
|
VMSTATE_BUFFER(rregs, ESPState),
|
|
|
|
VMSTATE_BUFFER(wregs, ESPState),
|
|
|
|
VMSTATE_INT32(ti_size, ESPState),
|
|
|
|
VMSTATE_UINT32(ti_rptr, ESPState),
|
|
|
|
VMSTATE_UINT32(ti_wptr, ESPState),
|
|
|
|
VMSTATE_BUFFER(ti_buf, ESPState),
|
2011-05-20 20:10:02 +02:00
|
|
|
VMSTATE_UINT32(status, ESPState),
|
2009-09-19 17:44:50 +02:00
|
|
|
VMSTATE_UINT32(dma, ESPState),
|
|
|
|
VMSTATE_BUFFER(cmdbuf, ESPState),
|
|
|
|
VMSTATE_UINT32(cmdlen, ESPState),
|
|
|
|
VMSTATE_UINT32(do_cmd, ESPState),
|
|
|
|
VMSTATE_UINT32(dma_left, ESPState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2005-03-13 10:43:36 +01:00
|
|
|
|
2013-07-01 12:18:34 +02:00
|
|
|
#define TYPE_ESP "esp"
|
|
|
|
#define ESP(obj) OBJECT_CHECK(SysBusESPState, (obj), TYPE_ESP)
|
|
|
|
|
2012-07-09 12:02:28 +02:00
|
|
|
typedef struct {
|
2013-07-01 12:18:34 +02:00
|
|
|
/*< private >*/
|
|
|
|
SysBusDevice parent_obj;
|
|
|
|
/*< public >*/
|
|
|
|
|
2012-07-09 12:02:28 +02:00
|
|
|
MemoryRegion iomem;
|
|
|
|
uint32_t it_shift;
|
|
|
|
ESPState esp;
|
|
|
|
} SysBusESPState;
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void sysbus_esp_mem_write(void *opaque, hwaddr addr,
|
2012-07-09 12:02:28 +02:00
|
|
|
uint64_t val, unsigned int size)
|
|
|
|
{
|
|
|
|
SysBusESPState *sysbus = opaque;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = addr >> sysbus->it_shift;
|
|
|
|
esp_reg_write(&sysbus->esp, saddr, val);
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t sysbus_esp_mem_read(void *opaque, hwaddr addr,
|
2012-07-09 12:02:28 +02:00
|
|
|
unsigned int size)
|
|
|
|
{
|
|
|
|
SysBusESPState *sysbus = opaque;
|
|
|
|
uint32_t saddr;
|
|
|
|
|
|
|
|
saddr = addr >> sysbus->it_shift;
|
|
|
|
return esp_reg_read(&sysbus->esp, saddr);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps sysbus_esp_mem_ops = {
|
|
|
|
.read = sysbus_esp_mem_read,
|
|
|
|
.write = sysbus_esp_mem_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid.accepts = esp_mem_accepts,
|
|
|
|
};
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
void esp_init(hwaddr espaddr, int it_shift,
|
2010-02-07 10:17:35 +01:00
|
|
|
ESPDMAMemoryReadWriteFunc dma_memory_read,
|
|
|
|
ESPDMAMemoryReadWriteFunc dma_memory_write,
|
2010-09-11 18:38:33 +02:00
|
|
|
void *dma_opaque, qemu_irq irq, qemu_irq *reset,
|
|
|
|
qemu_irq *dma_enable)
|
2005-03-13 10:43:36 +01:00
|
|
|
{
|
2009-05-14 23:35:07 +02:00
|
|
|
DeviceState *dev;
|
|
|
|
SysBusDevice *s;
|
2012-07-09 12:02:28 +02:00
|
|
|
SysBusESPState *sysbus;
|
2009-07-15 13:43:31 +02:00
|
|
|
ESPState *esp;
|
2009-05-14 23:35:07 +02:00
|
|
|
|
2013-07-01 12:18:34 +02:00
|
|
|
dev = qdev_create(NULL, TYPE_ESP);
|
|
|
|
sysbus = ESP(dev);
|
2012-07-09 12:02:28 +02:00
|
|
|
esp = &sysbus->esp;
|
2009-07-15 13:43:31 +02:00
|
|
|
esp->dma_memory_read = dma_memory_read;
|
|
|
|
esp->dma_memory_write = dma_memory_write;
|
|
|
|
esp->dma_opaque = dma_opaque;
|
2012-07-09 12:02:28 +02:00
|
|
|
sysbus->it_shift = it_shift;
|
2010-09-11 18:38:33 +02:00
|
|
|
/* XXX for now until rc4030 has been changed to use DMA enable signal */
|
|
|
|
esp->dma_enabled = 1;
|
2009-10-07 01:15:58 +02:00
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
s = SYS_BUS_DEVICE(dev);
|
2009-05-14 23:35:07 +02:00
|
|
|
sysbus_connect_irq(s, 0, irq);
|
|
|
|
sysbus_mmio_map(s, 0, espaddr);
|
2009-08-08 23:43:12 +02:00
|
|
|
*reset = qdev_get_gpio_in(dev, 0);
|
2010-09-11 18:38:33 +02:00
|
|
|
*dma_enable = qdev_get_gpio_in(dev, 1);
|
2009-05-14 23:35:07 +02:00
|
|
|
}
|
2005-03-13 10:43:36 +01:00
|
|
|
|
2011-08-13 15:44:45 +02:00
|
|
|
static const struct SCSIBusInfo esp_scsi_info = {
|
|
|
|
.tcq = false,
|
2011-08-13 18:55:17 +02:00
|
|
|
.max_target = ESP_MAX_DEVS,
|
|
|
|
.max_lun = 7,
|
2011-08-13 15:44:45 +02:00
|
|
|
|
2011-04-22 12:27:30 +02:00
|
|
|
.transfer_data = esp_transfer_data,
|
2011-04-18 22:53:08 +02:00
|
|
|
.complete = esp_command_complete,
|
|
|
|
.cancel = esp_request_cancelled
|
2011-04-18 17:11:14 +02:00
|
|
|
};
|
|
|
|
|
2012-07-09 12:02:28 +02:00
|
|
|
static void sysbus_esp_gpio_demux(void *opaque, int irq, int level)
|
2009-05-14 23:35:07 +02:00
|
|
|
{
|
2013-07-01 12:18:34 +02:00
|
|
|
SysBusESPState *sysbus = ESP(opaque);
|
2012-07-09 12:02:28 +02:00
|
|
|
ESPState *s = &sysbus->esp;
|
|
|
|
|
|
|
|
switch (irq) {
|
|
|
|
case 0:
|
|
|
|
parent_esp_reset(s, irq, level);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
esp_dma_enable(opaque, irq, level);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-01 12:18:35 +02:00
|
|
|
static void sysbus_esp_realize(DeviceState *dev, Error **errp)
|
2012-07-09 12:02:28 +02:00
|
|
|
{
|
2013-07-01 12:18:35 +02:00
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
2013-07-01 12:18:34 +02:00
|
|
|
SysBusESPState *sysbus = ESP(dev);
|
2012-07-09 12:02:28 +02:00
|
|
|
ESPState *s = &sysbus->esp;
|
2013-07-21 12:16:34 +02:00
|
|
|
Error *err = NULL;
|
2005-03-13 10:43:36 +01:00
|
|
|
|
2013-07-01 12:18:35 +02:00
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2012-07-09 12:02:28 +02:00
|
|
|
assert(sysbus->it_shift != -1);
|
2005-03-13 10:43:36 +01:00
|
|
|
|
2012-07-09 12:02:26 +02:00
|
|
|
s->chip_id = TCHI_FAS100A;
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&sysbus->iomem, OBJECT(sysbus), &sysbus_esp_mem_ops,
|
|
|
|
sysbus, "esp", ESP_REGS << sysbus->it_shift);
|
2013-07-01 12:18:35 +02:00
|
|
|
sysbus_init_mmio(sbd, &sysbus->iomem);
|
2005-03-13 10:43:36 +01:00
|
|
|
|
2013-07-01 12:18:35 +02:00
|
|
|
qdev_init_gpio_in(dev, sysbus_esp_gpio_demux, 2);
|
2007-08-16 21:56:27 +02:00
|
|
|
|
2013-08-23 20:30:03 +02:00
|
|
|
scsi_bus_new(&s->bus, sizeof(s->bus), dev, &esp_scsi_info, NULL);
|
2013-07-21 12:16:34 +02:00
|
|
|
scsi_bus_legacy_handle_cmdline(&s->bus, &err);
|
|
|
|
if (err != NULL) {
|
|
|
|
error_propagate(errp, err);
|
2013-07-01 12:18:35 +02:00
|
|
|
return;
|
|
|
|
}
|
2006-09-03 18:09:07 +02:00
|
|
|
}
|
2009-05-14 23:35:07 +02:00
|
|
|
|
2012-07-09 12:02:28 +02:00
|
|
|
static void sysbus_esp_hard_reset(DeviceState *dev)
|
|
|
|
{
|
2013-07-01 12:18:34 +02:00
|
|
|
SysBusESPState *sysbus = ESP(dev);
|
2012-07-09 12:02:28 +02:00
|
|
|
esp_hard_reset(&sysbus->esp);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_sysbus_esp_scsi = {
|
|
|
|
.name = "sysbusespscsi",
|
|
|
|
.version_id = 0,
|
|
|
|
.minimum_version_id = 0,
|
|
|
|
.fields = (VMStateField[]) {
|
|
|
|
VMSTATE_STRUCT(esp, SysBusESPState, 0, vmstate_esp, ESPState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
2012-01-24 20:12:29 +01:00
|
|
|
};
|
|
|
|
|
2012-07-09 12:02:28 +02:00
|
|
|
static void sysbus_esp_class_init(ObjectClass *klass, void *data)
|
2012-01-24 20:12:29 +01:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
2013-07-01 12:18:35 +02:00
|
|
|
dc->realize = sysbus_esp_realize;
|
2012-07-09 12:02:28 +02:00
|
|
|
dc->reset = sysbus_esp_hard_reset;
|
|
|
|
dc->vmsd = &vmstate_sysbus_esp_scsi;
|
2013-07-29 16:17:45 +02:00
|
|
|
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2012-08-02 10:40:30 +02:00
|
|
|
static const TypeInfo sysbus_esp_info = {
|
2013-07-01 12:18:34 +02:00
|
|
|
.name = TYPE_ESP,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
2012-07-09 12:02:28 +02:00
|
|
|
.instance_size = sizeof(SysBusESPState),
|
|
|
|
.class_init = sysbus_esp_class_init,
|
2009-10-24 18:34:21 +02:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void esp_register_types(void)
|
2009-05-14 23:35:07 +02:00
|
|
|
{
|
2012-07-09 12:02:28 +02:00
|
|
|
type_register_static(&sysbus_esp_info);
|
2009-05-14 23:35:07 +02:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(esp_register_types)
|