2009-01-07 13:19:50 +01:00
|
|
|
/*
|
|
|
|
* QEMU model for the AXIS devboard 88.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
|
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*
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|
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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|
*
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|
* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
|
2009-05-16 01:40:46 +02:00
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|
|
2016-01-26 19:17:24 +01:00
|
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|
#include "qemu/osdep.h"
|
include/qemu/osdep.h: Don't include qapi/error.h
Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the
Error typedef. Since then, we've moved to include qemu/osdep.h
everywhere. Its file comment explains: "To avoid getting into
possible circular include dependencies, this file should not include
any other QEMU headers, with the exceptions of config-host.h,
compiler.h, os-posix.h and os-win32.h, all of which are doing a
similar job to this file and are under similar constraints."
qapi/error.h doesn't do a similar job, and it doesn't adhere to
similar constraints: it includes qapi-types.h. That's in excess of
100KiB of crap most .c files don't actually need.
Add the typedef to qemu/typedefs.h, and include that instead of
qapi/error.h. Include qapi/error.h in .c files that need it and don't
get it now. Include qapi-types.h in qom/object.h for uint16List.
Update scripts/clean-includes accordingly. Update it further to match
reality: replace config.h by config-target.h, add sysemu/os-posix.h,
sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h
comment quoted above similarly.
This reduces the number of objects depending on qapi/error.h from "all
of them" to less than a third. Unfortunately, the number depending on
qapi-types.h shrinks only a little. More work is needed for that one.
Signed-off-by: Markus Armbruster <armbru@redhat.com>
[Fix compilation without the spice devel packages. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-14 09:01:28 +01:00
|
|
|
#include "qapi/error.h"
|
2016-01-19 21:51:44 +01:00
|
|
|
#include "qemu-common.h"
|
|
|
|
#include "cpu.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/sysbus.h"
|
2012-10-24 08:43:34 +02:00
|
|
|
#include "net/net.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/block/flash.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/boards.h"
|
2013-02-05 17:06:20 +01:00
|
|
|
#include "hw/cris/etraxfs.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/loader.h"
|
2009-09-20 16:58:02 +02:00
|
|
|
#include "elf.h"
|
2013-03-18 17:36:02 +01:00
|
|
|
#include "boot.h"
|
2014-10-07 13:59:13 +02:00
|
|
|
#include "sysemu/block-backend.h"
|
2012-12-17 18:19:49 +01:00
|
|
|
#include "exec/address-spaces.h"
|
2013-07-29 18:40:20 +02:00
|
|
|
#include "sysemu/qtest.h"
|
2016-05-25 08:39:01 +02:00
|
|
|
#include "sysemu/sysemu.h"
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
#define D(x)
|
|
|
|
#define DNAND(x)
|
|
|
|
|
|
|
|
struct nand_state_t
|
|
|
|
{
|
2011-07-29 17:35:24 +02:00
|
|
|
DeviceState *nand;
|
2011-11-14 10:17:21 +01:00
|
|
|
MemoryRegion iomem;
|
2009-01-07 13:19:50 +01:00
|
|
|
unsigned int rdy:1;
|
|
|
|
unsigned int ale:1;
|
|
|
|
unsigned int cle:1;
|
|
|
|
unsigned int ce:1;
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct nand_state_t nand_state;
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t nand_read(void *opaque, hwaddr addr, unsigned size)
|
2009-01-07 13:19:50 +01:00
|
|
|
{
|
|
|
|
struct nand_state_t *s = opaque;
|
|
|
|
uint32_t r;
|
|
|
|
int rdy;
|
|
|
|
|
|
|
|
r = nand_getio(s->nand);
|
|
|
|
nand_getpins(s->nand, &rdy);
|
|
|
|
s->rdy = rdy;
|
|
|
|
|
|
|
|
DNAND(printf("%s addr=%x r=%x\n", __func__, addr, r));
|
|
|
|
return r;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2012-10-23 12:30:10 +02:00
|
|
|
nand_write(void *opaque, hwaddr addr, uint64_t value,
|
2011-11-14 10:17:21 +01:00
|
|
|
unsigned size)
|
2009-01-07 13:19:50 +01:00
|
|
|
{
|
|
|
|
struct nand_state_t *s = opaque;
|
|
|
|
int rdy;
|
|
|
|
|
2011-11-14 10:17:21 +01:00
|
|
|
DNAND(printf("%s addr=%x v=%x\n", __func__, addr, (unsigned)value));
|
2009-01-07 13:19:50 +01:00
|
|
|
nand_setpins(s->nand, s->cle, s->ale, s->ce, 1, 0);
|
|
|
|
nand_setio(s->nand, value);
|
|
|
|
nand_getpins(s->nand, &rdy);
|
|
|
|
s->rdy = rdy;
|
|
|
|
}
|
|
|
|
|
2011-11-14 10:17:21 +01:00
|
|
|
static const MemoryRegionOps nand_ops = {
|
|
|
|
.read = nand_read,
|
|
|
|
.write = nand_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2009-01-07 13:19:50 +01:00
|
|
|
};
|
|
|
|
|
2009-01-07 14:05:58 +01:00
|
|
|
struct tempsensor_t
|
|
|
|
{
|
|
|
|
unsigned int shiftreg;
|
|
|
|
unsigned int count;
|
|
|
|
enum {
|
|
|
|
ST_OUT, ST_IN, ST_Z
|
|
|
|
} state;
|
|
|
|
|
|
|
|
uint16_t regs[3];
|
|
|
|
};
|
|
|
|
|
|
|
|
static void tempsensor_clkedge(struct tempsensor_t *s,
|
|
|
|
unsigned int clk, unsigned int data_in)
|
|
|
|
{
|
|
|
|
D(printf("%s clk=%d state=%d sr=%x\n", __func__,
|
|
|
|
clk, s->state, s->shiftreg));
|
|
|
|
if (s->count == 0) {
|
|
|
|
s->count = 16;
|
|
|
|
s->state = ST_OUT;
|
|
|
|
}
|
|
|
|
switch (s->state) {
|
|
|
|
case ST_OUT:
|
|
|
|
/* Output reg is clocked at negedge. */
|
|
|
|
if (!clk) {
|
|
|
|
s->count--;
|
|
|
|
s->shiftreg <<= 1;
|
|
|
|
if (s->count == 0) {
|
|
|
|
s->shiftreg = 0;
|
|
|
|
s->state = ST_IN;
|
|
|
|
s->count = 16;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ST_Z:
|
|
|
|
if (clk) {
|
|
|
|
s->count--;
|
|
|
|
if (s->count == 0) {
|
|
|
|
s->shiftreg = 0;
|
|
|
|
s->state = ST_OUT;
|
|
|
|
s->count = 16;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ST_IN:
|
|
|
|
/* Indata is sampled at posedge. */
|
|
|
|
if (clk) {
|
|
|
|
s->count--;
|
|
|
|
s->shiftreg <<= 1;
|
|
|
|
s->shiftreg |= data_in & 1;
|
|
|
|
if (s->count == 0) {
|
|
|
|
D(printf("%s cfgreg=%x\n", __func__, s->shiftreg));
|
|
|
|
s->regs[0] = s->shiftreg;
|
|
|
|
s->state = ST_OUT;
|
|
|
|
s->count = 16;
|
|
|
|
|
|
|
|
if ((s->regs[0] & 0xff) == 0) {
|
2015-09-08 23:45:14 +02:00
|
|
|
/* 25 degrees celsius. */
|
2009-01-07 14:05:58 +01:00
|
|
|
s->shiftreg = 0x0b9f;
|
|
|
|
} else if ((s->regs[0] & 0xff) == 0xff) {
|
|
|
|
/* Sensor ID, 0x8100 LM70. */
|
|
|
|
s->shiftreg = 0x8100;
|
|
|
|
} else
|
|
|
|
printf("Invalid tempsens state %x\n", s->regs[0]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
#define RW_PA_DOUT 0x00
|
|
|
|
#define R_PA_DIN 0x01
|
|
|
|
#define RW_PA_OE 0x02
|
|
|
|
#define RW_PD_DOUT 0x10
|
|
|
|
#define R_PD_DIN 0x11
|
|
|
|
#define RW_PD_OE 0x12
|
|
|
|
|
|
|
|
static struct gpio_state_t
|
2009-01-07 13:19:50 +01:00
|
|
|
{
|
2011-11-14 10:17:21 +01:00
|
|
|
MemoryRegion iomem;
|
2009-01-07 13:19:50 +01:00
|
|
|
struct nand_state_t *nand;
|
2009-01-07 14:05:58 +01:00
|
|
|
struct tempsensor_t tempsensor;
|
2009-01-07 13:19:50 +01:00
|
|
|
uint32_t regs[0x5c / 4];
|
|
|
|
} gpio_state;
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t gpio_read(void *opaque, hwaddr addr, unsigned size)
|
2009-01-07 13:19:50 +01:00
|
|
|
{
|
|
|
|
struct gpio_state_t *s = opaque;
|
|
|
|
uint32_t r = 0;
|
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
switch (addr)
|
|
|
|
{
|
|
|
|
case R_PA_DIN:
|
|
|
|
r = s->regs[RW_PA_DOUT] & s->regs[RW_PA_OE];
|
|
|
|
|
|
|
|
/* Encode pins from the nand. */
|
|
|
|
r |= s->nand->rdy << 7;
|
|
|
|
break;
|
2009-01-07 14:05:58 +01:00
|
|
|
case R_PD_DIN:
|
|
|
|
r = s->regs[RW_PD_DOUT] & s->regs[RW_PD_OE];
|
|
|
|
|
|
|
|
/* Encode temp sensor pins. */
|
|
|
|
r |= (!!(s->tempsensor.shiftreg & 0x10000)) << 4;
|
|
|
|
break;
|
|
|
|
|
2009-01-07 13:19:50 +01:00
|
|
|
default:
|
|
|
|
r = s->regs[addr];
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return r;
|
|
|
|
D(printf("%s %x=%x\n", __func__, addr, r));
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void gpio_write(void *opaque, hwaddr addr, uint64_t value,
|
2011-11-14 10:17:21 +01:00
|
|
|
unsigned size)
|
2009-01-07 13:19:50 +01:00
|
|
|
{
|
|
|
|
struct gpio_state_t *s = opaque;
|
2011-11-14 10:17:21 +01:00
|
|
|
D(printf("%s %x=%x\n", __func__, addr, (unsigned)value));
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
addr >>= 2;
|
|
|
|
switch (addr)
|
|
|
|
{
|
|
|
|
case RW_PA_DOUT:
|
|
|
|
/* Decode nand pins. */
|
|
|
|
s->nand->ale = !!(value & (1 << 6));
|
|
|
|
s->nand->cle = !!(value & (1 << 5));
|
|
|
|
s->nand->ce = !!(value & (1 << 4));
|
|
|
|
|
|
|
|
s->regs[addr] = value;
|
|
|
|
break;
|
2009-01-07 14:05:58 +01:00
|
|
|
|
|
|
|
case RW_PD_DOUT:
|
|
|
|
/* Temp sensor clk. */
|
|
|
|
if ((s->regs[addr] ^ value) & 2)
|
|
|
|
tempsensor_clkedge(&s->tempsensor, !!(value & 2),
|
|
|
|
!!(value & 16));
|
|
|
|
s->regs[addr] = value;
|
|
|
|
break;
|
|
|
|
|
2009-01-07 13:19:50 +01:00
|
|
|
default:
|
|
|
|
s->regs[addr] = value;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-11-14 10:17:21 +01:00
|
|
|
static const MemoryRegionOps gpio_ops = {
|
|
|
|
.read = gpio_read,
|
|
|
|
.write = gpio_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
.valid = {
|
|
|
|
.min_access_size = 4,
|
|
|
|
.max_access_size = 4,
|
|
|
|
},
|
2009-01-07 13:19:50 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
#define INTMEM_SIZE (128 * 1024)
|
|
|
|
|
2010-06-10 14:45:46 +02:00
|
|
|
static struct cris_load_info li;
|
2010-03-14 21:20:59 +01:00
|
|
|
|
2009-01-07 13:19:50 +01:00
|
|
|
static
|
2014-05-07 16:42:57 +02:00
|
|
|
void axisdev88_init(MachineState *machine)
|
2009-01-07 13:19:50 +01:00
|
|
|
{
|
2014-05-07 16:42:57 +02:00
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
|
|
const char *cpu_model = machine->cpu_model;
|
|
|
|
const char *kernel_filename = machine->kernel_filename;
|
|
|
|
const char *kernel_cmdline = machine->kernel_cmdline;
|
2012-05-05 11:50:35 +02:00
|
|
|
CRISCPU *cpu;
|
2012-03-14 01:38:23 +01:00
|
|
|
CPUCRISState *env;
|
2009-05-18 22:24:22 +02:00
|
|
|
DeviceState *dev;
|
|
|
|
SysBusDevice *s;
|
2011-07-29 17:35:19 +02:00
|
|
|
DriveInfo *nand;
|
2014-01-21 13:45:54 +01:00
|
|
|
qemu_irq irq[30], nmi[2];
|
2009-01-07 13:19:50 +01:00
|
|
|
void *etraxfs_dmac;
|
2011-08-09 12:13:26 +02:00
|
|
|
struct etraxfs_dma_client *dma_eth;
|
2009-01-07 13:19:50 +01:00
|
|
|
int i;
|
2011-07-25 13:32:34 +02:00
|
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
|
|
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
/* init CPUs */
|
|
|
|
if (cpu_model == NULL) {
|
|
|
|
cpu_model = "crisv32";
|
|
|
|
}
|
2017-08-24 18:31:42 +02:00
|
|
|
cpu = CRIS_CPU(cpu_generic_init(TYPE_CRIS_CPU, cpu_model));
|
2012-05-05 11:50:35 +02:00
|
|
|
env = &cpu->env;
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
/* allocate RAM */
|
2015-04-04 14:15:10 +02:00
|
|
|
memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram",
|
|
|
|
ram_size);
|
2011-07-25 13:32:34 +02:00
|
|
|
memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
|
|
|
|
internal memory. */
|
2017-07-07 16:42:53 +02:00
|
|
|
memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram",
|
|
|
|
INTMEM_SIZE, &error_fatal);
|
2011-07-25 13:32:34 +02:00
|
|
|
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
/* Attach a NAND flash to CS1. */
|
2011-07-29 17:35:19 +02:00
|
|
|
nand = drive_get(IF_MTD, 0, 0);
|
2014-10-07 13:59:18 +02:00
|
|
|
nand_state.nand = nand_init(nand ? blk_by_legacy_dinfo(nand) : NULL,
|
2011-07-29 17:35:19 +02:00
|
|
|
NAND_MFR_STMICRO, 0x39);
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&nand_state.iomem, NULL, &nand_ops, &nand_state,
|
2011-11-14 10:17:21 +01:00
|
|
|
"nand", 0x05000000);
|
|
|
|
memory_region_add_subregion(address_space_mem, 0x10000000,
|
|
|
|
&nand_state.iomem);
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
gpio_state.nand = &nand_state;
|
2013-06-06 11:41:28 +02:00
|
|
|
memory_region_init_io(&gpio_state.iomem, NULL, &gpio_ops, &gpio_state,
|
2011-11-14 10:17:21 +01:00
|
|
|
"gpio", 0x5c);
|
|
|
|
memory_region_add_subregion(address_space_mem, 0x3001a000,
|
|
|
|
&gpio_state.iomem);
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
|
2009-05-18 22:24:22 +02:00
|
|
|
dev = qdev_create(NULL, "etraxfs,pic");
|
|
|
|
/* FIXME: Is there a proper way to signal vectors to the CPU core? */
|
2009-07-15 13:43:31 +02:00
|
|
|
qdev_prop_set_ptr(dev, "interrupt_vector", &env->interrupt_vector);
|
2009-10-07 01:15:58 +02:00
|
|
|
qdev_init_nofail(dev);
|
2013-01-20 02:47:33 +01:00
|
|
|
s = SYS_BUS_DEVICE(dev);
|
2009-05-18 22:24:22 +02:00
|
|
|
sysbus_mmio_map(s, 0, 0x3001c000);
|
2014-01-21 13:45:54 +01:00
|
|
|
sysbus_connect_irq(s, 0, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_IRQ));
|
|
|
|
sysbus_connect_irq(s, 1, qdev_get_gpio_in(DEVICE(cpu), CRIS_CPU_NMI));
|
2009-05-18 22:24:22 +02:00
|
|
|
for (i = 0; i < 30; i++) {
|
2009-05-26 15:56:11 +02:00
|
|
|
irq[i] = qdev_get_gpio_in(dev, i);
|
2009-05-18 22:24:22 +02:00
|
|
|
}
|
2009-05-26 15:56:11 +02:00
|
|
|
nmi[0] = qdev_get_gpio_in(dev, 30);
|
|
|
|
nmi[1] = qdev_get_gpio_in(dev, 31);
|
2009-05-16 00:23:15 +02:00
|
|
|
|
2009-06-15 21:00:50 +02:00
|
|
|
etraxfs_dmac = etraxfs_dmac_init(0x30000000, 10);
|
2009-01-07 13:19:50 +01:00
|
|
|
for (i = 0; i < 10; i++) {
|
|
|
|
/* On ETRAX, odd numbered channels are inputs. */
|
2009-05-16 00:23:15 +02:00
|
|
|
etraxfs_dmac_connect(etraxfs_dmac, i, irq + 7 + i, i & 1);
|
2009-01-07 13:19:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Add the two ethernet blocks. */
|
2011-08-21 05:09:37 +02:00
|
|
|
dma_eth = g_malloc0(sizeof dma_eth[0] * 4); /* Allocate 4 channels. */
|
2011-08-09 12:13:26 +02:00
|
|
|
etraxfs_eth_init(&nd_table[0], 0x30034000, 1, &dma_eth[0], &dma_eth[1]);
|
|
|
|
if (nb_nics > 1) {
|
|
|
|
etraxfs_eth_init(&nd_table[1], 0x30036000, 2, &dma_eth[2], &dma_eth[3]);
|
|
|
|
}
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
/* The DMA Connector block is missing, hardwire things for now. */
|
2011-08-09 12:13:26 +02:00
|
|
|
etraxfs_dmac_connect_client(etraxfs_dmac, 0, &dma_eth[0]);
|
|
|
|
etraxfs_dmac_connect_client(etraxfs_dmac, 1, &dma_eth[1]);
|
|
|
|
if (nb_nics > 1) {
|
|
|
|
etraxfs_dmac_connect_client(etraxfs_dmac, 6, &dma_eth[2]);
|
|
|
|
etraxfs_dmac_connect_client(etraxfs_dmac, 7, &dma_eth[3]);
|
2009-01-07 13:19:50 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* 2 timers. */
|
2009-05-16 02:08:16 +02:00
|
|
|
sysbus_create_varargs("etraxfs,timer", 0x3001e000, irq[0x1b], nmi[1], NULL);
|
|
|
|
sysbus_create_varargs("etraxfs,timer", 0x3005e000, irq[0x1b], nmi[1], NULL);
|
2009-01-07 13:19:50 +01:00
|
|
|
|
|
|
|
for (i = 0; i < 4; i++) {
|
2016-05-25 08:39:01 +02:00
|
|
|
etraxfs_ser_create(0x30026000 + i * 0x2000, irq[0x14 + i], serial_hds[i]);
|
2009-01-07 13:19:50 +01:00
|
|
|
}
|
|
|
|
|
2013-07-29 18:40:20 +02:00
|
|
|
if (kernel_filename) {
|
|
|
|
li.image_filename = kernel_filename;
|
|
|
|
li.cmdline = kernel_cmdline;
|
|
|
|
cris_load_image(cpu, &li);
|
|
|
|
} else if (!qtest_enabled()) {
|
2010-06-10 14:45:46 +02:00
|
|
|
fprintf(stderr, "Kernel image must be specified\n");
|
|
|
|
exit(1);
|
2009-01-07 13:19:50 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
static void axisdev88_machine_init(MachineClass *mc)
|
2009-05-21 01:38:09 +02:00
|
|
|
{
|
2015-09-04 20:37:08 +02:00
|
|
|
mc->desc = "AXIS devboard 88";
|
|
|
|
mc->init = axisdev88_init;
|
|
|
|
mc->is_default = 1;
|
2009-05-21 01:38:09 +02:00
|
|
|
}
|
|
|
|
|
2015-09-04 20:37:08 +02:00
|
|
|
DEFINE_MACHINE("axis-dev88", axisdev88_machine_init)
|