2021-05-05 18:06:03 +02:00
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/*
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2022-04-23 04:34:58 +02:00
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* RISC-V translation routines for the Zb[abcs] and Zbk[bcx] Standard Extension.
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2021-05-05 18:06:03 +02:00
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*
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* Copyright (c) 2020 Kito Cheng, kito.cheng@sifive.com
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* Copyright (c) 2020 Frank Chang, frank.chang@sifive.com
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2021-09-11 16:00:05 +02:00
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* Copyright (c) 2021 Philipp Tomsich, philipp.tomsich@vrull.eu
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2021-05-05 18:06:03 +02:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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2021-09-11 16:00:05 +02:00
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#define REQUIRE_ZBA(ctx) do { \
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2022-02-03 16:39:45 +01:00
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if (!ctx->cfg_ptr->ext_zba) { \
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2021-09-11 16:00:05 +02:00
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return false; \
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} \
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} while (0)
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2021-08-23 21:55:15 +02:00
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2021-09-11 16:00:10 +02:00
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#define REQUIRE_ZBB(ctx) do { \
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2022-02-03 16:39:45 +01:00
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if (!ctx->cfg_ptr->ext_zbb) { \
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2021-09-11 16:00:10 +02:00
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return false; \
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} \
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} while (0)
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2021-09-11 16:00:09 +02:00
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#define REQUIRE_ZBC(ctx) do { \
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2022-02-03 16:39:45 +01:00
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if (!ctx->cfg_ptr->ext_zbc) { \
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2021-09-11 16:00:09 +02:00
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return false; \
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} \
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} while (0)
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2021-09-11 16:00:08 +02:00
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#define REQUIRE_ZBS(ctx) do { \
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2022-02-03 16:39:45 +01:00
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if (!ctx->cfg_ptr->ext_zbs) { \
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2021-09-11 16:00:08 +02:00
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return false; \
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} \
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} while (0)
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2022-04-23 04:34:58 +02:00
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#define REQUIRE_ZBKB(ctx) do { \
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if (!ctx->cfg_ptr->ext_zbkb) { \
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return false; \
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} \
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} while (0)
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2022-04-23 04:35:00 +02:00
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#define REQUIRE_ZBKX(ctx) do { \
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if (!ctx->cfg_ptr->ext_zbkx) { \
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return false; \
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} \
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} while (0)
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2021-08-23 21:55:15 +02:00
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static void gen_clz(TCGv ret, TCGv arg1)
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{
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tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
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}
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2021-09-11 16:00:10 +02:00
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2021-10-20 05:17:06 +02:00
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static void gen_clzw(TCGv ret, TCGv arg1)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shli_tl(t, arg1, 32);
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tcg_gen_clzi_tl(ret, t, 32);
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tcg_temp_free(t);
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}
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2021-05-05 18:06:03 +02:00
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static bool trans_clz(DisasContext *ctx, arg_clz *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2021-10-20 05:17:06 +02:00
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return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
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2021-05-05 18:06:03 +02:00
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}
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2021-08-23 21:55:15 +02:00
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static void gen_ctz(TCGv ret, TCGv arg1)
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{
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tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
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}
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2021-10-20 05:17:06 +02:00
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static void gen_ctzw(TCGv ret, TCGv arg1)
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{
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tcg_gen_ctzi_tl(ret, arg1, 32);
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}
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2021-05-05 18:06:03 +02:00
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static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2021-10-20 05:17:06 +02:00
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return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
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2021-05-05 18:06:03 +02:00
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}
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2021-05-05 18:06:04 +02:00
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static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2021-08-23 21:55:16 +02:00
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return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
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2021-05-05 18:06:04 +02:00
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}
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2021-05-05 18:06:05 +02:00
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static bool trans_andn(DisasContext *ctx, arg_andn *a)
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{
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2022-04-23 04:34:58 +02:00
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REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
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2022-01-06 22:00:55 +01:00
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return gen_logic(ctx, a, tcg_gen_andc_tl);
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2021-05-05 18:06:05 +02:00
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}
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static bool trans_orn(DisasContext *ctx, arg_orn *a)
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{
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2022-04-23 04:34:58 +02:00
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REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
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2022-01-06 22:00:55 +01:00
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return gen_logic(ctx, a, tcg_gen_orc_tl);
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2021-05-05 18:06:05 +02:00
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}
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static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
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{
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2022-04-23 04:34:58 +02:00
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REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
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2022-01-06 22:00:55 +01:00
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return gen_logic(ctx, a, tcg_gen_eqv_tl);
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2021-05-05 18:06:05 +02:00
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}
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2021-05-05 18:06:07 +02:00
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static bool trans_min(DisasContext *ctx, arg_min *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2022-01-06 22:01:03 +01:00
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smin_tl, NULL);
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2021-05-05 18:06:07 +02:00
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}
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static bool trans_max(DisasContext *ctx, arg_max *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2022-01-06 22:01:03 +01:00
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_smax_tl, NULL);
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2021-05-05 18:06:07 +02:00
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}
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static bool trans_minu(DisasContext *ctx, arg_minu *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2022-01-06 22:01:03 +01:00
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umin_tl, NULL);
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2021-05-05 18:06:07 +02:00
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}
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static bool trans_maxu(DisasContext *ctx, arg_maxu *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2022-01-06 22:01:03 +01:00
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return gen_arith(ctx, a, EXT_SIGN, tcg_gen_umax_tl, NULL);
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2021-05-05 18:06:07 +02:00
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}
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2021-05-05 18:06:08 +02:00
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static bool trans_sext_b(DisasContext *ctx, arg_sext_b *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2021-08-23 21:55:16 +02:00
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl);
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2021-05-05 18:06:08 +02:00
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}
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static bool trans_sext_h(DisasContext *ctx, arg_sext_h *a)
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{
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2021-09-11 16:00:10 +02:00
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REQUIRE_ZBB(ctx);
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2021-08-23 21:55:16 +02:00
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl);
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2021-05-05 18:06:08 +02:00
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}
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2021-08-23 21:55:15 +02:00
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static void gen_sbop_mask(TCGv ret, TCGv shamt)
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{
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tcg_gen_movi_tl(ret, 1);
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tcg_gen_shl_tl(ret, ret, shamt);
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}
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static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt)
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{
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TCGv t = tcg_temp_new();
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gen_sbop_mask(t, shamt);
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tcg_gen_or_tl(ret, arg1, t);
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tcg_temp_free(t);
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}
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2021-05-05 18:06:10 +02:00
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static bool trans_bset(DisasContext *ctx, arg_bset *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2022-01-06 22:01:02 +01:00
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return gen_shift(ctx, a, EXT_NONE, gen_bset, NULL);
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2021-05-05 18:06:10 +02:00
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}
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static bool trans_bseti(DisasContext *ctx, arg_bseti *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2021-08-23 21:55:17 +02:00
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bset);
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2021-05-05 18:06:10 +02:00
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}
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2021-08-23 21:55:15 +02:00
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static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt)
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{
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TCGv t = tcg_temp_new();
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gen_sbop_mask(t, shamt);
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tcg_gen_andc_tl(ret, arg1, t);
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tcg_temp_free(t);
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}
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2021-05-05 18:06:10 +02:00
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static bool trans_bclr(DisasContext *ctx, arg_bclr *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2022-01-06 22:01:02 +01:00
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return gen_shift(ctx, a, EXT_NONE, gen_bclr, NULL);
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2021-05-05 18:06:10 +02:00
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}
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static bool trans_bclri(DisasContext *ctx, arg_bclri *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2021-08-23 21:55:17 +02:00
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bclr);
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2021-05-05 18:06:10 +02:00
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}
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2021-08-23 21:55:15 +02:00
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static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt)
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{
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TCGv t = tcg_temp_new();
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gen_sbop_mask(t, shamt);
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tcg_gen_xor_tl(ret, arg1, t);
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tcg_temp_free(t);
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}
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2021-05-05 18:06:10 +02:00
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static bool trans_binv(DisasContext *ctx, arg_binv *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2022-01-06 22:01:02 +01:00
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return gen_shift(ctx, a, EXT_NONE, gen_binv, NULL);
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2021-05-05 18:06:10 +02:00
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}
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static bool trans_binvi(DisasContext *ctx, arg_binvi *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2021-08-23 21:55:17 +02:00
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_binv);
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2021-05-05 18:06:10 +02:00
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}
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2021-08-23 21:55:15 +02:00
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static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt)
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{
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tcg_gen_shr_tl(ret, arg1, shamt);
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tcg_gen_andi_tl(ret, ret, 1);
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}
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2021-05-05 18:06:10 +02:00
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static bool trans_bext(DisasContext *ctx, arg_bext *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2022-01-06 22:01:02 +01:00
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return gen_shift(ctx, a, EXT_NONE, gen_bext, NULL);
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2021-05-05 18:06:10 +02:00
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}
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static bool trans_bexti(DisasContext *ctx, arg_bexti *a)
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{
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2021-09-11 16:00:08 +02:00
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REQUIRE_ZBS(ctx);
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2021-08-23 21:55:17 +02:00
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return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
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2021-05-05 18:06:10 +02:00
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}
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2021-10-20 05:17:07 +02:00
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static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv_i32 t1 = tcg_temp_new_i32();
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TCGv_i32 t2 = tcg_temp_new_i32();
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/* truncate to 32-bits */
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tcg_gen_trunc_tl_i32(t1, arg1);
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tcg_gen_trunc_tl_i32(t2, arg2);
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tcg_gen_rotr_i32(t1, t1, t2);
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/* sign-extend 64-bits */
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tcg_gen_ext_i32_tl(ret, t1);
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tcg_temp_free_i32(t1);
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tcg_temp_free_i32(t2);
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}
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2021-05-05 18:06:12 +02:00
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static bool trans_ror(DisasContext *ctx, arg_ror *a)
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{
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2022-04-23 04:34:58 +02:00
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REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
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2022-01-06 22:01:02 +01:00
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return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotr_tl, gen_rorw, NULL);
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2021-10-20 05:17:07 +02:00
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}
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static void gen_roriw(TCGv ret, TCGv arg1, target_long shamt)
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{
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TCGv_i32 t1 = tcg_temp_new_i32();
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tcg_gen_trunc_tl_i32(t1, arg1);
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tcg_gen_rotri_i32(t1, t1, shamt);
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tcg_gen_ext_i32_tl(ret, t1);
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tcg_temp_free_i32(t1);
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2021-05-05 18:06:12 +02:00
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}
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static bool trans_rori(DisasContext *ctx, arg_rori *a)
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{
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2022-04-23 04:34:58 +02:00
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REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
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2021-10-20 05:17:07 +02:00
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|
|
return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE,
|
2022-01-06 22:01:02 +01:00
|
|
|
tcg_gen_rotri_tl, gen_roriw, NULL);
|
2021-10-20 05:17:07 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2)
|
|
|
|
{
|
|
|
|
TCGv_i32 t1 = tcg_temp_new_i32();
|
|
|
|
TCGv_i32 t2 = tcg_temp_new_i32();
|
|
|
|
|
|
|
|
/* truncate to 32-bits */
|
|
|
|
tcg_gen_trunc_tl_i32(t1, arg1);
|
|
|
|
tcg_gen_trunc_tl_i32(t2, arg2);
|
|
|
|
|
|
|
|
tcg_gen_rotl_i32(t1, t1, t2);
|
|
|
|
|
|
|
|
/* sign-extend 64-bits */
|
|
|
|
tcg_gen_ext_i32_tl(ret, t1);
|
|
|
|
|
|
|
|
tcg_temp_free_i32(t1);
|
|
|
|
tcg_temp_free_i32(t2);
|
2021-05-05 18:06:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_rol(DisasContext *ctx, arg_rol *a)
|
|
|
|
{
|
2022-04-23 04:34:58 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
|
2022-01-06 22:01:02 +01:00
|
|
|
return gen_shift_per_ol(ctx, a, EXT_NONE, tcg_gen_rotl_tl, gen_rolw, NULL);
|
2021-05-05 18:06:12 +02:00
|
|
|
}
|
|
|
|
|
2021-10-20 05:17:05 +02:00
|
|
|
static void gen_rev8_32(TCGv ret, TCGv src1)
|
|
|
|
{
|
|
|
|
tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
|
|
|
|
}
|
|
|
|
|
2021-09-11 16:00:13 +02:00
|
|
|
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
|
2021-05-05 18:06:13 +02:00
|
|
|
{
|
2021-09-11 16:00:13 +02:00
|
|
|
REQUIRE_32BIT(ctx);
|
2022-04-23 04:34:58 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
|
2021-10-20 05:17:05 +02:00
|
|
|
return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
|
2021-08-23 21:55:15 +02:00
|
|
|
}
|
|
|
|
|
2021-09-11 16:00:13 +02:00
|
|
|
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
|
2021-05-05 18:06:13 +02:00
|
|
|
{
|
2021-09-11 16:00:13 +02:00
|
|
|
REQUIRE_64BIT(ctx);
|
2022-04-23 04:34:58 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
|
2021-09-11 16:00:13 +02:00
|
|
|
return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
|
2021-05-05 18:06:13 +02:00
|
|
|
}
|
|
|
|
|
2021-09-11 16:00:11 +02:00
|
|
|
static void gen_orc_b(TCGv ret, TCGv source1)
|
2021-05-05 18:06:14 +02:00
|
|
|
{
|
2021-09-11 16:00:11 +02:00
|
|
|
TCGv tmp = tcg_temp_new();
|
2021-10-13 20:41:25 +02:00
|
|
|
TCGv low7 = tcg_constant_tl(dup_const_tl(MO_8, 0x7f));
|
2021-09-11 16:00:11 +02:00
|
|
|
|
2021-10-13 20:41:25 +02:00
|
|
|
/* Set msb in each byte if the byte was non-zero. */
|
|
|
|
tcg_gen_and_tl(tmp, source1, low7);
|
|
|
|
tcg_gen_add_tl(tmp, tmp, low7);
|
|
|
|
tcg_gen_or_tl(tmp, tmp, source1);
|
|
|
|
|
|
|
|
/* Extract the msb to the lsb in each byte */
|
|
|
|
tcg_gen_andc_tl(tmp, tmp, low7);
|
2021-09-11 16:00:11 +02:00
|
|
|
tcg_gen_shri_tl(tmp, tmp, 7);
|
|
|
|
|
|
|
|
/* Replicate the lsb of each byte across the byte. */
|
|
|
|
tcg_gen_muli_tl(ret, tmp, 0xff);
|
|
|
|
|
|
|
|
tcg_temp_free(tmp);
|
2021-05-05 18:06:14 +02:00
|
|
|
}
|
|
|
|
|
2021-09-11 16:00:11 +02:00
|
|
|
static bool trans_orc_b(DisasContext *ctx, arg_orc_b *a)
|
2021-05-05 18:06:14 +02:00
|
|
|
{
|
2021-09-11 16:00:11 +02:00
|
|
|
REQUIRE_ZBB(ctx);
|
|
|
|
return gen_unary(ctx, a, EXT_ZERO, gen_orc_b);
|
2021-05-05 18:06:14 +02:00
|
|
|
}
|
|
|
|
|
2021-08-23 21:55:15 +02:00
|
|
|
#define GEN_SHADD(SHAMT) \
|
|
|
|
static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \
|
|
|
|
{ \
|
|
|
|
TCGv t = tcg_temp_new(); \
|
|
|
|
\
|
|
|
|
tcg_gen_shli_tl(t, arg1, SHAMT); \
|
|
|
|
tcg_gen_add_tl(ret, t, arg2); \
|
|
|
|
\
|
|
|
|
tcg_temp_free(t); \
|
|
|
|
}
|
|
|
|
|
|
|
|
GEN_SHADD(1)
|
|
|
|
GEN_SHADD(2)
|
|
|
|
GEN_SHADD(3)
|
|
|
|
|
2021-05-05 18:06:15 +02:00
|
|
|
#define GEN_TRANS_SHADD(SHAMT) \
|
|
|
|
static bool trans_sh##SHAMT##add(DisasContext *ctx, arg_sh##SHAMT##add *a) \
|
|
|
|
{ \
|
2021-09-11 16:00:05 +02:00
|
|
|
REQUIRE_ZBA(ctx); \
|
2022-01-06 22:01:03 +01:00
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add, NULL); \
|
2021-05-05 18:06:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
GEN_TRANS_SHADD(1)
|
|
|
|
GEN_TRANS_SHADD(2)
|
|
|
|
GEN_TRANS_SHADD(3)
|
|
|
|
|
2021-09-11 16:00:14 +02:00
|
|
|
static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
|
|
|
|
{
|
|
|
|
REQUIRE_32BIT(ctx);
|
|
|
|
REQUIRE_ZBB(ctx);
|
|
|
|
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
|
|
|
REQUIRE_ZBB(ctx);
|
|
|
|
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
|
|
|
|
}
|
|
|
|
|
2021-05-05 18:06:03 +02:00
|
|
|
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2021-09-11 16:00:10 +02:00
|
|
|
REQUIRE_ZBB(ctx);
|
target/riscv: clwz must ignore high bits (use shift-left & changed logic)
Assume clzw being executed on a register that is not sign-extended, such
as for the following sequence that uses (1ULL << 63) | 392 as the operand
to clzw:
bseti a2, zero, 63
addi a2, a2, 392
clzw a3, a2
The correct result of clzw would be 23, but the current implementation
returns -32 (as it performs a 64bit clz, which results in 0 leading zero
bits, and then subtracts 32).
Fix this by changing the implementation to:
1. shift the original register up by 32
2. performs a target-length (64bit) clz
3. return 32 if no bits are set
Marking this instruction as 'w-form' (i.e., setting ctx->w) would not
correctly model the behaviour, as the instruction should not perform
a zero-extensions on the input (after all, it is not a .uw instruction)
and the result is always in the range 0..32 (so neither a sign-extension
nor a zero-extension on the result will ever be needed). Consequently,
we do not set ctx->w and mark the instruction as EXT_NONE.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: LIU Zhiwei<zhiwei_liu@c-sky.com>
Message-id: 20210911140016.834071-4-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-09-11 16:00:03 +02:00
|
|
|
return gen_unary(ctx, a, EXT_NONE, gen_clzw);
|
2021-05-05 18:06:03 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2021-09-11 16:00:10 +02:00
|
|
|
REQUIRE_ZBB(ctx);
|
2021-10-20 05:17:06 +02:00
|
|
|
return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
|
2021-08-23 21:55:15 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 18:06:04 +02:00
|
|
|
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2021-09-11 16:00:10 +02:00
|
|
|
REQUIRE_ZBB(ctx);
|
2021-10-20 05:17:03 +02:00
|
|
|
ctx->ol = MXL_RV32;
|
2021-08-23 21:55:16 +02:00
|
|
|
return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
|
2021-05-05 18:06:04 +02:00
|
|
|
}
|
2021-05-05 18:06:06 +02:00
|
|
|
|
2021-05-05 18:06:12 +02:00
|
|
|
static bool trans_rorw(DisasContext *ctx, arg_rorw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2022-04-23 04:34:58 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
|
2021-10-20 05:17:03 +02:00
|
|
|
ctx->ol = MXL_RV32;
|
2022-01-06 22:01:02 +01:00
|
|
|
return gen_shift(ctx, a, EXT_NONE, gen_rorw, NULL);
|
2021-05-05 18:06:12 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_roriw(DisasContext *ctx, arg_roriw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2022-04-23 04:34:58 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
|
2021-10-20 05:17:03 +02:00
|
|
|
ctx->ol = MXL_RV32;
|
2022-01-06 22:01:02 +01:00
|
|
|
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL);
|
2021-08-23 21:55:15 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 18:06:12 +02:00
|
|
|
static bool trans_rolw(DisasContext *ctx, arg_rolw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2022-04-23 04:34:58 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbb, zbkb);
|
2021-10-20 05:17:03 +02:00
|
|
|
ctx->ol = MXL_RV32;
|
2022-01-06 22:01:02 +01:00
|
|
|
return gen_shift(ctx, a, EXT_NONE, gen_rolw, NULL);
|
2021-08-23 21:55:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
#define GEN_SHADD_UW(SHAMT) \
|
|
|
|
static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \
|
|
|
|
{ \
|
|
|
|
TCGv t = tcg_temp_new(); \
|
|
|
|
\
|
|
|
|
tcg_gen_ext32u_tl(t, arg1); \
|
|
|
|
\
|
|
|
|
tcg_gen_shli_tl(t, t, SHAMT); \
|
|
|
|
tcg_gen_add_tl(ret, t, arg2); \
|
|
|
|
\
|
|
|
|
tcg_temp_free(t); \
|
|
|
|
}
|
|
|
|
|
|
|
|
GEN_SHADD_UW(1)
|
|
|
|
GEN_SHADD_UW(2)
|
|
|
|
GEN_SHADD_UW(3)
|
|
|
|
|
2021-05-05 18:06:15 +02:00
|
|
|
#define GEN_TRANS_SHADD_UW(SHAMT) \
|
|
|
|
static bool trans_sh##SHAMT##add_uw(DisasContext *ctx, \
|
|
|
|
arg_sh##SHAMT##add_uw *a) \
|
|
|
|
{ \
|
|
|
|
REQUIRE_64BIT(ctx); \
|
2021-09-11 16:00:05 +02:00
|
|
|
REQUIRE_ZBA(ctx); \
|
2022-01-06 22:01:03 +01:00
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_sh##SHAMT##add_uw, NULL); \
|
2021-05-05 18:06:15 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
GEN_TRANS_SHADD_UW(1)
|
|
|
|
GEN_TRANS_SHADD_UW(2)
|
|
|
|
GEN_TRANS_SHADD_UW(3)
|
2021-05-05 18:06:16 +02:00
|
|
|
|
2021-08-23 21:55:15 +02:00
|
|
|
static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2)
|
|
|
|
{
|
2021-09-11 16:00:01 +02:00
|
|
|
TCGv t = tcg_temp_new();
|
|
|
|
tcg_gen_ext32u_tl(t, arg1);
|
|
|
|
tcg_gen_add_tl(ret, t, arg2);
|
|
|
|
tcg_temp_free(t);
|
2021-08-23 21:55:15 +02:00
|
|
|
}
|
|
|
|
|
2021-05-05 18:06:16 +02:00
|
|
|
static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2021-09-11 16:00:05 +02:00
|
|
|
REQUIRE_ZBA(ctx);
|
2022-01-06 22:01:03 +01:00
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_add_uw, NULL);
|
2021-05-05 18:06:16 +02:00
|
|
|
}
|
|
|
|
|
2021-08-23 21:55:25 +02:00
|
|
|
static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
|
|
|
|
{
|
|
|
|
tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
|
|
|
|
}
|
|
|
|
|
2021-05-05 18:06:16 +02:00
|
|
|
static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
2021-09-11 16:00:05 +02:00
|
|
|
REQUIRE_ZBA(ctx);
|
2022-01-06 22:01:02 +01:00
|
|
|
return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw, NULL);
|
2021-05-05 18:06:16 +02:00
|
|
|
}
|
2021-09-11 16:00:09 +02:00
|
|
|
|
|
|
|
static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
|
|
|
|
{
|
2022-04-23 04:34:59 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
|
2022-01-06 22:01:03 +01:00
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmul, NULL);
|
2021-09-11 16:00:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void gen_clmulh(TCGv dst, TCGv src1, TCGv src2)
|
|
|
|
{
|
|
|
|
gen_helper_clmulr(dst, src1, src2);
|
|
|
|
tcg_gen_shri_tl(dst, dst, 1);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
|
|
|
|
{
|
2022-04-23 04:34:59 +02:00
|
|
|
REQUIRE_EITHER_EXT(ctx, zbc, zbkc);
|
2022-01-06 22:01:03 +01:00
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_clmulh, NULL);
|
2021-09-11 16:00:09 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
|
|
|
|
{
|
|
|
|
REQUIRE_ZBC(ctx);
|
2022-01-06 22:01:03 +01:00
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_helper_clmulr, NULL);
|
2021-09-11 16:00:09 +02:00
|
|
|
}
|
2022-04-23 04:34:58 +02:00
|
|
|
|
|
|
|
static void gen_pack(TCGv ret, TCGv src1, TCGv src2)
|
|
|
|
{
|
|
|
|
tcg_gen_deposit_tl(ret, src1, src2,
|
|
|
|
TARGET_LONG_BITS / 2,
|
|
|
|
TARGET_LONG_BITS / 2);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
|
|
|
|
{
|
|
|
|
TCGv t = tcg_temp_new();
|
|
|
|
|
|
|
|
tcg_gen_ext8u_tl(t, src2);
|
|
|
|
tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
|
|
|
|
tcg_temp_free(t);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gen_packw(TCGv ret, TCGv src1, TCGv src2)
|
|
|
|
{
|
|
|
|
TCGv t = tcg_temp_new();
|
|
|
|
|
|
|
|
tcg_gen_ext16s_tl(t, src2);
|
|
|
|
tcg_gen_deposit_tl(ret, src1, t, 16, TARGET_LONG_BITS - 16);
|
|
|
|
tcg_temp_free(t);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_brev8(DisasContext *ctx, arg_brev8 *a)
|
|
|
|
{
|
|
|
|
REQUIRE_ZBKB(ctx);
|
|
|
|
return gen_unary(ctx, a, EXT_NONE, gen_helper_brev8);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_pack(DisasContext *ctx, arg_pack *a)
|
|
|
|
{
|
|
|
|
REQUIRE_ZBKB(ctx);
|
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_pack, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_packh(DisasContext *ctx, arg_packh *a)
|
|
|
|
{
|
|
|
|
REQUIRE_ZBKB(ctx);
|
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_packh, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_packw(DisasContext *ctx, arg_packw *a)
|
|
|
|
{
|
|
|
|
REQUIRE_64BIT(ctx);
|
|
|
|
REQUIRE_ZBKB(ctx);
|
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_packw, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_unzip(DisasContext *ctx, arg_unzip *a)
|
|
|
|
{
|
|
|
|
REQUIRE_32BIT(ctx);
|
|
|
|
REQUIRE_ZBKB(ctx);
|
|
|
|
return gen_unary(ctx, a, EXT_NONE, gen_helper_unzip);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_zip(DisasContext *ctx, arg_zip *a)
|
|
|
|
{
|
|
|
|
REQUIRE_32BIT(ctx);
|
|
|
|
REQUIRE_ZBKB(ctx);
|
|
|
|
return gen_unary(ctx, a, EXT_NONE, gen_helper_zip);
|
|
|
|
}
|
2022-04-23 04:35:00 +02:00
|
|
|
|
|
|
|
static bool trans_xperm4(DisasContext *ctx, arg_xperm4 *a)
|
|
|
|
{
|
|
|
|
REQUIRE_ZBKX(ctx);
|
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm4, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool trans_xperm8(DisasContext *ctx, arg_xperm8 *a)
|
|
|
|
{
|
|
|
|
REQUIRE_ZBKX(ctx);
|
|
|
|
return gen_arith(ctx, a, EXT_NONE, gen_helper_xperm8, NULL);
|
|
|
|
}
|