2007-09-16 23:08:06 +02:00
|
|
|
/*
|
2006-04-09 03:32:52 +02:00
|
|
|
* ARM PrimeCell Timer modules.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2005-2006 CodeSourcery.
|
|
|
|
* Written by Paul Brook
|
|
|
|
*
|
2011-06-26 04:21:35 +02:00
|
|
|
* This code is licensed under the GPL.
|
2006-04-09 03:32:52 +02:00
|
|
|
*/
|
|
|
|
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/sysbus.h"
|
2012-12-17 18:20:00 +01:00
|
|
|
#include "qemu/timer.h"
|
2011-12-29 07:19:51 +01:00
|
|
|
#include "qemu-common.h"
|
2013-02-04 15:40:22 +01:00
|
|
|
#include "hw/qdev.h"
|
|
|
|
#include "hw/ptimer.h"
|
2013-08-21 17:02:47 +02:00
|
|
|
#include "qemu/main-loop.h"
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
/* Common timer implementation. */
|
|
|
|
|
|
|
|
#define TIMER_CTRL_ONESHOT (1 << 0)
|
|
|
|
#define TIMER_CTRL_32BIT (1 << 1)
|
|
|
|
#define TIMER_CTRL_DIV1 (0 << 2)
|
|
|
|
#define TIMER_CTRL_DIV16 (1 << 2)
|
|
|
|
#define TIMER_CTRL_DIV256 (2 << 2)
|
|
|
|
#define TIMER_CTRL_IE (1 << 5)
|
|
|
|
#define TIMER_CTRL_PERIODIC (1 << 6)
|
|
|
|
#define TIMER_CTRL_ENABLE (1 << 7)
|
|
|
|
|
|
|
|
typedef struct {
|
2007-05-23 02:06:54 +02:00
|
|
|
ptimer_state *timer;
|
2006-04-09 03:32:52 +02:00
|
|
|
uint32_t control;
|
|
|
|
uint32_t limit;
|
|
|
|
int freq;
|
|
|
|
int int_level;
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq irq;
|
2006-04-09 03:32:52 +02:00
|
|
|
} arm_timer_state;
|
|
|
|
|
|
|
|
/* Check all active timers, and schedule the next timer interrupt. */
|
|
|
|
|
2007-05-23 02:06:54 +02:00
|
|
|
static void arm_timer_update(arm_timer_state *s)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
|
|
|
/* Update interrupts. */
|
|
|
|
if (s->int_level && (s->control & TIMER_CTRL_IE)) {
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq_raise(s->irq);
|
2006-04-09 03:32:52 +02:00
|
|
|
} else {
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq_lower(s->irq);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint32_t arm_timer_read(void *opaque, hwaddr offset)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
|
|
|
arm_timer_state *s = (arm_timer_state *)opaque;
|
|
|
|
|
|
|
|
switch (offset >> 2) {
|
|
|
|
case 0: /* TimerLoad */
|
|
|
|
case 6: /* TimerBGLoad */
|
|
|
|
return s->limit;
|
|
|
|
case 1: /* TimerValue */
|
2007-05-23 02:06:54 +02:00
|
|
|
return ptimer_get_count(s->timer);
|
2006-04-09 03:32:52 +02:00
|
|
|
case 2: /* TimerControl */
|
|
|
|
return s->control;
|
|
|
|
case 4: /* TimerRIS */
|
|
|
|
return s->int_level;
|
|
|
|
case 5: /* TimerMIS */
|
|
|
|
if ((s->control & TIMER_CTRL_IE) == 0)
|
|
|
|
return 0;
|
|
|
|
return s->int_level;
|
|
|
|
default:
|
2012-10-30 08:45:10 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Bad offset %x\n", __func__, (int)offset);
|
2006-04-09 03:32:52 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-05-23 02:06:54 +02:00
|
|
|
/* Reset the timer limit after settings have changed. */
|
|
|
|
static void arm_timer_recalibrate(arm_timer_state *s, int reload)
|
|
|
|
{
|
|
|
|
uint32_t limit;
|
|
|
|
|
2010-05-02 11:50:52 +02:00
|
|
|
if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
|
2007-05-23 02:06:54 +02:00
|
|
|
/* Free running. */
|
|
|
|
if (s->control & TIMER_CTRL_32BIT)
|
|
|
|
limit = 0xffffffff;
|
|
|
|
else
|
|
|
|
limit = 0xffff;
|
|
|
|
} else {
|
|
|
|
/* Periodic. */
|
|
|
|
limit = s->limit;
|
|
|
|
}
|
|
|
|
ptimer_set_limit(s->timer, limit, reload);
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void arm_timer_write(void *opaque, hwaddr offset,
|
2006-04-09 03:32:52 +02:00
|
|
|
uint32_t value)
|
|
|
|
{
|
|
|
|
arm_timer_state *s = (arm_timer_state *)opaque;
|
2007-05-23 02:06:54 +02:00
|
|
|
int freq;
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
switch (offset >> 2) {
|
|
|
|
case 0: /* TimerLoad */
|
|
|
|
s->limit = value;
|
2007-05-23 02:06:54 +02:00
|
|
|
arm_timer_recalibrate(s, 1);
|
2006-04-09 03:32:52 +02:00
|
|
|
break;
|
|
|
|
case 1: /* TimerValue */
|
|
|
|
/* ??? Linux seems to want to write to this readonly register.
|
|
|
|
Ignore it. */
|
|
|
|
break;
|
|
|
|
case 2: /* TimerControl */
|
|
|
|
if (s->control & TIMER_CTRL_ENABLE) {
|
|
|
|
/* Pause the timer if it is running. This may cause some
|
|
|
|
inaccuracy dure to rounding, but avoids a whole lot of other
|
|
|
|
messyness. */
|
2007-05-23 02:06:54 +02:00
|
|
|
ptimer_stop(s->timer);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
s->control = value;
|
2007-05-23 02:06:54 +02:00
|
|
|
freq = s->freq;
|
2006-04-09 03:32:52 +02:00
|
|
|
/* ??? Need to recalculate expiry time after changing divisor. */
|
|
|
|
switch ((value >> 2) & 3) {
|
2007-05-23 02:06:54 +02:00
|
|
|
case 1: freq >>= 4; break;
|
|
|
|
case 2: freq >>= 8; break;
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
2010-05-02 11:50:51 +02:00
|
|
|
arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
|
2007-05-23 02:06:54 +02:00
|
|
|
ptimer_set_freq(s->timer, freq);
|
2006-04-09 03:32:52 +02:00
|
|
|
if (s->control & TIMER_CTRL_ENABLE) {
|
|
|
|
/* Restart the timer if still enabled. */
|
2007-05-23 02:06:54 +02:00
|
|
|
ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case 3: /* TimerIntClr */
|
|
|
|
s->int_level = 0;
|
|
|
|
break;
|
|
|
|
case 6: /* TimerBGLoad */
|
|
|
|
s->limit = value;
|
2007-05-23 02:06:54 +02:00
|
|
|
arm_timer_recalibrate(s, 0);
|
2006-04-09 03:32:52 +02:00
|
|
|
break;
|
|
|
|
default:
|
2012-10-30 08:45:10 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Bad offset %x\n", __func__, (int)offset);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
2007-05-23 02:06:54 +02:00
|
|
|
arm_timer_update(s);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void arm_timer_tick(void *opaque)
|
|
|
|
{
|
2007-05-23 02:06:54 +02:00
|
|
|
arm_timer_state *s = (arm_timer_state *)opaque;
|
|
|
|
s->int_level = 1;
|
|
|
|
arm_timer_update(s);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
|
2010-12-01 23:15:41 +01:00
|
|
|
static const VMStateDescription vmstate_arm_timer = {
|
|
|
|
.name = "arm_timer",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-05-13 17:09:35 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2010-12-01 23:15:41 +01:00
|
|
|
VMSTATE_UINT32(control, arm_timer_state),
|
|
|
|
VMSTATE_UINT32(limit, arm_timer_state),
|
|
|
|
VMSTATE_INT32(int_level, arm_timer_state),
|
|
|
|
VMSTATE_PTIMER(timer, arm_timer_state),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-07-02 18:48:32 +02:00
|
|
|
|
2009-05-14 23:35:07 +02:00
|
|
|
static arm_timer_state *arm_timer_init(uint32_t freq)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
|
|
|
arm_timer_state *s;
|
2007-05-23 02:06:54 +02:00
|
|
|
QEMUBH *bh;
|
2006-04-09 03:32:52 +02:00
|
|
|
|
2011-08-21 05:09:37 +02:00
|
|
|
s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
|
2007-05-23 02:06:54 +02:00
|
|
|
s->freq = freq;
|
2006-04-09 03:32:52 +02:00
|
|
|
s->control = TIMER_CTRL_IE;
|
|
|
|
|
2007-05-23 02:06:54 +02:00
|
|
|
bh = qemu_bh_new(arm_timer_tick, s);
|
|
|
|
s->timer = ptimer_init(bh);
|
2010-12-01 23:15:41 +01:00
|
|
|
vmstate_register(NULL, -1, &vmstate_arm_timer, s);
|
2006-04-09 03:32:52 +02:00
|
|
|
return s;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* ARM PrimeCell SP804 dual timer module.
|
2011-12-12 11:25:42 +01:00
|
|
|
* Docs at
|
|
|
|
* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html
|
|
|
|
*/
|
2006-04-09 03:32:52 +02:00
|
|
|
|
2013-07-27 14:17:41 +02:00
|
|
|
#define TYPE_SP804 "sp804"
|
|
|
|
#define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804)
|
|
|
|
|
2013-07-27 14:15:46 +02:00
|
|
|
typedef struct SP804State {
|
2013-07-27 14:17:41 +02:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-08-15 16:17:19 +02:00
|
|
|
MemoryRegion iomem;
|
2009-05-14 23:35:07 +02:00
|
|
|
arm_timer_state *timer[2];
|
2011-12-29 07:19:51 +01:00
|
|
|
uint32_t freq0, freq1;
|
2006-04-09 03:32:52 +02:00
|
|
|
int level[2];
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq irq;
|
2013-07-27 14:15:46 +02:00
|
|
|
} SP804State;
|
2006-04-09 03:32:52 +02:00
|
|
|
|
2011-12-12 11:25:42 +01:00
|
|
|
static const uint8_t sp804_ids[] = {
|
|
|
|
/* Timer ID */
|
|
|
|
0x04, 0x18, 0x14, 0,
|
|
|
|
/* PrimeCell ID */
|
|
|
|
0xd, 0xf0, 0x05, 0xb1
|
|
|
|
};
|
|
|
|
|
2007-04-07 20:14:41 +02:00
|
|
|
/* Merge the IRQs from the two component devices. */
|
2006-04-09 03:32:52 +02:00
|
|
|
static void sp804_set_irq(void *opaque, int irq, int level)
|
|
|
|
{
|
2013-07-27 14:15:46 +02:00
|
|
|
SP804State *s = (SP804State *)opaque;
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
s->level[irq] = level;
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_set_irq(s->irq, s->level[0] || s->level[1]);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t sp804_read(void *opaque, hwaddr offset,
|
2011-08-15 16:17:19 +02:00
|
|
|
unsigned size)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
2013-07-27 14:15:46 +02:00
|
|
|
SP804State *s = (SP804State *)opaque;
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
if (offset < 0x20) {
|
|
|
|
return arm_timer_read(s->timer[0], offset);
|
2011-12-12 11:25:42 +01:00
|
|
|
}
|
|
|
|
if (offset < 0x40) {
|
2006-04-09 03:32:52 +02:00
|
|
|
return arm_timer_read(s->timer[1], offset - 0x20);
|
|
|
|
}
|
2011-12-12 11:25:42 +01:00
|
|
|
|
|
|
|
/* TimerPeriphID */
|
|
|
|
if (offset >= 0xfe0 && offset <= 0xffc) {
|
|
|
|
return sp804_ids[(offset - 0xfe0) >> 2];
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (offset) {
|
|
|
|
/* Integration Test control registers, which we won't support */
|
|
|
|
case 0xf00: /* TimerITCR */
|
|
|
|
case 0xf04: /* TimerITOP (strictly write only but..) */
|
2012-10-30 08:45:10 +01:00
|
|
|
qemu_log_mask(LOG_UNIMP,
|
|
|
|
"%s: integration test registers unimplemented\n",
|
|
|
|
__func__);
|
2011-12-12 11:25:42 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-10-30 08:45:10 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: Bad offset %x\n", __func__, (int)offset);
|
2011-12-12 11:25:42 +01:00
|
|
|
return 0;
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void sp804_write(void *opaque, hwaddr offset,
|
2011-08-15 16:17:19 +02:00
|
|
|
uint64_t value, unsigned size)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
2013-07-27 14:15:46 +02:00
|
|
|
SP804State *s = (SP804State *)opaque;
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
if (offset < 0x20) {
|
|
|
|
arm_timer_write(s->timer[0], offset, value);
|
2011-12-12 11:25:42 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (offset < 0x40) {
|
2006-04-09 03:32:52 +02:00
|
|
|
arm_timer_write(s->timer[1], offset - 0x20, value);
|
2011-12-12 11:25:42 +01:00
|
|
|
return;
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
2011-12-12 11:25:42 +01:00
|
|
|
|
|
|
|
/* Technically we could be writing to the Test Registers, but not likely */
|
2012-10-30 08:45:10 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
|
|
|
|
__func__, (int)offset);
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
|
2011-08-15 16:17:19 +02:00
|
|
|
static const MemoryRegionOps sp804_ops = {
|
|
|
|
.read = sp804_read,
|
|
|
|
.write = sp804_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2006-04-09 03:32:52 +02:00
|
|
|
};
|
|
|
|
|
2010-12-01 23:12:32 +01:00
|
|
|
static const VMStateDescription vmstate_sp804 = {
|
|
|
|
.name = "sp804",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
2014-05-13 17:09:35 +02:00
|
|
|
.fields = (VMStateField[]) {
|
2013-07-27 14:15:46 +02:00
|
|
|
VMSTATE_INT32_ARRAY(level, SP804State, 2),
|
2010-12-01 23:12:32 +01:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
2008-07-02 18:48:32 +02:00
|
|
|
|
2013-07-27 14:17:41 +02:00
|
|
|
static int sp804_init(SysBusDevice *sbd)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
2013-07-27 14:17:41 +02:00
|
|
|
DeviceState *dev = DEVICE(sbd);
|
|
|
|
SP804State *s = SP804(dev);
|
2007-04-07 20:14:41 +02:00
|
|
|
qemu_irq *qi;
|
2006-04-09 03:32:52 +02:00
|
|
|
|
2007-04-07 20:14:41 +02:00
|
|
|
qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
|
2013-07-27 14:17:41 +02:00
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2011-12-29 07:19:51 +01:00
|
|
|
s->timer[0] = arm_timer_init(s->freq0);
|
|
|
|
s->timer[1] = arm_timer_init(s->freq1);
|
2009-05-14 23:35:07 +02:00
|
|
|
s->timer[0]->irq = qi[0];
|
|
|
|
s->timer[1]->irq = qi[1];
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &sp804_ops, s,
|
|
|
|
"sp804", 0x1000);
|
2013-07-27 14:17:41 +02:00
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
vmstate_register(dev, -1, &vmstate_sp804, s);
|
2009-08-14 10:36:05 +02:00
|
|
|
return 0;
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Integrator/CP timer module. */
|
|
|
|
|
2013-07-27 14:20:25 +02:00
|
|
|
#define TYPE_INTEGRATOR_PIT "integrator_pit"
|
|
|
|
#define INTEGRATOR_PIT(obj) \
|
|
|
|
OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT)
|
|
|
|
|
2006-04-09 03:32:52 +02:00
|
|
|
typedef struct {
|
2013-07-27 14:20:25 +02:00
|
|
|
SysBusDevice parent_obj;
|
|
|
|
|
2011-08-15 16:17:19 +02:00
|
|
|
MemoryRegion iomem;
|
2009-05-14 23:35:07 +02:00
|
|
|
arm_timer_state *timer[3];
|
2006-04-09 03:32:52 +02:00
|
|
|
} icp_pit_state;
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static uint64_t icp_pit_read(void *opaque, hwaddr offset,
|
2011-08-15 16:17:19 +02:00
|
|
|
unsigned size)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
|
|
|
icp_pit_state *s = (icp_pit_state *)opaque;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
/* ??? Don't know the PrimeCell ID for this device. */
|
|
|
|
n = offset >> 8;
|
2011-11-11 14:30:15 +01:00
|
|
|
if (n > 2) {
|
2012-10-30 08:45:10 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
|
2014-02-26 18:19:58 +01:00
|
|
|
return 0;
|
2009-05-08 03:35:15 +02:00
|
|
|
}
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
return arm_timer_read(s->timer[n], offset & 0xff);
|
|
|
|
}
|
|
|
|
|
2012-10-23 12:30:10 +02:00
|
|
|
static void icp_pit_write(void *opaque, hwaddr offset,
|
2011-08-15 16:17:19 +02:00
|
|
|
uint64_t value, unsigned size)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
|
|
|
icp_pit_state *s = (icp_pit_state *)opaque;
|
|
|
|
int n;
|
|
|
|
|
|
|
|
n = offset >> 8;
|
2011-11-11 14:30:15 +01:00
|
|
|
if (n > 2) {
|
2012-10-30 08:45:10 +01:00
|
|
|
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
|
2014-02-26 18:19:58 +01:00
|
|
|
return;
|
2009-05-08 03:35:15 +02:00
|
|
|
}
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
arm_timer_write(s->timer[n], offset & 0xff, value);
|
|
|
|
}
|
|
|
|
|
2011-08-15 16:17:19 +02:00
|
|
|
static const MemoryRegionOps icp_pit_ops = {
|
|
|
|
.read = icp_pit_read,
|
|
|
|
.write = icp_pit_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2006-04-09 03:32:52 +02:00
|
|
|
};
|
|
|
|
|
2009-08-14 10:36:05 +02:00
|
|
|
static int icp_pit_init(SysBusDevice *dev)
|
2006-04-09 03:32:52 +02:00
|
|
|
{
|
2013-07-27 14:20:25 +02:00
|
|
|
icp_pit_state *s = INTEGRATOR_PIT(dev);
|
2006-04-09 03:32:52 +02:00
|
|
|
|
|
|
|
/* Timer 0 runs at the system clock speed (40MHz). */
|
2009-05-14 23:35:07 +02:00
|
|
|
s->timer[0] = arm_timer_init(40000000);
|
2006-04-09 03:32:52 +02:00
|
|
|
/* The other two timers run at 1MHz. */
|
2009-05-14 23:35:07 +02:00
|
|
|
s->timer[1] = arm_timer_init(1000000);
|
|
|
|
s->timer[2] = arm_timer_init(1000000);
|
|
|
|
|
|
|
|
sysbus_init_irq(dev, &s->timer[0]->irq);
|
|
|
|
sysbus_init_irq(dev, &s->timer[1]->irq);
|
|
|
|
sysbus_init_irq(dev, &s->timer[2]->irq);
|
2006-04-09 03:32:52 +02:00
|
|
|
|
2013-06-07 03:25:08 +02:00
|
|
|
memory_region_init_io(&s->iomem, OBJECT(s), &icp_pit_ops, s,
|
|
|
|
"icp_pit", 0x1000);
|
2011-11-27 10:38:10 +01:00
|
|
|
sysbus_init_mmio(dev, &s->iomem);
|
2008-07-02 18:48:32 +02:00
|
|
|
/* This device has no state to save/restore. The component timers will
|
|
|
|
save themselves. */
|
2009-08-14 10:36:05 +02:00
|
|
|
return 0;
|
2006-04-09 03:32:52 +02:00
|
|
|
}
|
2009-05-14 23:35:07 +02:00
|
|
|
|
2012-01-24 20:12:29 +01:00
|
|
|
static void icp_pit_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
sdc->init = icp_pit_init;
|
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo icp_pit_info = {
|
2013-07-27 14:20:25 +02:00
|
|
|
.name = TYPE_INTEGRATOR_PIT,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(icp_pit_state),
|
|
|
|
.class_init = icp_pit_class_init,
|
|
|
|
};
|
|
|
|
|
|
|
|
static Property sp804_properties[] = {
|
2013-07-27 14:15:46 +02:00
|
|
|
DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000),
|
|
|
|
DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000),
|
2011-12-08 04:34:16 +01:00
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
2012-01-24 20:12:29 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
static void sp804_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
2011-12-08 04:34:16 +01:00
|
|
|
DeviceClass *k = DEVICE_CLASS(klass);
|
2012-01-24 20:12:29 +01:00
|
|
|
|
|
|
|
sdc->init = sp804_init;
|
2011-12-08 04:34:16 +01:00
|
|
|
k->props = sp804_properties;
|
2012-01-24 20:12:29 +01:00
|
|
|
}
|
|
|
|
|
2013-01-10 16:19:07 +01:00
|
|
|
static const TypeInfo sp804_info = {
|
2013-07-27 14:17:41 +02:00
|
|
|
.name = TYPE_SP804,
|
2011-12-08 04:34:16 +01:00
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
2013-07-27 14:15:46 +02:00
|
|
|
.instance_size = sizeof(SP804State),
|
2011-12-08 04:34:16 +01:00
|
|
|
.class_init = sp804_class_init,
|
2012-01-24 20:12:29 +01:00
|
|
|
};
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
static void arm_timer_register_types(void)
|
2009-05-14 23:35:07 +02:00
|
|
|
{
|
2011-12-08 04:34:16 +01:00
|
|
|
type_register_static(&icp_pit_info);
|
|
|
|
type_register_static(&sp804_info);
|
2009-05-14 23:35:07 +02:00
|
|
|
}
|
|
|
|
|
2012-02-09 15:20:55 +01:00
|
|
|
type_init(arm_timer_register_types)
|