Commit Graph

538 Commits

Author SHA1 Message Date
Stefan Weil 2a5612e6a3 target-mips: Fix format specifiers for fpu_fprintf
In the previous patch which introduced fprintf_function to
allow parameter checking by gcc some compiler warnings
remained unfixed.

These warnings are fixed here.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-09 21:53:23 +02:00
Stefan Weil a7200c9f98 target-mips: Fix one more format specifier for cpu_fprintf
env->bcond must be printed using TARGET_FMT_ld.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:46:57 +02:00
Paolo Bonzini 1a7ff92218 remove TARGET_* defines from translate-all.c
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-04-08 21:34:12 +02:00
Paul Brook d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
Aurelien Jarno 30724e758a target-mips: update address space definitions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-13 11:35:55 +01:00
Paul Brook 3c7b48b74c Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:44:24 +00:00
Paul Brook 4fcc562bff Remove cpu_get_phys_page_debug from userspace emulation
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:34:25 +00:00
Richard Henderson 5270589032 Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.
Removes a set of ifdefs from exec.c.

Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other
than Alpha.  This will be used for page_find_alloc, which is
supposed to be using virtual addresses in the first place.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2010-03-12 16:28:24 +00:00
Aurelien Jarno deb4203dc9 target-mips: use newer logical ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-04 17:42:03 +01:00
Aurelien Jarno e68dd28fd7 target-mips: use setcond when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-02 23:16:56 +01:00
Nathan Froyd 3399e30f56 target-mips: fix ROTR and DROTR by zero
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:25 +01:00
Nathan Froyd c2c65dab45 target-mips: fix CpU exception for coprocessor 0
When we signal a CpU exception for coprocessor 0, we should indicate
that it's for coprocessor 0 instead of coprocessor 1.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:24 +01:00
Aurelien Jarno 6462bfcded target-mips: remove useless sign extension
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-23 19:47:24 +01:00
Aurelien Jarno c36bbb28ad target-mips: don't call cpu_loop_exit() from helper.c
In helper.c AREG0 may not correspond do env, so it's not possible to
call cpu_loop_exit() here. Call it from op_helper.c instead.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:23:33 +01:00
Paolo Bonzini 49a945a3c0 kill regs_to_env and env_to_regs
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-01-19 16:31:02 -06:00
Stefan Weil ab3aee26c4 target-mips: No MIPS16 support for 4Kc, 4KEc cores
Fix regression introduced by d19954f46d.

4Kc and 4KEc don't support MIPS16.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-17 00:28:58 +01:00
Stefan Weil 73642f5bdb target-mips: 4Kc, 4KEc cores do not support MIPS16
4Kc, 4KEc cores do not support MIPS16, so not only the
CP0_Config1 had to be fixed (see previous patch),
but also MIPS16 instructions must not be executed.

(Hint from Nathan Froyd, thanks).

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-16 18:20:19 +01:00
Nathan Froyd 91a7593526 target-mips: fix user-mode emulation startup
Running programs with the MIPS user-mode emulator fails during dynamic
loading, as floating-point instructions are not enabled in in
env->hflags.  Move the code for doing so from fpu_init to cpu_reset so
the MIPS_HFLAG_{FPU,F64} setting doesn't get clobbered by cpu_reset
setting env->hflags to MIPS_HFLAG_UM.

The same end can be achieved by swapping the ordering of fpu_init and
cpu_reset in cpu_mips_init, but it seemed better to consolidate the
CONFIG_USER_ONLY code into a single location.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 21:01:33 +01:00
Nathan Froyd d19954f46d target-mips: set Config1.CA for MIPS16-aware CPUs
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd 9da53be7ea target-mips: add copyright notice for mips16 work
Also cross off mips16 ASE in TODO.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd 364d48314a target-mips: add mips16 instruction decoding
There's no good way to add this incrementally, so we do it all at once.
The only changes to shared code are in handle_delay_slot.  We need to
flip ISAMode when doing a jump-and-exchange.  We also need to set
ISAMode the low bit of the target address for jump-to-register.

Also, since we're now adding bits that can be in MIPS_HFLAG_BMASK_EXT,
make sure we use MIPS_HFLAG_BMASK_BASE in the places where we just want
basic information about a branch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd 6ea219d019 target-mips: add enums for MIPS16 opcodes
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:20 +01:00
Nathan Froyd c960206137 target-mips: split out delay slot handling
Move delay slot handling to common code whose invocation can be
controlled from gen_intermediate_code_internal.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd 662d748516 target-mips: add gen_base_offset_addr
This is a common pattern in existing code.  We'll also use it to
implement the mips16 SAVE/RESTORE instructions.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd 7dca4ad050 target-mips: make gen_compute_branch 16/32-bit-aware
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd ea63e2c358 target-mips: move ROTR and ROTRV inside gen_shift_{imm, }
It's easier to implement mips16 shift instructions if we're not
examining the opcode inside gen_shift_{imm,}.  So move ROTR and ROTRV
and do the special-case handling of SRL and SRLV inside decode_opc.
Likewise for their 64-bit counterparts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd 32188a03da target-mips: change interrupt bits to be mips16-aware
We need to stash the operating mode into the low bit of the error PC and
restore it on return from interrupts.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Nathan Froyd 79ef2c4cdb target-mips: add new HFLAGs for JALX and 16/32-bit delay slots
We create separate masks for the "basic" branch hflags and the
"extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or
of those two.  This is done to avoid churning the codebase in lots of
different places.

We also make the execution mode an hflag under MIPS_HFLAG_TMASK

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Aurelien Jarno e7139c440c target-mips: use physical address in lladdr
Currently the ll/sc instructions use the virtual address in both
user and system mode. Use the physical address insteead in system
mode.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:18:28 +01:00
Aurelien Jarno 25b91e32e0 target-mips: add a function to do virtual -> physical translations
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:10:04 +01:00
Aurelien Jarno 1147e18994 target-mips: split code raising MMU exception in a separate function
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:10:00 +01:00
Aurelien Jarno 0ae430454c target-mips: factorize load/store code in op_helper.c
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:06:25 +01:00
Aurelien Jarno 60c9af07aa target-mips: fix physical address type in MMU functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:37:04 +01:00
Aurelien Jarno 2a6e32dd46 target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22 14:12:19 +01:00
Aurelien Jarno 5499b6ffac target-mips: rename CP0_LLAddr into lladdr
The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:12:13 +01:00
Aurelien Jarno 31e3104fdb target-mips: fix indentation
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 13:10:00 +01:00
Blue Swirl 51cc2e783a mips: fix cpu_reset memory leak
Remove cpu_mips_register()
- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()
- move the other parts in cpu_mips_init()

Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 02:25:52 +01:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Aurelien Jarno 941694d09a target-mips: make sure constants are in the second argument
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 23:12:51 +02:00
Stefan Weil a0d700e43b mips: Fix spelling in comment
inofficial -> unofficial

Thanks to Blue Swirl.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-30 19:07:15 +00:00
Michael S. Tsirkin 58caed6dda target-mips: unmatched brackets in if 0
Fix unmatched braket in commented out code

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-30 18:45:50 +00:00
Aurelien Jarno 618b0fe9ab target-mips: log instructions start in TCG code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-28 13:03:30 +02:00
Aurelien Jarno d42320c26a target-mips: remove MAX_OP_PER_INSTR workaround
Now that MAX_OP_PER_INSTR has been increased to a safer value, removed
the target-mips specific workaround.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-23 09:25:03 +02:00
Blue Swirl 6f4fc3679c Add 'static' to please Sparse
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-21 18:39:26 +00:00
Nathan Froyd 7b270ef2a3 target-mips: fix single-stepping
Single-stepping branches on MIPS didn't work right, because the
generation of EXCP_DEBUG happened after the generation of the code to
exit the current TB.  That is, given the code:

    bne v0,v1,target
    nop
    ...
  target:
    addu v0,v0,v1
  1:

when you single-stepped through the NOP, execution wouldn't actually
halt until you reached the label `1'.

This patch corrects that and also changes single-stepping so that a
branch and its delay slot are executed as one instruction for the
purposes of single-stepping.  This behavior is comparable to what other
MIPS tools (e.g. MIPSsim with MDI) do.  GDB avoids placing breakpoints
in branch delay slots, so this change doesn't break anything on the GDB
side.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-14 19:34:12 +02:00
Blue Swirl 72cf2d4f0e Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-12 07:36:22 +00:00
Nathan Froyd fa31af0e63 target-mips: fix conditional moves off fp condition codes
Conditional moves off fp condition codes were using the result of
get_fp_bit to isolate and test the relevant condition code.  However,
get_fp_bit returns the bit number of the condition code, not a
bitmask.  (Compare the use of get_fp_bit in gen_compute_branch1, for
instance.)

Fixed by shifting a bitmask into place using the result of get_fp_bit in
the relevant functions (gen_mov{ci,cf_s,cf_d,cf_ps}).

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-08-25 18:05:27 +02:00
Nathan Froyd 0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Juan Quintela e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00