OpenE2K/qemu-e2k
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104 Commits

Author SHA1 Message Date
Richard Henderson
32d98fbd10 tcg: Allow target-specific implementation of NOR. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:52:44 +01:00
Richard Henderson
9940a96bc8 tcg: Allow target-specific implementation of NAND. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:44:40 +01:00
Richard Henderson
8d625cf1d1 tcg: Allow target-specific implementation of EQV. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:42:46 +01:00
Richard Henderson
8a56e84091 tcg: Use TCGCond where appropriate. 
Use the TCGCond enumeration type in the brcond and setcond
related prototypes in tcg-op.h and each code generator.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:29:08 +01:00
Richard Henderson
a975160954 tcg: Name the opcode enumeration. 
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.
Use that enumeration type instead of "int" whereever appropriate.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 21:28:24 +01:00
Paolo Bonzini
a63b5829af remove remaining occurrences AREG[1-9] and TCG_AREG[1-9] 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2010-03-26 20:48:30 +01:00
malc
35f6b5997a tcg/ppc[64]: Only define addend load helpers in softmmu case 
Signed-off-by: malc <av1474@comtv.ru>
 2010-03-13 00:27:46 +03:00
malc
d616cf1d15 tcg/ppc: Fix right rotation 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-27 02:00:00 +03:00
malc
98b8d951dc tcg/ppc: Fix typo 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-23 00:50:03 +03:00
malc
65fe043eb4 tcg/ppc: Implement some of the optional ops 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-22 21:50:01 +03:00
Jay Foad
30c0c76ce0 tcg: fix build on 32-bit hppa, ppc and sparc hosts 
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.

Signed-off-by: Jay Foad <jay.foad@gmail.com>
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-22 19:38:52 +03:00
Richard Henderson
3682825669 tcg: Add comments for all optional instructions not implemented. 
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2010-02-20 08:35:12 +00:00
malc
6ec8523603 tcg/ppc: Consistently use calling convention selection macros 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-20 01:47:35 +03:00
Juergen Lock
5da79c86a3 Use ppc host calling convention definitions to set TCG_TARGET_CALL_{ALIGN_ARGS,STACK_OFFSET}. 
New version after malc's comments.  (This avoids having to do
  #if defined __linux__ || defined __FreeBSD__ || defined __FreeBSD_kernel__
for the third case.)

Submitted by: Andreas Tobler <andreast@fgznet.ch>  (original version)

Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de>
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-20 01:37:33 +03:00
malc
27a7797b09 tcg/ppc32: proper setcond implementation 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-07 02:48:48 +03:00
malc
b0809bf7ca tcg/ppc32: implement setcond[2] 
Signed-off-by: malc <av1474@comtv.ru>
 2010-02-07 02:18:06 +03:00
malc
d937032764 tcg/ppc: always use tcg_out_call 
Signed-off-by: malc <av1474@comtv.ru>
 2009-09-27 14:41:14 +04:00
malc
c45851c44a When targeting PPU use rlwinm instead of andi. if possible 
andi. is microcoded and slow there.

Signed-off-by: malc <av1474@comtv.ru>
 2009-09-06 07:24:37 +04:00
malc
a71836de38 Fix rbase initialization 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-20 01:15:23 +04:00
malc
f6548c0a4b PPC 32/64 GUEST_BASE support 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-18 13:16:36 +04:00
malc
4f4a67ae78 Fix LHZX opcode value 
Signed-off-by: malc <av1474@comtv.ru>
 2009-07-18 13:16:13 +04:00
malc
9de187a099 Whack [LS]MW 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-11 07:39:04 +00:00
malc
e23f2f36b1 Remove reserved registers from tcg_target_reg_alloc_order 
Noticed by Andreas Faerber

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-11 07:38:56 +00:00
blueswir1
e63d7abdde Prune unused TCG_AREGs 
Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-08 14:45:45 +00:00
malc
eb2eb1dc00 Add missing r24..r26 to calle save registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-11 18:51:19 +00:00
malc
5db3ee7991 R13 is reserved for small data area pointer by SVR4 PPC ABI 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-26 18:21:53 +00:00
malc
b1503cda1e Use the ARRAY_SIZE() macro where appropriate. 
Change from v1:
  Avoid changing the existing coding style in certain files.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-22 20:33:55 +00:00
malc
902b3d5c39 Introduce and use cache-utils.[ch] 
Thanks to Segher Boessenkool and Holis Blanchard.

AIX and Darwin cache inquiry:
http://gcc.gnu.org/ml/gcc-patches/2007-08/msg00388.html

Auxiliary vectors:
http://manugarg.googlepages.com/aboutelfauxiliaryvectors

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5973 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-10 19:18:40 +00:00
malc
b29fe3ed48 Preliminary AIX support 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 01:42:22 +00:00
malc
2946898b48 Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSET 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-12 20:36:24 +00:00
blueswir1
d4a9eb1fc6 Add some missing static and const qualifiers, reg_names only used if NDEBUG set 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-05 09:59:14 +00:00
malc
f8edcbaa2d Avoid clobbering input register in qemu_ld64+bswap+useronly case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-22 01:08:08 +00:00
blueswir1
79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 09:51:20 +00:00
malc
70fa887c14 Relax qemu_ld/st constraints for !SOFTMMU case 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-21 01:14:07 +00:00
malc
bf6bca527c Account for MacOS X ABI reserved space in linkage area (Andreas Faerber) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-03 19:04:11 +00:00
malc
f9bf298717 Preliminary MacOS X on PPC32 support 
Big thanks to BlueSwirl for Sparc failure analysis.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-03 19:04:07 +00:00
malc
52781543ad On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64 
Avoids nasty warnings about flush_icache_range from gcc4 and inability
to compile [cpu-]exec.c with gcc3 and -O, also the function is much
too large to be candidate for inlining anyway.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-29 20:08:17 +00:00
malc
000a2d866a Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-28 23:46:03 +00:00
malc
e46b9681e5 Provide extNs_M instructions 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-23 20:01:23 +00:00
malc
e924c48573 Fuse EQ and NE handling in tcg_out_brcond2 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 23:49:14 +00:00
malc
8c5e95d807 Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 18:51:23 +00:00
malc
ca88500f43 According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 05:47:06 +00:00
malc
a35e86c55f Shuffle contents of tcg_target_reg_alloc_order 
Move reserved/volatile registers down. Currently qemu_ld/stXX are
marked with TCG_OPF_CALL_CLOBBER and since memory accesses are
frequent and R3 through R12 are volatile moving this down results in
less spills and tighter generated code.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4778 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-23 05:47:03 +00:00
malc
17ca26e791 Save LR into proper place on callers stack frame 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4745 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-18 01:58:52 +00:00
malc
c596defdb9 Reimplement brcond2 and refactor brcond 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4738 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-12 12:33:10 +00:00
malc
0d5bd3631f Remove stray variable 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4725 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-10 01:47:17 +00:00
malc
77b73de676 Use rem/div[u]_i32 drop div[u]2_i32 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4722 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 23:44:44 +00:00
malc
fa4fbfb98a Emit trampolines manually in prologue 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4715 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 19:57:36 +00:00
malc
5d794885a2 Fix test for signed div fast path 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4714 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 19:57:27 +00:00
malc
398ce98e4f Fix div[u]2. 
Previous code assummed 32 by 32 bit divmod operation, and survived
x86_64 test only by sheer luck. MIPS wasn't so forgiving.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4705 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-09 06:06:25 +00:00
malc
0a878c4760 PPC TCG Fixes 
* Fix typo in aliased div2
* "Optimize" aliased div2/divu2
* Fix two remaining branch retranslation problems
  (Kudos to Andrzej Zaborowski)
* Rework goto_tb and set_jmp_target1
* Use correct size when flushing icache
* Use correct register selection for ORI
  (Was harmless since in both cases srcreg was equal to dstreg)



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4691 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-07 20:31:33 +00:00
bellard
932a690969 support of long calls for PPC (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4629 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-30 20:56:52 +00:00
bellard
f3f478a7ef Fix signed/unsigned issues of immediate version of brcond (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4588 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-26 19:11:07 +00:00
bellard
2662e13f68 ppc TCG target (malc) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4584 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 18:59:57 +00:00