OpenE2K/qemu-e2k
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qemu-e2k/target/riscv
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Alexey Baturo 0ee9a4e57e target/riscv: Allow experimental J-ext to be turned on 
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211025173609.2724490-9-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-28 14:39:23 +10:00
..
insn_trans
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
2021-10-28 14:39:23 +10:00
arch_dump.c
…
bitmanip_helper.c
target/riscv: Add rev8 instruction, removing grev/grevi
2021-10-07 08:41:33 +10:00
cpu_bits.h
target/riscv: Add CSR defines for RISC-V PM extension
2021-10-28 14:39:23 +10:00
cpu_helper.c
target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
2021-10-28 14:39:23 +10:00
cpu_user.h
…
cpu-param.h
…
cpu.c
target/riscv: Allow experimental J-ext to be turned on
2021-10-28 14:39:23 +10:00
cpu.h
target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
2021-10-28 14:39:23 +10:00
csr.c
target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode
2021-10-28 14:39:23 +10:00
fpu_helper.c
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00
gdbstub.c
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-22 07:47:51 +10:00
helper.h
target/riscv: Add rev8 instruction, removing grev/grevi
2021-10-07 08:41:33 +10:00
insn16.decode
target/riscv: Consolidate RV32/64 16-bit instructions
2021-05-11 20:02:07 +10:00
insn32.decode
target/riscv: Remove RVB (replaced by Zb[abcs])
2021-10-07 08:41:33 +10:00
instmap.h
…
internals.h
…
Kconfig
meson: Introduce target-specific Kconfig
2021-07-09 18:21:34 +02:00
machine.c
target/riscv: Add J extension state description
2021-10-28 14:39:23 +10:00
meson.build
target/riscv: rvb: generalized reverse
2021-06-08 09:59:45 +10:00
monitor.c
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
2021-10-22 07:47:51 +10:00
op_helper.c
target/riscv: Reorg csr instructions
2021-09-01 11:59:12 +10:00
pmp.c
target/riscv: pmp: Fix some typos
2021-07-15 08:56:00 +10:00
pmp.h
…
trace-events
…
trace.h
…
translate.c
target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension
2021-10-28 14:39:23 +10:00
vector_helper.c
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00