LIU Zhiwei f297245f6a target/riscv: Relax UXL field for debugging ... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-24-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-01-21 15:52:57 +10:00
..
insn_trans	target/riscv: Adjust scalar reg in vector with XLEN	2022-01-21 15:52:57 +10:00
arch_dump.c
bitmanip_helper.c
cpu_bits.h	target/riscv: Enable uxl field write	2022-01-21 15:52:57 +10:00
cpu_helper.c	target/riscv: Split out the vill from vtype	2022-01-21 15:52:57 +10:00
cpu_user.h
cpu-param.h
cpu.c	target/riscv: Set default XLEN for hypervisor	2022-01-21 15:52:57 +10:00
cpu.h	target/riscv: Remove VILL field in VTYPE	2022-01-21 15:52:57 +10:00
csr.c	target/riscv: Relax UXL field for debugging	2022-01-21 15:52:57 +10:00
fpu_helper.c
gdbstub.c	target/riscv: Use gdb xml according to max mxlen	2022-01-21 15:52:57 +10:00
helper.h	target/riscv: Don't save pc when exception return	2022-01-21 15:52:57 +10:00
insn16.decode
insn32.decode	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
instmap.h
internals.h
Kconfig
kvm_riscv.h	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm-stub.c	target/riscv: Support setting external interrupt by KVM	2022-01-21 15:52:56 +10:00
kvm.c	target/riscv: Implement virtual time adjusting with vm state changing	2022-01-21 15:52:56 +10:00
m128_helper.c	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
machine.c	target/riscv: Split out the vill from vtype	2022-01-21 15:52:57 +10:00
meson.build	target/riscv: Support start kernel directly by KVM	2022-01-21 15:52:56 +10:00
monitor.c
op_helper.c	target/riscv: Adjust csr write mask with XLEN	2022-01-21 15:52:57 +10:00
pmp.c	target/riscv: Adjust pmpcfg access with mxl	2022-01-21 15:52:57 +10:00
pmp.h
sbi_ecall_interface.h	target/riscv: Handle KVM_EXIT_RISCV_SBI exit	2022-01-21 15:52:56 +10:00
trace-events
trace.h
translate.c	target/riscv: Split pm_enabled into mask and base	2022-01-21 15:52:57 +10:00
vector_helper.c	target/riscv: Adjust vector address with mask	2022-01-21 15:52:57 +10:00