Daniel Henrique Barboza 1dbb6104ff target/riscv/cpu.c: make misa_ext_cfgs[] 'const' ... The array isn't marked as 'const' because we're initializing their elements in riscv_cpu_add_misa_properties(), 'name' and 'description' fields. In a closer look we can see that we're not using these 2 fields after creating the MISA properties. And we can create the properties by using riscv_get_misa_ext_name() and riscv_get_misa_ext_description() directly. Remove the 'name' and 'description' fields from RISCVCPUMisaExtConfig and make misa_ext_cfgs[] a const array. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230925175709.35696-17-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-10-12 12:25:12 +10:00
..
insn_trans	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
kvm	target/riscv/kvm: do not use riscv_cpu_add_misa_properties()	2023-10-12 12:21:37 +10:00
tcg	target/riscv/tcg: introduce tcg_cpu_instance_init()	2023-10-12 12:24:07 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Update CSR bits name for svadu extension	2023-09-11 11:45:55 +10:00
cpu_cfg.h	target/riscv: Add Zihintntl extension ISA string to DTS	2023-09-11 11:45:55 +10:00
cpu_helper.c	target/riscv: Update CSR bits name for svadu extension	2023-09-11 11:45:55 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add 'max' CPU type	2023-10-12 11:39:33 +10:00
cpu.c	target/riscv/cpu.c: make misa_ext_cfgs[] 'const'	2023-10-12 12:25:12 +10:00
cpu.h	target/riscv/tcg: introduce tcg_cpu_instance_init()	2023-10-12 12:24:07 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c	2023-10-12 11:57:46 +10:00
debug.c	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
debug.h	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
fpu_helper.c	riscv: Add support for the Zfa extension	2023-07-10 22:29:20 +10:00
gdbstub.c
helper.h	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
insn16.decode
insn32.decode	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
instmap.h
internals.h
Kconfig
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c	target/riscv: Restrict KVM-specific fields from ArchCPU	2023-06-28 14:27:59 +02:00
meson.build	target/riscv: move KVM only files to kvm subdir	2023-10-12 12:20:24 +10:00
monitor.c	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
op_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
pmp.c	target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes	2023-09-11 11:45:55 +10:00
pmp.h	target/riscv: Change the return type of pmp_hart_has_privs() to bool	2023-06-13 17:09:13 +10:00
pmu.c	target/riscv/pmu: Restrict 'qemu/log.h' include to source	2023-08-31 19:47:43 +02:00
pmu.h	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	accel/tcg: Replace CPUState.env_ptr with cpu_env()	2023-10-04 11:03:54 -07:00
vcrypto_helper.c	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
vector_helper.c	tcg: Correct invalid mentions of 'softmmu' by 'system-mode'	2023-10-07 19:02:33 +02:00
vector_internals.c	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:54 +10:00
vector_internals.h	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:55 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c