OpenE2K/qemu-e2k
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qemu-e2k/target/riscv
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Philippe Mathieu-Daudé b8012ecff1 target: Add missing "qemu/timer.h" include 
timer_new_ns(), cpu_get_host_ticks() and NANOSECONDS_PER_SECOND are
declared in "qemu/timer.h".

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220207082756.82600-8-f4bug@amsat.org>
Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-02-21 10:18:06 +01:00
..
insn_trans
target/riscv: add support for svinval extension
2022-02-16 12:25:52 +10:00
arch_dump.c
…
bitmanip_helper.c
…
cpu_bits.h
target/riscv: add support for svpbmt extension
2022-02-16 12:25:52 +10:00
cpu_helper.c
target/riscv: add support for svpbmt extension
2022-02-16 12:25:52 +10:00
cpu_user.h
…
cpu-param.h
…
cpu.c
target/riscv: add support for svpbmt extension
2022-02-16 12:25:52 +10:00
cpu.h
target/riscv: add support for svinval extension
2022-02-16 12:25:52 +10:00
csr.c
target: Add missing "qemu/timer.h" include
2022-02-21 10:18:06 +01:00
fpu_helper.c
target/riscv: add "set round to odd" rounding mode helper function
2021-12-20 14:53:31 +10:00
gdbstub.c
target/riscv: correct "code should not be reached" for x-rv128
2022-02-16 12:24:18 +10:00
helper.h
target/riscv: Don't save pc when exception return
2022-01-21 15:52:57 +10:00
insn16.decode
target/riscv: accessors to registers upper part and 128-bit load/store
2022-01-08 15:46:10 +10:00
insn32.decode
target/riscv: add support for svinval extension
2022-02-16 12:25:52 +10:00
instmap.h
…
internals.h
target/riscv: add "set round to odd" rounding mode helper function
2021-12-20 14:53:31 +10:00
Kconfig
…
kvm_riscv.h
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm-stub.c
target/riscv: Support setting external interrupt by KVM
2022-01-21 15:52:56 +10:00
kvm.c
target/riscv: Implement virtual time adjusting with vm state changing
2022-01-21 15:52:56 +10:00
m128_helper.c
target/riscv: support for 128-bit M extension
2022-01-08 15:46:10 +10:00
machine.c
target/riscv: Implement AIA xiselect and xireg CSRs
2022-02-16 12:24:19 +10:00
meson.build
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00
monitor.c
…
op_helper.c
target/riscv: Adjust csr write mask with XLEN
2022-01-21 15:52:57 +10:00
pmp.c
target/riscv: Adjust pmpcfg access with mxl
2022-01-21 15:52:57 +10:00
pmp.h
…
sbi_ecall_interface.h
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
2022-01-21 15:52:56 +10:00
trace-events
…
trace.h
…
translate.c
target/riscv: add support for svinval extension
2022-02-16 12:25:52 +10:00
vector_helper.c
target/riscv: Fix vill field write in vtype
2022-02-16 12:24:18 +10:00
XVentanaCondOps.decode
target/riscv: Add XVentanaCondOps custom extension
2022-02-16 12:24:18 +10:00