Frederic Barrat 6f2cbd133d pnv/xive2: Handle TIMA access through all ports ... The Thread Interrupt Management Area (TIMA) can be accessed through 4 ports, targeted by the address. The base address of a TIMA is using port 0 and the other ports are 0x80 apart. Using one port or another can be useful to balance the load on the snoop buses. With skiboot and linux, we currently use port 0, but as it tends to be busy, another hypervisor is using port 1 for TIMA access. The port address bits fall in between the special op indication bits (the 2 MSBs) and the register offset bits (the 6 LSBs). They are "don't care" for the hardware when processing a TIMA operation. This patch filters out those port address bits so that a TIMA operation can be triggered using any port. It is also true for indirect access (through the IC BAR) and it's actually nothing new, it was already the case on P9. Which helps here, as the TIMA handling code is common between P9 (xive) and P10 (xive2). Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20230601121331.487207-6-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>		2023-06-10 10:19:24 -03:00
..
allwinner-a10-pic.c	hw/intc/allwinner-a10-pic: Don't use set_bit()/clear_bit()	2023-05-02 15:47:41 +01:00
apic_common.c	hw/intc: Extract the IRQ counting functions into a separate file	2023-01-13 16:22:57 +01:00
apic.c	apic: disable reentrancy detection for apic-msi	2023-04-28 11:31:54 +02:00
arm_gic_common.c	hw/intc: Convert TYPE_ARM_GIC_COMMON to 3-phase reset	2022-12-15 11:18:20 +00:00
arm_gic_kvm.c	hw/intc: Convert TYPE_ARM_GIC_KVM to 3-phase reset	2022-12-15 11:18:20 +00:00
arm_gic.c	hw/intc: add implementation of GICD_IIDR to Arm GIC	2022-11-21 11:45:13 +00:00
arm_gicv2m.c
arm_gicv3_common.c	hw/intc: Convert TYPE_ARM_GICV3_COMMON to 3-phase reset	2022-12-15 11:18:20 +00:00
arm_gicv3_cpuif_common.c
arm_gicv3_cpuif.c	target/arm: Mark up sysregs for HFGRTR bits 36..63	2023-02-03 12:59:23 +00:00
arm_gicv3_dist.c	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	2023-01-18 11:14:34 +01:00
arm_gicv3_its_common.c	hw/intc: Convert TYPE_ARM_GICV3_ITS_COMMON to 3-phase reset	2022-12-15 11:18:20 +00:00
arm_gicv3_its_kvm.c	hw/intc: Convert TYPE_KVM_ARM_ITS to 3-phase reset	2022-12-15 11:18:20 +00:00
arm_gicv3_its.c	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	2023-01-18 11:14:34 +01:00
arm_gicv3_kvm.c	hw/intc: Convert TYPE_KVM_ARM_GICV3 to 3-phase reset	2022-12-15 11:18:20 +00:00
arm_gicv3_redist.c	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	2023-01-18 11:14:34 +01:00
arm_gicv3.c
armv7m_nvic.c	hw/intc/armv7m_nvic: Use QOM cast CPU() macro	2023-02-27 13:27:05 +00:00
aspeed_vic.c
bcm2835_ic.c
bcm2836_control.c
etraxfs_pic.c
exynos4210_combiner.c	bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx	2023-01-18 11:14:34 +01:00
exynos4210_gic.c
gic_internal.h
gicv3_internal.h
goldfish_pic.c
grlib_irqmp.c
heathrow_pic.c	hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h	2022-10-31 18:48:23 +00:00
i8259_common.c	hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select	2023-03-08 00:37:48 +01:00
i8259.c	hw/intc/i8259: Implement legacy LTIM Edge/Level Bank Select	2023-03-08 00:37:48 +01:00
imx_avic.c
imx_gpcv2.c
intc.c
ioapic_common.c	hw: Move ioapic*.h to intc/	2023-02-27 22:29:01 +01:00
ioapic_internal.h	hw: Move ioapic*.h to intc/	2023-02-27 22:29:01 +01:00
ioapic.c	hw/intc/ioapic: Update KVM routes before redelivering IRQ, on RTE update	2023-03-15 11:52:25 +01:00
Kconfig	hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers	2023-01-06 10:42:55 +10:00
kvm_irqcount.c	hw/intc: Extract the IRQ counting functions into a separate file	2023-01-13 16:22:57 +01:00
loongarch_extioi.c	bulk: Remove pointless QOM casts	2023-06-05 20:48:34 +02:00
loongarch_ipi.c	hw/intc/loongarch_ipi: Bring back all 4 IPI mailboxes	2023-06-05 11:08:55 +08:00
loongarch_pch_msi.c	hw/intc/loongarch_pch_msi: add irq number property	2023-01-06 10:54:20 +08:00
loongarch_pch_pic.c	hw/intc/loongarch_pch: Change default irq number of pch irq controller	2023-01-06 14:12:43 +08:00
loongson_liointc.c
m68k_irqc.c
meson.build	hw/intc: Mark more interrupt-controller files as target independent	2023-01-16 17:56:59 +01:00
mips_gic.c	hw/mips: Declare all length properties as unsigned	2023-03-08 00:37:48 +01:00
nios2_vic.c
omap_intc.c	hw/intc/omap_intc: Use CamelCase for TYPE_OMAP_INTC type name	2023-01-12 17:15:09 +00:00
ompic.c
openpic_kvm.c
openpic.c	hw/ppc/mac.h: Rename to include/hw/nvram/mac_nvram.h	2022-10-31 18:48:23 +00:00
pl190.c
pnv_xive2_regs.h	pnv/xive2: Add definition for the ESB cache configuration register	2023-06-10 10:19:24 -03:00
pnv_xive2.c	pnv/xive2: Handle TIMA access through all ports	2023-06-10 10:19:24 -03:00
pnv_xive_regs.h
pnv_xive.c	include/hw/ppc: Split pnv_chip.h off pnv.h	2023-01-20 07:25:10 +01:00
ppc-uic.c
realview_gic.c
riscv_aclint.c	hw: intc: Use cpu_by_arch_id to fetch CPU state	2023-03-05 15:33:40 -08:00
riscv_aplic.c	hw/intc/riscv_aplic: Zero init APLIC internal state	2023-05-05 10:49:50 +10:00
riscv_imsic.c	hw: intc: Use cpu_by_arch_id to fetch CPU state	2023-03-05 15:33:40 -08:00
rx_icu.c
s390_flic_kvm.c
s390_flic.c
sh_intc.c
sifive_plic.c	hw/intc: sifive_plic: Fix the pending register range check	2023-01-06 10:42:55 +10:00
slavio_intctl.c
spapr_xive_kvm.c
spapr_xive.c
trace-events	hw/intc: Add NULL pointer check on LoongArch ipi device	2023-05-15 19:09:33 +08:00
trace.h
vgic_common.h
xics_kvm.c
xics_pnv.c
xics_spapr.c
xics.c	hw/intc/xics: Convert TYPE_ICS to 3-phase reset	2022-12-16 15:59:07 +00:00
xilinx_intc.c	hw/intc/xilinx_intc: Use 'XpsIntc' typedef instead of 'struct xlx_pic'	2023-01-12 17:15:09 +00:00
xive2.c
xive.c	pnv/xive2: Handle TIMA access through all ports	2023-06-10 10:19:24 -03:00
xlnx-pmu-iomod-intc.c
xlnx-zynqmp-ipi.c