qemu-e2k/hw/misc
Peter Delevoryas 55c57023b7 hw/misc/aspeed: Add PECI controller
This introduces a really basic PECI controller that responses to
commands by always setting the response code to success and then raising
an interrupt to indicate the command is done. This helps avoid getting
hit with constant errors if the driver continuously attempts to send a
command and keeps timing out.

The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC.
They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support
PECI 4.0, which includes more read/write buffer registers from 0x80 to
0xFC to support 64-byte mode.

This patch doesn't attempt to handle that, or to create a different
version of the controller for the different generations, since it's only
implementing functionality that is common to all generations.

The basic sequence of events is that the firmware will read and write to
various registers and then trigger a command by setting the FIRE bit in
the command register (similar to the I2C controller).

Then the firmware waits for an interrupt from the PECI controller,
expecting the interrupt status register to be filled in with info on
what happened. If the command was transmitted and received successfully,
then response codes from the host CPU will be found in the data buffer
registers.

Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220630045133.32251-12-me@pjd.dev>
[ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-06-30 09:21:14 +02:00
..
macio
a9scu.c
allwinner-cpucfg.c
allwinner-h3-ccu.c
allwinner-h3-dramc.c
allwinner-h3-sysctrl.c
allwinner-sid.c
applesmc.c acpi: applesmc: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML 2022-06-09 19:32:49 -04:00
arm11scu.c
arm_integrator_debug.c
arm_l2x0.c
arm_sysctl.c
armsse-cpu-pwrctrl.c
armsse-cpuid.c
armsse-mhu.c
armv7m_ras.c
aspeed_hace.c aspeed/hace: Accumulative mode supported 2022-06-30 09:21:13 +02:00
aspeed_i3c.c
aspeed_lpc.c
aspeed_peci.c hw/misc/aspeed: Add PECI controller 2022-06-30 09:21:14 +02:00
aspeed_sbc.c aspeed: sbc: Correct default reset values 2022-05-02 17:03:02 +02:00
aspeed_scu.c aspeed/scu: Add trace events for read ops 2022-06-30 09:21:13 +02:00
aspeed_sdmc.c
aspeed_xdma.c
auxbus.c
avr_power.c
bcm2835_cprman.c
bcm2835_mbox.c
bcm2835_mphi.c
bcm2835_powermgt.c
bcm2835_property.c
bcm2835_rng.c
bcm2835_thermal.c
cbus.c
debugexit.c
eccmemctl.c
edu.c
empty_slot.c
exynos4210_clk.c
exynos4210_pmu.c
exynos4210_rng.c
grlib_ahb_apb_pnp.c
imx6_ccm.c
imx6_src.c Use g_new() & friends where that makes obvious sense 2022-03-21 15:44:44 +01:00
imx6ul_ccm.c
imx7_ccm.c
imx7_gpr.c
imx7_snvs.c
imx25_ccm.c
imx31_ccm.c
imx_ccm.c
imx_rngc.c
iotkit-secctl.c
iotkit-sysctl.c
iotkit-sysinfo.c
ivshmem.c Use g_unix_set_fd_nonblocking() 2022-05-03 15:17:30 +04:00
Kconfig lasi: move from hw/hppa to hw/misc 2022-05-08 18:52:37 +01:00
lasi.c lasi: move from hw/hppa to hw/misc 2022-05-08 18:52:37 +01:00
led.c
mac_via.c
mchp_pfsoc_dmc.c
mchp_pfsoc_ioscb.c
mchp_pfsoc_sysreg.c
meson.build hw/misc/aspeed: Add PECI controller 2022-06-30 09:21:14 +02:00
mips_cmgcr.c
mips_cpc.c
mips_itu.c compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
mos6522.c
mps2-fpgaio.c
mps2-scc.c
msf2-sysreg.c
mst_fpga.c
npcm7xx_clk.c hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init() 2022-03-18 10:55:15 +00:00
npcm7xx_gcr.c
npcm7xx_mft.c
npcm7xx_pwm.c
npcm7xx_rng.c
nrf51_rng.c
omap_clk.c
omap_gpmc.c
omap_l4.c
omap_sdrc.c
omap_tap.c
pc-testdev.c
pca9552.c
pci-testdev.c
pvpanic-isa.c acpi: pvpanic-isa: use AcpiDevAmlIfClass:build_dev_aml to provide device's AML 2022-06-09 19:32:49 -04:00
pvpanic-pci.c
pvpanic.c
sbsa_ec.c Remove qemu-common.h include from most units 2022-04-06 14:31:55 +02:00
sga.c
sifive_e_prci.c
sifive_test.c
sifive_u_otp.c
sifive_u_prci.c
slavio_misc.c
stm32f2xx_syscfg.c
stm32f4xx_exti.c
stm32f4xx_syscfg.c
trace-events hw/misc/aspeed: Add PECI controller 2022-06-30 09:21:14 +02:00
trace.h
tz-mpc.c
tz-msc.c
tz-ppc.c
unimp.c
virt_ctrl.c
vmcoreinfo.c
xlnx-versal-crl.c hw/misc: Add a model of the Xilinx Versal CRL 2022-04-21 11:37:03 +01:00
xlnx-versal-pmc-iou-slcr.c
xlnx-versal-xramc.c
xlnx-zynqmp-apu-ctrl.c hw/misc: Add a model of the Xilinx ZynqMP APU Control 2022-03-18 11:31:20 +00:00
xlnx-zynqmp-crf.c hw/misc: Add a model of the Xilinx ZynqMP CRF 2022-03-18 11:31:20 +00:00
zynq_slcr.c