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qemu-e2k/hw/riscv
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Bin Meng 898dc008e8 hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card 
Microchip PolarFire SoC integrates one Cadence SDHCI controller.
On the Icicle Kit board, one eMMC chip and an external SD card
connect to this controller depending on different configuration.

As QEMU does not support eMMC yet, we just emulate the SD card
configuration. To test this, the Hart Software Services (HSS)
should choose the SD card configuration:

$ cp boards/icicle-kit-es/def_config.sdcard .config
$ make BOARD=icicle-kit-es

The SD card image can be built from the Yocto BSP at:
https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp

Note the generated SD card image should be resized before use:
$ qemu-img resize /path/to/sdcard.img 4G

Launch QEMU with the following command:
$ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
 		2020-09-09 15:54:18 -07:00
..
Kconfig hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card 2020-09-09 15:54:18 -07:00
boot.c RISC-V: Support 64 bit start address 2020-07-13 17:25:37 -07:00
meson.build hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board 2020-09-09 15:54:18 -07:00
microchip_pfsoc.c hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card 2020-09-09 15:54:18 -07:00
numa.c hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.c target/riscv: cpu: Set reset vector based on the configured property value 2020-09-09 15:54:18 -07:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
riscv_htif.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
sifive_clint.c hw/riscv: Allow creating multiple instances of CLINT 2020-08-25 09:11:35 -07:00
sifive_e.c target/riscv: cpu: Set reset vector based on the configured property value 2020-09-09 15:54:18 -07:00
sifive_e_prci.c sysbus: Convert to sysbus_realize() etc. with Coccinelle 2020-06-15 22:05:28 +02:00
sifive_gpio.c hw/riscv: sifive_gpio: Do not blindly trigger output IRQs 2020-06-19 08:25:27 -07:00
sifive_plic.c hw/riscv: Allow creating multiple instances of PLIC 2020-08-25 09:11:35 -07:00
sifive_test.c riscv: sifive_test: Allow 16-bit writes to memory region 2020-09-09 15:54:18 -07:00
sifive_u.c target/riscv: cpu: Set reset vector based on the configured property value 2020-09-09 15:54:18 -07:00
sifive_u_otp.c qdev: set properties with device_class_set_props() 2020-01-24 20:59:15 +01:00
sifive_u_prci.c riscv: sifive: Implement PRCI model for FU540 2019-09-17 08:42:47 -07:00
sifive_uart.c chardev: Use QEMUChrEvent enum in IOEventHandler typedef 2020-01-08 11:15:35 +01:00
spike.c hw/riscv: spike: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00
trace-events SiFive RISC-V GPIO Device 2019-05-24 11:58:30 -07:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
virt.c hw/riscv: virt: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00