qemu-e2k/target/riscv
Yifei Jiang 9997cc1e19 target/riscv: Implement kvm_arch_put_registers
Put GPR CSR and FP registers to kvm by KVM_SET_ONE_REG ioctl

Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Mingwang Li <limingwang@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Message-id: 20220112081329.1835-6-jiangyifei@huawei.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-21 15:52:56 +10:00
..
insn_trans target/riscv: modification of the trans_csrxx for 128-bit support 2022-01-08 15:46:10 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: Add rev8 instruction, removing grev/grevi 2021-10-07 08:41:33 +10:00
cpu_bits.h target/riscv: actual functions to realize crs 128-bit insns 2022-01-08 15:46:10 +10:00
cpu_helper.c target/riscv: Implement the stval/mtval illegal instruction 2022-01-08 15:46:10 +10:00
cpu_user.h
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: setup everything for rv64 to support rv128 execution 2022-01-08 15:46:10 +10:00
cpu.h target/riscv: Implement the stval/mtval illegal instruction 2022-01-08 15:46:10 +10:00
csr.c target/riscv: actual functions to realize crs 128-bit insns 2022-01-08 15:46:10 +10:00
fpu_helper.c target/riscv: add "set round to odd" rounding mode helper function 2021-12-20 14:53:31 +10:00
gdbstub.c target/riscv: setup everything for rv64 to support rv128 execution 2022-01-08 15:46:10 +10:00
helper.h target/riscv: helper functions to wrap calls to 128-bit csr insns 2022-01-08 15:46:10 +10:00
insn16.decode target/riscv: accessors to registers upper part and 128-bit load/store 2022-01-08 15:46:10 +10:00
insn32.decode target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
instmap.h
internals.h target/riscv: add "set round to odd" rounding mode helper function 2021-12-20 14:53:31 +10:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm.c target/riscv: Implement kvm_arch_put_registers 2022-01-21 15:52:56 +10:00
m128_helper.c target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
machine.c target/riscv: adding high part of some csrs 2022-01-08 15:46:10 +10:00
meson.build target/riscv: Add target/riscv/kvm.c to place the public kvm interface 2022-01-21 15:52:56 +10:00
monitor.c target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl 2021-10-22 07:47:51 +10:00
op_helper.c target/riscv: helper functions to wrap calls to 128-bit csr insns 2022-01-08 15:46:10 +10:00
pmp.c target/riscv: pmp: Fix some typos 2021-07-15 08:56:00 +10:00
pmp.h target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h
translate.c target/riscv: Implement the stval/mtval illegal instruction 2022-01-08 15:46:10 +10:00
vector_helper.c target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm 2021-12-20 14:53:31 +10:00