Daniel Henrique Barboza b955fd1a00 target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[] ... Create a new riscv_cpu_experimental_exts[] to store the non-ratified extensions properties. Once they are ratified we'll move them back to riscv_cpu_extensions[]. riscv_cpu_add_user_properties() and riscv_cpu_add_kvm_properties() are changed to keep adding non-ratified properties to users. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230912132423.268494-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-10-12 11:33:50 +10:00
..
insn_trans	tcg: Rename cpu_env to tcg_env	2023-10-03 08:01:02 -07:00
arch_dump.c	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Update CSR bits name for svadu extension	2023-09-11 11:45:55 +10:00
cpu_cfg.h	target/riscv: Add Zihintntl extension ISA string to DTS	2023-09-11 11:45:55 +10:00
cpu_helper.c	target/riscv: Update CSR bits name for svadu extension	2023-09-11 11:45:55 +10:00
cpu_user.h
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu-param.h	target/riscv: Remove NB_MMU_MODES define	2023-03-13 06:44:37 -07:00
cpu-qom.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
cpu.c	target/riscv/cpu.c: split non-ratified exts from riscv_cpu_extensions[]	2023-10-12 11:33:50 +10:00
cpu.h	accel/tcg: Move CPUNegativeOffsetState into CPUState	2023-10-03 08:01:02 -07:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv: don't read CSR in riscv_csrrw_do64	2023-09-11 11:45:55 +10:00
debug.c	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
debug.h	target/riscv: Allocate itrigger timers only once	2023-09-11 11:45:55 +10:00
fpu_helper.c	riscv: Add support for the Zfa extension	2023-07-10 22:29:20 +10:00
gdbstub.c	target/riscv: Use PRV_RESERVED instead of PRV_H	2023-05-05 10:49:50 +10:00
helper.h	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
insn16.decode	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00
insn32.decode	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
instmap.h
internals.h	target/riscv: Introduce mmuidx_2stage	2023-05-05 10:49:50 +10:00
Kconfig
kvm_riscv.h	target/riscv/cpu.c: split kvm prop handling to its own helper	2023-10-12 11:31:38 +10:00
kvm-stub.c
kvm.c	hw/intc/riscv_aplic.c fix non-KVM --enable-debug build	2023-09-11 11:45:55 +10:00
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c	target/riscv: Restrict KVM-specific fields from ArchCPU	2023-06-28 14:27:59 +02:00
meson.build	meson: Rename target_softmmu_arch -> target_system_arch	2023-10-07 19:03:07 +02:00
monitor.c	riscv: spelling fixes	2023-09-08 13:08:52 +03:00
op_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
pmp.c	target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes	2023-09-11 11:45:55 +10:00
pmp.h	target/riscv: Change the return type of pmp_hart_has_privs() to bool	2023-06-13 17:09:13 +10:00
pmu.c	target/riscv/pmu: Restrict 'qemu/log.h' include to source	2023-08-31 19:47:43 +02:00
pmu.h	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
riscv-qmp-cmds.c	target/riscv: add TYPE_RISCV_DYNAMIC_CPU	2023-05-05 10:49:50 +10:00
sbi_ecall_interface.h	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
time_helper.c	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events
trace.h
translate.c	accel/tcg: Replace CPUState.env_ptr with cpu_env()	2023-10-04 11:03:54 -07:00
vcrypto_helper.c	target/riscv: Add Zvksed ISA extension support	2023-09-11 11:45:55 +10:00
vector_helper.c	tcg: Correct invalid mentions of 'softmmu' by 'system-mode'	2023-10-07 19:02:33 +02:00
vector_internals.c	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:54 +10:00
vector_internals.h	target/riscv: Refactor some of the generic vector functionality	2023-09-11 11:45:55 +10:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00