Jean-Christophe DUBOIS ec46eaa83a i.MX: Add i.MX6 SOC implementation. ... For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2016-05-12 13:22:29 +01:00
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allwinner-a10.h
arm.h	arm: boot: Support big-endian elfs	2016-03-04 11:30:21 +00:00
ast2400.h	hw/arm: Add ASPEED AST2400 SoC model	2016-03-16 17:42:18 +00:00
bcm2835_peripherals.h	bcm2835_dma: add emulation of Raspberry Pi DMA controller	2016-03-16 17:42:18 +00:00
bcm2836.h	bcm2836: add bcm2836 SoC device	2016-02-03 15:00:46 +00:00
digic.h
exynos4210.h
fdt.h
fsl-imx6.h	i.MX: Add i.MX6 SOC implementation.	2016-05-12 13:22:29 +01:00
fsl-imx25.h	i.MX: Add an i.MX25 specific CCM class/instance	2015-12-17 13:37:16 +00:00
fsl-imx31.h
linux-boot-if.h
omap.h
primecell.h
pxa.h
raspi_platform.h	bcm2835_peripherals: add rollup device for bcm2835 peripherals	2016-02-03 15:00:45 +00:00
sharpsl.h
soc_dma.h
stm32f205_soc.h
sysbus-fdt.h
virt-acpi-build.h	arm: virt-acpi: each MADT.GICC entry as enabled unconditionally	2016-02-03 13:46:34 +00:00
virt.h	hw/arm/virt: Provide a secure-only RAM if booting in Secure mode	2016-03-04 11:30:17 +00:00
xlnx-zynqmp.h	xlnx-zynqmp: Connect the SPI devices	2016-01-21 14:15:03 +00:00