qemu-e2k/target/riscv
Georg Kotheimer 9a27f69bd6 target/riscv: Prevent lost illegal instruction exceptions
When decode_insn16() fails, we fall back to decode_RV32_64C() for
further compressed instruction decoding. However, prior to this change,
we did not raise an illegal instruction exception, if decode_RV32_64C()
fails to decode the instruction. This means that we skipped illegal
compressed instructions instead of raising an illegal instruction
exception.

Instead of patching decode_RV32_64C(), we can just remove it,
as it is dead code since f330433b36 anyway.

Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210322121609.3097928-1-georg.kotheimer@kernkonzept.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-22 21:54:40 -04:00
..
insn_trans riscv: Add semihosting support 2021-01-18 10:05:06 +00:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
cpu_bits.h target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
cpu_helper.c target/riscv: Add proper two-stage lookup exception detection 2021-03-22 21:54:40 -04:00
cpu_user.h
cpu-param.h target/riscv: Add a virtualised MMU Mode 2020-11-09 15:08:45 -08:00
cpu.c target/riscv: Add proper two-stage lookup exception detection 2021-03-22 21:54:40 -04:00
cpu.h target/riscv: Add proper two-stage lookup exception detection 2021-03-22 21:54:40 -04:00
csr.c target/riscv: Fix read and write accesses to vsip and vsie 2021-03-22 21:54:40 -04:00
fpu_helper.c target/riscv: fpu_helper: Match function defs in HELPER macros 2020-12-17 21:56:44 -08:00
gdbstub.c target/riscv: Generate the GDB XML file for CSR registers dynamically 2021-01-16 10:57:21 -08:00
helper.h target/riscv: fpu_helper: Match function defs in HELPER macros 2020-12-17 21:56:44 -08:00
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h
internals.h target/riscv: Add basic vmstate description of CPU 2020-11-03 07:17:23 -08:00
machine.c target/riscv: Add V extension state description 2020-11-03 07:17:23 -08:00
meson.build target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
monitor.c hmp: Pass monitor to mon_get_cpu_env() 2020-11-13 12:45:51 +00:00
op_helper.c target/riscv/pmp: Raise exception if no PMP entry is configured 2021-01-16 10:57:21 -08:00
pmp.c target/riscv: flush TLB pages if PMP permission has been changed 2021-03-22 21:54:40 -04:00
pmp.h target/riscv: propagate PMP permission to TLB page 2021-03-22 21:54:40 -04:00
trace-events trace-events: Fix attribution of trace points to source 2020-09-09 17:17:58 +01:00
trace.h
translate.c target/riscv: Prevent lost illegal instruction exceptions 2021-03-22 21:54:40 -04:00
vector_helper.c softfloat: Implement the full set of comparisons for float16 2020-08-28 10:48:07 -07:00