1999-04-16 03:35:26 +02:00
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// -*- C -*-
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//
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// <insn> ::=
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// <insn-word> { "+" <insn-word> }
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// ":" <format-name>
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// ":" <filter-flags>
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// ":" <options>
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// ":" <name>
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// <nl>
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// { <insn-model> }
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// { <insn-mnemonic> }
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// <code-block>
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//
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// IGEN config - mips16
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// :option:16::insn-bit-size:16
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// :option:16::hi-bit-nr:15
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:option:16::insn-specifying-widths:true
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:option:16::gen-delayed-branch:false
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// IGEN config - mips32/64..
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// :option:32::insn-bit-size:32
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// :option:32::hi-bit-nr:31
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:option:32::insn-specifying-widths:true
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:option:32::gen-delayed-branch:false
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// Generate separate simulators for each target
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// :option:::multi-sim:true
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2002-02-12 00:35:07 +01:00
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// Models known by this simulator are defined below.
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2002-02-19 09:10:44 +01:00
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//
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// When placing models in the instruction descriptions, please place
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// them one per line, in the order given here.
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2002-02-12 00:35:07 +01:00
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// MIPS ISAs:
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//
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// Instructions and related functions for these models are included in
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// this file.
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1999-04-16 03:35:26 +02:00
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:model:::mipsI:mips3000:
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:model:::mipsII:mips6000:
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:model:::mipsIII:mips4000:
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:model:::mipsIV:mips8000:
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2002-02-27 22:52:52 +01:00
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:model:::mipsV:mipsisaV:
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2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
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:model:::mips32:mipsisa32:
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2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
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:model:::mips32r2:mipsisa32r2:
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2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
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:model:::mips64:mipsisa64:
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2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
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:model:::mips64r2:mipsisa64r2:
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2002-02-12 00:35:07 +01:00
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// Vendor ISAs:
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//
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// Standard MIPS ISA instructions used for these models are listed here,
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// as are functions needed by those standard instructions. Instructions
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// which are model-dependent and which are not in the standard MIPS ISAs
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// (or which pre-date or use different encodings than the standard
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// instructions) are (for the most part) in separate .igen files.
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:model:::vr4100:mips4100: // vr.igen
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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:model:::vr4120:mips4120:
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1999-04-16 03:35:26 +02:00
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:model:::vr5000:mips5000:
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2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
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:model:::vr5400:mips5400:
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:model:::vr5500:mips5500:
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2002-02-12 00:35:07 +01:00
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:model:::r3900:mips3900: // tx.igen
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1999-04-16 03:35:26 +02:00
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2002-02-12 00:35:07 +01:00
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// MIPS Application Specific Extensions (ASEs)
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//
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// Instructions for the ASEs are in separate .igen files.
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2002-06-02 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips.igen (mdmx): New (pseudo-)model.
* mdmx.c, mdmx.igen: New files.
* Makefile.in (SIM_OBJS): Add mdmx.o.
* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
New typedefs.
(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
(qh_fmtsel): New macros.
(_sim_cpu): New member "acc".
(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
2002-06-02 09:39:26 +02:00
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// ASEs add instructions on to a base ISA.
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2002-02-12 00:35:07 +01:00
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:model:::mips16:mips16: // m16.igen (and m16.dc)
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2005-06-16 17:15:49 +02:00
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:model:::mips16e:mips16e: // m16e.igen
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2002-06-14 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
2002-06-14 20:49:09 +02:00
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:model:::mips3d:mips3d: // mips3d.igen
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2002-06-02 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips.igen (mdmx): New (pseudo-)model.
* mdmx.c, mdmx.igen: New files.
* Makefile.in (SIM_OBJS): Add mdmx.o.
* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
New typedefs.
(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
(qh_fmtsel): New macros.
(_sim_cpu): New member "acc".
(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
2002-06-02 09:39:26 +02:00
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:model:::mdmx:mdmx: // mdmx.igen
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* Makefile.in (SIM_OBJS): Add dsp.o.
(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
2005-12-15 00:07:56 +01:00
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:model:::dsp:dsp: // dsp.igen
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[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
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:model:::dsp2:dsp2: // dsp2.igen
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2006-08-29 14:45:26 +02:00
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:model:::smartmips:smartmips: // smartmips.igen
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1999-04-16 03:35:26 +02:00
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2002-06-03 23:00:29 +02:00
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// Vendor Extensions
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//
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// Instructions specific to these extensions are in separate .igen files.
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// Extensions add instructions on to a base ISA.
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:model:::sb1:sb1: // sb1.igen
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1999-04-16 03:35:26 +02:00
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// Pseudo instructions known by IGEN
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:internal::::illegal:
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{
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SignalException (ReservedInstruction, 0);
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}
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// Pseudo instructions known by interp.c
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// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
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000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
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"rsvd <OP>"
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{
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SignalException (ReservedInstruction, instruction_0);
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}
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// Helper:
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//
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// Simulate a 32 bit delayslot instruction
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//
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|
|
|
|
|
|
:function:::address_word:delayslot32:address_word target
|
|
|
|
|
{
|
|
|
|
|
instruction_word delay_insn;
|
|
|
|
|
sim_events_slip (SD, 1);
|
|
|
|
|
DSPC = CIA;
|
|
|
|
|
CIA = CIA + 4; /* NOTE not mips16 */
|
|
|
|
|
STATE |= simDELAYSLOT;
|
|
|
|
|
delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
|
1999-09-09 02:02:17 +02:00
|
|
|
|
ENGINE_ISSUE_PREFIX_HOOK();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
idecode_issue (CPU_, delay_insn, (CIA));
|
|
|
|
|
STATE &= ~simDELAYSLOT;
|
|
|
|
|
return target;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::address_word:nullify_next_insn32:
|
|
|
|
|
{
|
|
|
|
|
sim_events_slip (SD, 1);
|
|
|
|
|
dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
|
|
|
|
|
return CIA + 8;
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
|
|
|
|
|
// Helper:
|
|
|
|
|
//
|
|
|
|
|
// Calculate an effective address given a base and an offset.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
:function:::address_word:loadstore_ea:address_word base, address_word offset
|
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
return base + offset;
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
:function:::address_word:loadstore_ea:address_word base, address_word offset
|
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
#if 0 /* XXX FIXME: enable this only after some additional testing. */
|
|
|
|
|
/* If in user mode and UX is not set, use 32-bit compatibility effective
|
|
|
|
|
address computations as defined in the MIPS64 Architecture for
|
|
|
|
|
Programmers Volume III, Revision 0.95, section 4.9. */
|
|
|
|
|
if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
|
|
|
|
|
== (ksu_user << status_KSU_shift))
|
|
|
|
|
return (address_word)((signed32)base + (signed32)offset);
|
|
|
|
|
#endif
|
|
|
|
|
return base + offset;
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
// Helper:
|
|
|
|
|
//
|
|
|
|
|
// Check that a 32-bit register value is properly sign-extended.
|
|
|
|
|
// (See NotWordValue in ISA spec.)
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
:function:::int:not_word_value:unsigned_word value
|
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
{
|
2007-02-19 18:31:08 +01:00
|
|
|
|
#if WITH_TARGET_WORD_BITSIZE == 64
|
|
|
|
|
return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
|
|
|
|
|
#else
|
|
|
|
|
return 0;
|
|
|
|
|
#endif
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// Helper:
|
|
|
|
|
//
|
|
|
|
|
// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent
|
|
|
|
|
// theoretically portable code which invokes non-portable behaviour from
|
|
|
|
|
// running with no indication of the portability issue.
|
|
|
|
|
// (See definition of UNPREDICTABLE in ISA spec.)
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
:function:::void:unpredictable:
|
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::void:unpredictable:
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
{
|
|
|
|
|
unpredictable_action (CPU, CIA);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-01-20 08:06:14 +01:00
|
|
|
|
// Helpers:
|
2002-03-04 04:19:49 +01:00
|
|
|
|
//
|
1999-04-16 03:35:26 +02:00
|
|
|
|
// Check that an access to a HI/LO register meets timing requirements
|
|
|
|
|
//
|
2004-01-20 08:06:14 +01:00
|
|
|
|
// In all MIPS ISAs,
|
1999-04-16 03:35:26 +02:00
|
|
|
|
//
|
2004-01-20 08:06:14 +01:00
|
|
|
|
// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
|
|
|
|
|
// makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
|
|
|
|
|
//
|
|
|
|
|
// The following restrictions exist for MIPS I - MIPS III:
|
|
|
|
|
//
|
|
|
|
|
// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
|
|
|
|
|
// in between makes MF UNPREDICTABLE. (2)
|
|
|
|
|
//
|
|
|
|
|
// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
|
|
|
|
|
// in between makes MF UNPREDICTABLE. (3)
|
|
|
|
|
//
|
|
|
|
|
// On the r3900, restriction (2) is not present, and restriction (3) is not
|
|
|
|
|
// present for multiplication.
|
|
|
|
|
//
|
2004-03-29 23:56:02 +02:00
|
|
|
|
// Unfortunately, there seems to be some confusion about whether the last
|
|
|
|
|
// two restrictions should apply to "MIPS IV" as well. One edition of
|
|
|
|
|
// the MIPS IV ISA says they do, but references in later ISA documents
|
|
|
|
|
// suggest they don't.
|
|
|
|
|
//
|
|
|
|
|
// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
|
|
|
|
|
// these restrictions, while others, like the VR5500, don't. To accomodate
|
|
|
|
|
// such differences, the MIPS IV and MIPS V version of these helper functions
|
|
|
|
|
// use auxillary routines to determine whether the restriction applies.
|
2004-01-20 08:06:14 +01:00
|
|
|
|
|
|
|
|
|
// check_mf_cycles:
|
|
|
|
|
//
|
|
|
|
|
// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
|
|
|
|
|
// to check for restrictions (2) and (3) above.
|
1999-04-16 03:35:26 +02:00
|
|
|
|
//
|
|
|
|
|
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
|
|
|
|
|
{
|
|
|
|
|
if (history->mf.timestamp + 3 > time)
|
|
|
|
|
{
|
|
|
|
|
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
|
|
|
|
|
itable[MY_INDEX].name,
|
|
|
|
|
new, (long) CIA,
|
2002-03-04 04:19:49 +01:00
|
|
|
|
(long) history->mf.cia);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
2004-01-20 08:06:14 +01:00
|
|
|
|
|
|
|
|
|
// check_mt_hilo:
|
|
|
|
|
//
|
|
|
|
|
// Check for restriction (2) above (for ISAs/processors that have it),
|
|
|
|
|
// and record timestamps for restriction (1) above.
|
|
|
|
|
//
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::int:check_mt_hilo:hilo_history *history
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
int ok = check_mf_cycles (SD_, history, time, "MT");
|
|
|
|
|
history->mt.timestamp = time;
|
|
|
|
|
history->mt.cia = CIA;
|
|
|
|
|
return ok;
|
|
|
|
|
}
|
|
|
|
|
|
2004-03-29 23:56:02 +02:00
|
|
|
|
:function:::int:check_mt_hilo:hilo_history *history
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
|
|
|
|
|
|| check_mf_cycles (SD_, history, time, "MT"));
|
|
|
|
|
history->mt.timestamp = time;
|
|
|
|
|
history->mt.cia = CIA;
|
|
|
|
|
return ok;
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::int:check_mt_hilo:hilo_history *history
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
history->mt.timestamp = time;
|
|
|
|
|
history->mt.cia = CIA;
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-01-20 08:06:14 +01:00
|
|
|
|
// check_mf_hilo:
|
|
|
|
|
//
|
|
|
|
|
// Check for restriction (1) above, and record timestamps for
|
|
|
|
|
// restriction (2) and (3) above.
|
|
|
|
|
//
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
int ok = 1;
|
|
|
|
|
if (peer != NULL
|
|
|
|
|
&& peer->mt.timestamp > history->op.timestamp
|
|
|
|
|
&& history->mt.timestamp < history->op.timestamp
|
|
|
|
|
&& ! (history->mf.timestamp > history->op.timestamp
|
|
|
|
|
&& history->mf.timestamp < peer->mt.timestamp)
|
|
|
|
|
&& ! (peer->mf.timestamp > history->op.timestamp
|
|
|
|
|
&& peer->mf.timestamp < peer->mt.timestamp))
|
|
|
|
|
{
|
|
|
|
|
/* The peer has been written to since the last OP yet we have
|
|
|
|
|
not */
|
|
|
|
|
sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
|
|
|
|
|
itable[MY_INDEX].name,
|
|
|
|
|
(long) CIA,
|
|
|
|
|
(long) history->op.cia,
|
2002-03-04 04:19:49 +01:00
|
|
|
|
(long) peer->mt.cia);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
ok = 0;
|
|
|
|
|
}
|
|
|
|
|
history->mf.timestamp = time;
|
|
|
|
|
history->mf.cia = CIA;
|
|
|
|
|
return ok;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2004-01-20 08:06:14 +01:00
|
|
|
|
// check_mult_hilo:
|
|
|
|
|
//
|
|
|
|
|
// Check for restriction (3) above (for ISAs/processors that have it)
|
|
|
|
|
// for MULT ops, and record timestamps for restriction (1) above.
|
|
|
|
|
//
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
int ok = (check_mf_cycles (SD_, hi, time, "OP")
|
|
|
|
|
&& check_mf_cycles (SD_, lo, time, "OP"));
|
|
|
|
|
hi->op.timestamp = time;
|
|
|
|
|
lo->op.timestamp = time;
|
|
|
|
|
hi->op.cia = CIA;
|
|
|
|
|
lo->op.cia = CIA;
|
|
|
|
|
return ok;
|
|
|
|
|
}
|
|
|
|
|
|
2004-03-29 23:56:02 +02:00
|
|
|
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
|
|
|
|
|
|| (check_mf_cycles (SD_, hi, time, "OP")
|
|
|
|
|
&& check_mf_cycles (SD_, lo, time, "OP")));
|
|
|
|
|
hi->op.timestamp = time;
|
|
|
|
|
lo->op.timestamp = time;
|
|
|
|
|
hi->op.cia = CIA;
|
|
|
|
|
lo->op.cia = CIA;
|
|
|
|
|
return ok;
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
/* FIXME: could record the fact that a stall occured if we want */
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
hi->op.timestamp = time;
|
|
|
|
|
lo->op.timestamp = time;
|
|
|
|
|
hi->op.cia = CIA;
|
|
|
|
|
lo->op.cia = CIA;
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-01-20 08:06:14 +01:00
|
|
|
|
// check_div_hilo:
|
|
|
|
|
//
|
|
|
|
|
// Check for restriction (3) above (for ISAs/processors that have it)
|
|
|
|
|
// for DIV ops, and record timestamps for restriction (1) above.
|
|
|
|
|
//
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
int ok = (check_mf_cycles (SD_, hi, time, "OP")
|
|
|
|
|
&& check_mf_cycles (SD_, lo, time, "OP"));
|
|
|
|
|
hi->op.timestamp = time;
|
|
|
|
|
lo->op.timestamp = time;
|
|
|
|
|
hi->op.cia = CIA;
|
|
|
|
|
lo->op.cia = CIA;
|
|
|
|
|
return ok;
|
|
|
|
|
}
|
|
|
|
|
|
2004-03-29 23:56:02 +02:00
|
|
|
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
|
|
|
|
|
|| (check_mf_cycles (SD_, hi, time, "OP")
|
|
|
|
|
&& check_mf_cycles (SD_, lo, time, "OP")));
|
|
|
|
|
hi->op.timestamp = time;
|
|
|
|
|
lo->op.timestamp = time;
|
|
|
|
|
hi->op.cia = CIA;
|
|
|
|
|
lo->op.cia = CIA;
|
|
|
|
|
return ok;
|
|
|
|
|
}
|
|
|
|
|
|
2004-01-20 08:06:14 +01:00
|
|
|
|
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2004-01-20 08:06:14 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2004-01-20 08:06:14 +01:00
|
|
|
|
{
|
|
|
|
|
signed64 time = sim_events_time (SD);
|
|
|
|
|
hi->op.timestamp = time;
|
|
|
|
|
lo->op.timestamp = time;
|
|
|
|
|
hi->op.cia = CIA;
|
|
|
|
|
lo->op.cia = CIA;
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
// Helper:
|
2002-03-04 04:19:49 +01:00
|
|
|
|
//
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
// Check that the 64-bit instruction can currently be used, and signal
|
2002-03-05 08:34:01 +01:00
|
|
|
|
// a ReservedInstruction exception if not.
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
:function:::void:check_u64:instruction_word insn
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*vr5400:
|
|
|
|
|
*vr5500:
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
{
|
|
|
|
|
// The check should be similar to mips64 for any with PX/UX bit equivalents.
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
:function:::void:check_u64:instruction_word insn
|
2005-06-16 17:15:49 +02:00
|
|
|
|
*mips16e:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
#if 0 /* XXX FIXME: enable this only after some additional testing. */
|
|
|
|
|
if (UserMode && (SR & (status_UX|status_PX)) == 0)
|
|
|
|
|
SignalException (ReservedInstruction, insn);
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
2002-02-12 00:35:07 +01:00
|
|
|
|
// MIPS Architecture:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
//
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
|
1999-04-16 03:35:26 +02:00
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
|
|
|
|
|
"add r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
{
|
|
|
|
|
ALU32_BEGIN (GPR[RS]);
|
|
|
|
|
ALU32_ADD (GPR[RT]);
|
2002-02-11 23:49:45 +01:00
|
|
|
|
ALU32_END (GPR[RD]); /* This checks for overflow. */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
|
2002-02-11 03:19:38 +01:00
|
|
|
|
"addi r<RT>, r<RS>, <IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
|
|
|
|
|
{
|
|
|
|
|
ALU32_BEGIN (GPR[RS]);
|
|
|
|
|
ALU32_ADD (EXTEND16 (IMMEDIATE));
|
2002-02-11 23:49:45 +01:00
|
|
|
|
ALU32_END (GPR[RT]); /* This checks for overflow. */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_addiu:int rs, int rt, unsigned16 immediate
|
|
|
|
|
{
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rs]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
|
|
|
|
GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rt]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
|
|
|
|
|
"addiu r<RT>, r<RS>, <IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_addiu (SD_, RS, RT, IMMEDIATE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_addu:int rs, int rt, int rd
|
|
|
|
|
{
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
|
|
|
|
|
"addu r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_addu (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_and:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = GPR[rs] & GPR[rt];
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
|
|
|
|
|
"and r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_and (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
|
2002-03-08 01:37:14 +01:00
|
|
|
|
"andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
|
|
|
|
|
GPR[RT] = GPR[RS] & IMMEDIATE;
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
|
|
|
|
|
"beq r<RS>, r<RT>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
|
|
|
|
|
"beql r<RS>, r<RT>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
|
|
|
|
|
"bgez r<RS>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] >= 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
|
|
|
|
|
"bgezal r<RS>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (RS == 31)
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
RA = (CIA + 8);
|
|
|
|
|
if ((signed_word) GPR[RS] >= 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
|
|
|
|
|
"bgezall r<RS>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (RS == 31)
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
RA = (CIA + 8);
|
|
|
|
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
|
|
|
|
executed */
|
|
|
|
|
if ((signed_word) GPR[RS] >= 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
|
|
|
|
|
"bgezl r<RS>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] >= 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
|
|
|
|
|
"bgtz r<RS>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] > 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
|
|
|
|
|
"bgtzl r<RS>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
|
|
|
|
executed */
|
|
|
|
|
if ((signed_word) GPR[RS] > 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
|
|
|
|
|
"blez r<RS>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
|
|
|
|
executed */
|
|
|
|
|
if ((signed_word) GPR[RS] <= 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
|
|
|
|
|
"bgezl r<RS>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] <= 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
|
|
|
|
|
"bltz r<RS>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] < 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
|
|
|
|
|
"bltzal r<RS>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (RS == 31)
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
RA = (CIA + 8);
|
|
|
|
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
|
|
|
|
executed */
|
|
|
|
|
if ((signed_word) GPR[RS] < 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
|
|
|
|
|
"bltzall r<RS>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (RS == 31)
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
RA = (CIA + 8);
|
|
|
|
|
if ((signed_word) GPR[RS] < 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
|
|
|
|
|
"bltzl r<RS>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
/* NOTE: The branch occurs AFTER the next instruction has been
|
|
|
|
|
executed */
|
|
|
|
|
if ((signed_word) GPR[RS] < 0)
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
|
|
|
|
|
"bne r<RS>, r<RT>, <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
|
|
|
|
|
"bnel r<RS>, r<RT>, <OFFSET>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET) << 2;
|
|
|
|
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (NIA + offset);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,20.CODE,001101:SPECIAL:32::BREAK
|
2002-03-08 01:37:14 +01:00
|
|
|
|
"break %#lx<CODE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
/* Check for some break instruction which are reserved for use by the simulator. */
|
|
|
|
|
unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
|
|
|
|
|
if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
|
|
|
|
|
break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
|
|
|
|
|
{
|
|
|
|
|
sim_engine_halt (SD, CPU, NULL, cia,
|
|
|
|
|
sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
|
|
|
|
|
}
|
|
|
|
|
else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) ||
|
|
|
|
|
break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
|
|
|
|
|
{
|
|
|
|
|
if (STATE & simDELAYSLOT)
|
|
|
|
|
PC = cia - 4; /* reference the branch instruction */
|
|
|
|
|
else
|
|
|
|
|
PC = cia;
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (BreakPoint, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
else
|
|
|
|
|
{
|
2002-03-04 04:19:49 +01:00
|
|
|
|
/* If we get this far, we're not an instruction reserved by the sim. Raise
|
1999-04-16 03:35:26 +02:00
|
|
|
|
the exception. */
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (BreakPoint, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
|
|
|
|
|
"clo r<RD>, r<RS>"
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
unsigned32 temp = GPR[RS];
|
|
|
|
|
unsigned32 i, mask;
|
|
|
|
|
if (RT != RD)
|
2002-04-25 07:37:03 +02:00
|
|
|
|
Unpredictable ();
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]))
|
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
|
|
|
|
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
|
|
|
|
|
{
|
|
|
|
|
if ((temp & mask) == 0)
|
|
|
|
|
break;
|
|
|
|
|
mask >>= 1;
|
|
|
|
|
}
|
|
|
|
|
GPR[RD] = EXTEND32 (i);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
|
|
|
|
|
"clz r<RD>, r<RS>"
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
unsigned32 temp = GPR[RS];
|
|
|
|
|
unsigned32 i, mask;
|
|
|
|
|
if (RT != RD)
|
2002-04-25 07:37:03 +02:00
|
|
|
|
Unpredictable ();
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]))
|
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
|
|
|
|
for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
|
|
|
|
|
{
|
|
|
|
|
if ((temp & mask) != 0)
|
|
|
|
|
break;
|
|
|
|
|
mask >>= 1;
|
|
|
|
|
}
|
|
|
|
|
GPR[RD] = EXTEND32 (i);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
|
|
|
|
|
"dadd r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
{
|
|
|
|
|
ALU64_BEGIN (GPR[RS]);
|
|
|
|
|
ALU64_ADD (GPR[RT]);
|
2002-02-11 23:49:45 +01:00
|
|
|
|
ALU64_END (GPR[RD]); /* This checks for overflow. */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
|
|
|
|
|
"daddi r<RT>, r<RS>, <IMMEDIATE>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
|
|
|
|
|
{
|
|
|
|
|
ALU64_BEGIN (GPR[RS]);
|
|
|
|
|
ALU64_ADD (EXTEND16 (IMMEDIATE));
|
2002-02-11 23:49:45 +01:00
|
|
|
|
ALU64_END (GPR[RT]); /* This checks for overflow. */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
|
|
|
|
GPR[rt] = GPR[rs] + EXTEND16 (immediate);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rt]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
|
2002-02-11 03:19:38 +01:00
|
|
|
|
"daddiu r<RT>, r<RS>, <IMMEDIATE>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_daddiu (SD_, RS, RT, IMMEDIATE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_daddu:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = GPR[rs] + GPR[rt];
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
|
|
|
|
|
"daddu r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_daddu (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
|
|
|
|
|
"dclo r<RD>, r<RS>"
|
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
unsigned64 temp = GPR[RS];
|
|
|
|
|
unsigned32 i;
|
|
|
|
|
unsigned64 mask;
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
if (RT != RD)
|
2002-04-25 07:37:03 +02:00
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
|
|
|
|
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
|
|
|
|
|
{
|
|
|
|
|
if ((temp & mask) == 0)
|
|
|
|
|
break;
|
|
|
|
|
mask >>= 1;
|
|
|
|
|
}
|
|
|
|
|
GPR[RD] = EXTEND32 (i);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
|
|
|
|
|
"dclz r<RD>, r<RS>"
|
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
unsigned64 temp = GPR[RS];
|
|
|
|
|
unsigned32 i;
|
|
|
|
|
unsigned64 mask;
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
if (RT != RD)
|
2002-04-25 07:37:03 +02:00
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT1 (GPR[RS]);
|
|
|
|
|
for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
|
|
|
|
|
{
|
|
|
|
|
if ((temp & mask) != 0)
|
|
|
|
|
break;
|
|
|
|
|
mask >>= 1;
|
|
|
|
|
}
|
|
|
|
|
GPR[RD] = EXTEND32 (i);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::void:do_ddiv:int rs, int rt
|
|
|
|
|
{
|
|
|
|
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
{
|
|
|
|
|
signed64 n = GPR[rs];
|
|
|
|
|
signed64 d = GPR[rt];
|
|
|
|
|
signed64 hi;
|
|
|
|
|
signed64 lo;
|
|
|
|
|
if (d == 0)
|
|
|
|
|
{
|
|
|
|
|
lo = SIGNED64 (0x8000000000000000);
|
|
|
|
|
hi = 0;
|
|
|
|
|
}
|
|
|
|
|
else if (d == -1 && n == SIGNED64 (0x8000000000000000))
|
|
|
|
|
{
|
|
|
|
|
lo = SIGNED64 (0x8000000000000000);
|
|
|
|
|
hi = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
lo = (n / d);
|
|
|
|
|
hi = (n % d);
|
|
|
|
|
}
|
|
|
|
|
HI = hi;
|
|
|
|
|
LO = lo;
|
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"ddiv r<RS>, r<RT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_ddiv (SD_, RS, RT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_ddivu:int rs, int rt
|
|
|
|
|
{
|
|
|
|
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
{
|
|
|
|
|
unsigned64 n = GPR[rs];
|
|
|
|
|
unsigned64 d = GPR[rt];
|
|
|
|
|
unsigned64 hi;
|
|
|
|
|
unsigned64 lo;
|
|
|
|
|
if (d == 0)
|
|
|
|
|
{
|
|
|
|
|
lo = SIGNED64 (0x8000000000000000);
|
|
|
|
|
hi = 0;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
lo = (n / d);
|
|
|
|
|
hi = (n % d);
|
|
|
|
|
}
|
|
|
|
|
HI = hi;
|
|
|
|
|
LO = lo;
|
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
|
|
|
|
|
"ddivu r<RS>, r<RT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_ddivu (SD_, RS, RT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::void:do_div:int rs, int rt
|
|
|
|
|
{
|
|
|
|
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
{
|
|
|
|
|
signed32 n = GPR[rs];
|
|
|
|
|
signed32 d = GPR[rt];
|
|
|
|
|
if (d == 0)
|
|
|
|
|
{
|
|
|
|
|
LO = EXTEND32 (0x80000000);
|
|
|
|
|
HI = EXTEND32 (0);
|
|
|
|
|
}
|
|
|
|
|
else if (n == SIGNED32 (0x80000000) && d == -1)
|
|
|
|
|
{
|
|
|
|
|
LO = EXTEND32 (0x80000000);
|
|
|
|
|
HI = EXTEND32 (0);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
LO = EXTEND32 (n / d);
|
|
|
|
|
HI = EXTEND32 (n % d);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"div r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_div (SD_, RS, RT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_divu:int rs, int rt
|
|
|
|
|
{
|
|
|
|
|
check_div_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
{
|
|
|
|
|
unsigned32 n = GPR[rs];
|
|
|
|
|
unsigned32 d = GPR[rt];
|
|
|
|
|
if (d == 0)
|
|
|
|
|
{
|
|
|
|
|
LO = EXTEND32 (0x80000000);
|
|
|
|
|
HI = EXTEND32 (0);
|
|
|
|
|
}
|
2002-03-02 00:51:18 +01:00
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
LO = EXTEND32 (n / d);
|
|
|
|
|
HI = EXTEND32 (n % d);
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"divu r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_divu (SD_, RS, RT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
|
|
|
|
|
{
|
|
|
|
|
unsigned64 lo;
|
|
|
|
|
unsigned64 hi;
|
|
|
|
|
unsigned64 m00;
|
|
|
|
|
unsigned64 m01;
|
|
|
|
|
unsigned64 m10;
|
|
|
|
|
unsigned64 m11;
|
|
|
|
|
unsigned64 mid;
|
|
|
|
|
int sign;
|
|
|
|
|
unsigned64 op1 = GPR[rs];
|
|
|
|
|
unsigned64 op2 = GPR[rt];
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
2002-03-04 04:19:49 +01:00
|
|
|
|
/* make signed multiply unsigned */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
sign = 0;
|
|
|
|
|
if (signed_p)
|
|
|
|
|
{
|
2003-06-18 03:12:03 +02:00
|
|
|
|
if ((signed64) op1 < 0)
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
op1 = - op1;
|
|
|
|
|
++sign;
|
|
|
|
|
}
|
2003-06-18 03:12:03 +02:00
|
|
|
|
if ((signed64) op2 < 0)
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
op2 = - op2;
|
|
|
|
|
++sign;
|
|
|
|
|
}
|
|
|
|
|
}
|
2000-05-29 21:35:50 +02:00
|
|
|
|
/* multiply out the 4 sub products */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
|
|
|
|
|
m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
|
|
|
|
|
m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
|
|
|
|
|
m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
|
|
|
|
|
/* add the products */
|
|
|
|
|
mid = ((unsigned64) VH4_8 (m00)
|
|
|
|
|
+ (unsigned64) VL4_8 (m10)
|
|
|
|
|
+ (unsigned64) VL4_8 (m01));
|
|
|
|
|
lo = U8_4 (mid, m00);
|
|
|
|
|
hi = (m11
|
|
|
|
|
+ (unsigned64) VH4_8 (mid)
|
|
|
|
|
+ (unsigned64) VH4_8 (m01)
|
|
|
|
|
+ (unsigned64) VH4_8 (m10));
|
|
|
|
|
/* fix the sign */
|
|
|
|
|
if (sign & 1)
|
|
|
|
|
{
|
|
|
|
|
lo = -lo;
|
|
|
|
|
if (lo == 0)
|
|
|
|
|
hi = -hi;
|
|
|
|
|
else
|
|
|
|
|
hi = -hi - 1;
|
|
|
|
|
}
|
|
|
|
|
/* save the result HI/LO (and a gpr) */
|
|
|
|
|
LO = lo;
|
|
|
|
|
HI = hi;
|
|
|
|
|
if (rd != 0)
|
|
|
|
|
GPR[rd] = lo;
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dmult:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
do_dmultx (SD_, rs, rt, rd, 1);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dmult r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dmult (SD_, RS, RT, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dmult r<RS>, r<RT>":RD == 0
|
|
|
|
|
"dmult r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dmult (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dmultu:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
do_dmultx (SD_, rs, rt, rd, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dmultu r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dmultu (SD_, RS, RT, 0);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dmultu r<RD>, r<RS>, r<RT>":RD == 0
|
|
|
|
|
"dmultu r<RS>, r<RT>"
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dmultu (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
|
|
|
|
|
:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
|
|
|
|
|
{
|
|
|
|
|
unsigned64 result;
|
|
|
|
|
|
|
|
|
|
y &= 63;
|
|
|
|
|
TRACE_ALU_INPUT2 (x, y);
|
|
|
|
|
result = ROTR64 (x, y);
|
|
|
|
|
TRACE_ALU_RESULT (result);
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
|
|
|
|
|
"dror r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*vr5400:
|
|
|
|
|
*vr5500:
|
|
|
|
|
{
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
|
|
|
|
|
"dror32 r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*vr5400:
|
|
|
|
|
*vr5500:
|
|
|
|
|
{
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
|
|
|
|
|
"drorv r<RD>, r<RT>, r<RS>"
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*vr5400:
|
|
|
|
|
*vr5500:
|
|
|
|
|
{
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::void:do_dsll:int rt, int rd, int shift
|
|
|
|
|
{
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[rd] = GPR[rt] << shift;
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsll r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dsll (SD_, RT, RD, SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsll32 r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
int s = 32 + SHIFT;
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[RD] = GPR[RT] << s;
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
2002-03-02 00:51:18 +01:00
|
|
|
|
:function:::void:do_dsllv:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
int s = MASKED64 (GPR[rs], 5, 0);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
|
|
|
|
GPR[rd] = GPR[rt] << s;
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsllv r<RD>, r<RT>, r<RS>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dsllv (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dsra:int rt, int rd, int shift
|
|
|
|
|
{
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[rd] = ((signed64) GPR[rt]) >> shift;
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsra r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dsra (SD_, RT, RD, SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
|
2002-03-01 08:34:57 +01:00
|
|
|
|
"dsra32 r<RD>, r<RT>, <SHIFT>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
int s = 32 + SHIFT;
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[RD] = ((signed64) GPR[RT]) >> s;
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dsrav:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
int s = MASKED64 (GPR[rs], 5, 0);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
|
|
|
|
GPR[rd] = ((signed64) GPR[rt]) >> s;
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
|
2002-03-01 08:34:57 +01:00
|
|
|
|
"dsrav r<RD>, r<RT>, r<RS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dsrav (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dsrl:int rt, int rd, int shift
|
|
|
|
|
{
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[rd] = (unsigned64) GPR[rt] >> shift;
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsrl r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dsrl (SD_, RT, RD, SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsrl32 r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
int s = 32 + SHIFT;
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RT], s);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[RD] = (unsigned64) GPR[RT] >> s;
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dsrlv:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
int s = MASKED64 (GPR[rs], 5, 0);
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[rd] = (unsigned64) GPR[rt] >> s;
|
2002-03-02 00:40:51 +01:00
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
|
2002-02-11 03:19:38 +01:00
|
|
|
|
"dsrlv r<RD>, r<RT>, r<RS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dsrlv (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsub r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
{
|
|
|
|
|
ALU64_BEGIN (GPR[RS]);
|
|
|
|
|
ALU64_SUB (GPR[RT]);
|
2002-02-11 23:49:45 +01:00
|
|
|
|
ALU64_END (GPR[RD]); /* This checks for overflow. */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_dsubu:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = GPR[rs] - GPR[rt];
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"dsubu r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_dsubu (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000010,26.INSTR_INDEX:NORMAL:32::J
|
|
|
|
|
"j <INSTR_INDEX>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
/* NOTE: The region used is that of the delay slot NIA and NOT the
|
|
|
|
|
current instruction */
|
|
|
|
|
address_word region = (NIA & MASK (63, 28));
|
|
|
|
|
DELAY_SLOT (region | (INSTR_INDEX << 2));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000011,26.INSTR_INDEX:NORMAL:32::JAL
|
|
|
|
|
"jal <INSTR_INDEX>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
/* NOTE: The region used is that of the delay slot and NOT the
|
|
|
|
|
current instruction */
|
|
|
|
|
address_word region = (NIA & MASK (63, 28));
|
|
|
|
|
GPR[31] = CIA + 8;
|
|
|
|
|
DELAY_SLOT (region | (INSTR_INDEX << 2));
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"jalr r<RS>":RD == 31
|
|
|
|
|
"jalr r<RD>, r<RS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
address_word temp = GPR[RS];
|
|
|
|
|
GPR[RD] = CIA + 8;
|
|
|
|
|
DELAY_SLOT (temp);
|
|
|
|
|
}
|
|
|
|
|
|
2007-02-19 18:53:29 +01:00
|
|
|
|
000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
|
|
|
|
|
"jalr.hb r<RS>":RD == 31
|
|
|
|
|
"jalr.hb r<RD>, r<RS>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
{
|
|
|
|
|
address_word temp = GPR[RS];
|
|
|
|
|
GPR[RD] = CIA + 8;
|
|
|
|
|
DELAY_SLOT (temp);
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2007-02-19 18:53:29 +01:00
|
|
|
|
000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"jr r<RS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (GPR[RS]);
|
|
|
|
|
}
|
|
|
|
|
|
2007-02-19 18:53:29 +01:00
|
|
|
|
000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
|
|
|
|
|
"jr.hb r<RS>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
{
|
|
|
|
|
DELAY_SLOT (GPR[RS]);
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
|
|
|
|
|
{
|
|
|
|
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
if ((vaddr & access) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
|
|
|
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
|
|
|
|
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
|
|
|
|
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
|
|
|
|
return (memval >> (8 * byte));
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-27 23:46:35 +01:00
|
|
|
|
:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
|
|
|
|
|
{
|
|
|
|
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
unsigned int word;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
int nr_lhs_bits;
|
|
|
|
|
int nr_rhs_bits;
|
|
|
|
|
unsigned_word lhs_mask;
|
|
|
|
|
unsigned_word temp;
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
2002-02-27 23:46:35 +01:00
|
|
|
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
|
|
|
|
paddr = (paddr ^ (reverseendian & mask));
|
|
|
|
|
if (BigEndianMem == 0)
|
|
|
|
|
paddr = paddr & ~access;
|
|
|
|
|
|
|
|
|
|
/* compute where within the word/mem we are */
|
|
|
|
|
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
|
|
|
|
|
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
|
|
|
|
|
nr_lhs_bits = 8 * byte + 8;
|
|
|
|
|
nr_rhs_bits = 8 * access - 8 * byte;
|
|
|
|
|
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
|
|
|
|
|
|
|
|
|
|
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
|
|
|
|
|
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
|
|
|
|
|
(long) ((unsigned64) paddr >> 32), (long) paddr,
|
|
|
|
|
word, byte, nr_lhs_bits, nr_rhs_bits); */
|
|
|
|
|
|
|
|
|
|
LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
|
|
|
|
|
if (word == 0)
|
|
|
|
|
{
|
|
|
|
|
/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
|
|
|
|
|
temp = (memval << nr_rhs_bits);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
/* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
|
|
|
|
|
temp = (memval >> nr_lhs_bits);
|
|
|
|
|
}
|
|
|
|
|
lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
|
|
|
|
|
rt = (rt & ~lhs_mask) | (temp & lhs_mask);
|
|
|
|
|
|
|
|
|
|
/* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
|
|
|
|
|
(long) ((unsigned64) memval >> 32), (long) memval,
|
|
|
|
|
(long) ((unsigned64) temp >> 32), (long) temp,
|
|
|
|
|
(long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
|
|
|
|
|
(long) (rt >> 32), (long) rt); */
|
|
|
|
|
return rt;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
|
|
|
|
|
{
|
|
|
|
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
2002-02-27 23:46:35 +01:00
|
|
|
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
|
|
|
|
|
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
|
|
|
|
|
paddr = (paddr ^ (reverseendian & mask));
|
|
|
|
|
if (BigEndianMem != 0)
|
|
|
|
|
paddr = paddr & ~access;
|
|
|
|
|
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
|
|
|
|
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
|
|
|
|
|
LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
|
|
|
|
|
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
|
|
|
|
|
(long) paddr, byte, (long) paddr, (long) memval); */
|
|
|
|
|
{
|
|
|
|
|
unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
|
|
|
|
|
rt &= ~screen;
|
|
|
|
|
rt |= (memval >> (8 * byte)) & screen;
|
|
|
|
|
}
|
|
|
|
|
return rt;
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
|
|
|
|
|
"lb r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
|
|
|
|
|
"lbu r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
|
|
|
|
|
"ld r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
|
|
|
|
|
"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
|
|
|
|
|
"ldl r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
|
|
|
|
|
"ldr r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
|
|
|
|
|
"lh r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
|
|
|
|
|
"lhu r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
|
|
|
|
|
"ll r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if ((vaddr & 3) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
|
|
|
|
{
|
|
|
|
|
unsigned64 memval = 0;
|
|
|
|
|
unsigned64 memval1 = 0;
|
2007-10-07 11:04:43 +02:00
|
|
|
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
unsigned int shift = 2;
|
|
|
|
|
unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
|
|
|
|
|
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
|
|
|
|
|
LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
|
|
|
|
|
byte = ((vaddr & mask) ^ (bigend << shift));
|
2002-03-03 07:49:43 +01:00
|
|
|
|
GPR[RT] = EXTEND32 (memval >> (8 * byte));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
LLBIT = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
|
|
|
|
|
"lld r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if ((vaddr & 7) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
|
|
|
|
{
|
|
|
|
|
unsigned64 memval = 0;
|
|
|
|
|
unsigned64 memval1 = 0;
|
|
|
|
|
LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
GPR[RT] = memval;
|
1999-04-16 03:35:26 +02:00
|
|
|
|
LLBIT = 1;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
|
2002-03-08 01:37:14 +01:00
|
|
|
|
"lui r<RT>, %#lx<IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT1 (IMMEDIATE);
|
|
|
|
|
GPR[RT] = EXTEND32 (IMMEDIATE << 16);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
|
|
|
|
|
"lw r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
|
|
|
|
|
"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
|
|
|
|
|
"lwl r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
1999-04-26 20:34:20 +02:00
|
|
|
|
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
|
|
|
|
|
"lwr r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-03-01 08:34:57 +01:00
|
|
|
|
100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"lwu r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
|
|
|
|
|
011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
|
|
|
|
|
"madd r<RS>, r<RT>"
|
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
signed64 temp;
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
|
|
|
|
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
|
|
|
|
LO = EXTEND32 (temp);
|
|
|
|
|
HI = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
|
|
|
|
|
"madd r<RS>, r<RT>":AC == 0
|
|
|
|
|
"madd ac<AC>, r<RS>, r<RT>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp2:
|
|
|
|
|
{
|
|
|
|
|
signed64 temp;
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
|
|
|
|
+ ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
|
|
|
|
DSPLO(AC) = EXTEND32 (temp);
|
|
|
|
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
|
|
|
|
|
011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
|
|
|
|
|
"maddu r<RS>, r<RT>"
|
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
unsigned64 temp;
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
|
|
|
|
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
2006-08-29 14:45:26 +02:00
|
|
|
|
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
LO = EXTEND32 (temp);
|
|
|
|
|
HI = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
|
|
|
|
|
"maddu r<RS>, r<RT>":AC == 0
|
|
|
|
|
"maddu ac<AC>, r<RS>, r<RT>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp2:
|
|
|
|
|
{
|
|
|
|
|
unsigned64 temp;
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
|
|
|
|
+ ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */
|
|
|
|
|
DSPLO(AC) = EXTEND32 (temp);
|
|
|
|
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::void:do_mfhi:int rd
|
|
|
|
|
{
|
|
|
|
|
check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
TRACE_ALU_INPUT1 (HI);
|
|
|
|
|
GPR[rd] = HI;
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
|
|
|
|
|
"mfhi r<RD>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
2007-03-01 15:29:26 +01:00
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
do_mfhi (SD_, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
|
|
|
|
|
"mfhi r<RD>":AC == 0
|
|
|
|
|
"mfhi r<RD>, ac<AC>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp:
|
|
|
|
|
{
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
do_mfhi (SD_, RD);
|
|
|
|
|
else
|
|
|
|
|
GPR[RD] = DSPHI(AC);
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
:function:::void:do_mflo:int rd
|
|
|
|
|
{
|
|
|
|
|
check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
|
|
|
|
|
TRACE_ALU_INPUT1 (LO);
|
|
|
|
|
GPR[rd] = LO;
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
|
|
|
|
|
"mflo r<RD>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
2007-03-01 15:29:26 +01:00
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
do_mflo (SD_, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
|
|
|
|
|
"mflo r<RD>":AC == 0
|
|
|
|
|
"mflo r<RD>, ac<AC>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp:
|
|
|
|
|
{
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
do_mflo (SD_, RD);
|
|
|
|
|
else
|
|
|
|
|
GPR[RD] = DSPLO(AC);
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"movn r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if (GPR[RT] != 0)
|
2002-06-13 01:20:56 +02:00
|
|
|
|
{
|
|
|
|
|
GPR[RD] = GPR[RS];
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"movz r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if (GPR[RT] == 0)
|
2002-06-13 01:20:56 +02:00
|
|
|
|
{
|
|
|
|
|
GPR[RD] = GPR[RS];
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
|
|
|
|
|
"msub r<RS>, r<RT>"
|
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
signed64 temp;
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
|
|
|
|
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
|
|
|
|
LO = EXTEND32 (temp);
|
|
|
|
|
HI = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
|
|
|
|
|
"msub r<RS>, r<RT>":AC == 0
|
|
|
|
|
"msub ac<AC>, r<RS>, r<RT>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp2:
|
|
|
|
|
{
|
|
|
|
|
signed64 temp;
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
|
|
|
|
- ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
|
|
|
|
|
DSPLO(AC) = EXTEND32 (temp);
|
|
|
|
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
|
|
|
|
|
011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
|
|
|
|
|
"msubu r<RS>, r<RT>"
|
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
unsigned64 temp;
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
|
|
|
|
|
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
|
|
|
|
LO = EXTEND32 (temp);
|
|
|
|
|
HI = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
|
|
|
|
|
"msubu r<RS>, r<RT>":AC == 0
|
|
|
|
|
"msubu ac<AC>, r<RS>, r<RT>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp2:
|
|
|
|
|
{
|
|
|
|
|
unsigned64 temp;
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
|
|
|
|
|
- ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
|
|
|
|
|
DSPLO(AC) = EXTEND32 (temp);
|
|
|
|
|
DSPHI(AC) = EXTEND32 (VH4_8 (temp));
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
|
|
|
|
|
"mthi r<RS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
2007-03-01 15:29:26 +01:00
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
check_mt_hilo (SD_, HIHISTORY);
|
|
|
|
|
HI = GPR[RS];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
|
|
|
|
|
"mthi r<RS>":AC == 0
|
|
|
|
|
"mthi r<RS>, ac<AC>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp:
|
|
|
|
|
{
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mt_hilo (SD_, HIHISTORY);
|
|
|
|
|
DSPHI(AC) = GPR[RS];
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"mtlo r<RS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
2007-03-01 15:29:26 +01:00
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
check_mt_hilo (SD_, LOHISTORY);
|
|
|
|
|
LO = GPR[RS];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
|
|
|
|
|
"mtlo r<RS>":AC == 0
|
|
|
|
|
"mtlo r<RS>, ac<AC>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp:
|
|
|
|
|
{
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mt_hilo (SD_, LOHISTORY);
|
|
|
|
|
DSPLO(AC) = GPR[RS];
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
|
|
|
|
|
"mul r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
2003-01-05 08:56:59 +01:00
|
|
|
|
*vr5500:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
signed64 prod;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
prod = (((signed64)(signed32) GPR[RS])
|
|
|
|
|
* ((signed64)(signed32) GPR[RT]));
|
|
|
|
|
GPR[RD] = EXTEND32 (VL4_8 (prod));
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::void:do_mult:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
signed64 prod;
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
prod = (((signed64)(signed32) GPR[rs])
|
|
|
|
|
* ((signed64)(signed32) GPR[rt]));
|
|
|
|
|
LO = EXTEND32 (VL4_8 (prod));
|
|
|
|
|
HI = EXTEND32 (VH4_8 (prod));
|
2006-08-29 14:45:26 +02:00
|
|
|
|
ACX = 0; /* SmartMIPS */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
if (rd != 0)
|
|
|
|
|
GPR[rd] = LO;
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"mult r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
{
|
|
|
|
|
do_mult (SD_, RS, RT, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
|
|
|
|
|
"mult r<RS>, r<RT>":AC == 0
|
|
|
|
|
"mult ac<AC>, r<RS>, r<RT>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp2:
|
|
|
|
|
{
|
|
|
|
|
signed64 prod;
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
prod = ((signed64)(signed32) GPR[RS])
|
|
|
|
|
* ((signed64)(signed32) GPR[RT]);
|
|
|
|
|
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
|
|
|
|
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
{
|
|
|
|
|
ACX = 0; /* SmartMIPS */
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
|
1999-07-07 19:31:57 +02:00
|
|
|
|
"mult r<RS>, r<RT>":RD == 0
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"mult r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_mult (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_multu:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
unsigned64 prod;
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
prod = (((unsigned64)(unsigned32) GPR[rs])
|
|
|
|
|
* ((unsigned64)(unsigned32) GPR[rt]));
|
|
|
|
|
LO = EXTEND32 (VL4_8 (prod));
|
|
|
|
|
HI = EXTEND32 (VH4_8 (prod));
|
|
|
|
|
if (rd != 0)
|
|
|
|
|
GPR[rd] = LO;
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"multu r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
|
|
|
|
*mips64:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
{
|
1999-09-13 23:40:00 +02:00
|
|
|
|
do_multu (SD_, RS, RT, 0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
|
|
|
|
|
"multu r<RS>, r<RT>":AC == 0
|
|
|
|
|
"multu r<RS>, r<RT>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
|
|
|
|
*dsp2:
|
|
|
|
|
{
|
|
|
|
|
unsigned64 prod;
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
|
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
prod = ((unsigned64)(unsigned32) GPR[RS])
|
|
|
|
|
* ((unsigned64)(unsigned32) GPR[RT]);
|
|
|
|
|
DSPLO(AC) = EXTEND32 (VL4_8 (prod));
|
|
|
|
|
DSPHI(AC) = EXTEND32 (VH4_8 (prod));
|
|
|
|
|
if (AC == 0)
|
|
|
|
|
TRACE_ALU_RESULT2 (HI, LO);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
|
1999-07-07 19:31:57 +02:00
|
|
|
|
"multu r<RS>, r<RT>":RD == 0
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"multu r<RD>, r<RS>, r<RT>"
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
1999-09-13 23:40:00 +02:00
|
|
|
|
do_multu (SD_, RS, RT, RD);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_nor:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = ~ (GPR[rs] | GPR[rt]);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
|
|
|
|
|
"nor r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_nor (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_or:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = (GPR[rs] | GPR[rt]);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
|
|
|
|
|
"or r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_or (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_ori:int rs, int rt, unsigned immediate
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], immediate);
|
|
|
|
|
GPR[rt] = (GPR[rs] | immediate);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rt]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
|
2002-03-08 01:37:14 +01:00
|
|
|
|
"ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_ori (SD_, RS, RT, IMMEDIATE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-28 08:01:14 +01:00
|
|
|
|
110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
|
|
|
|
|
"pref <HINT>, <OFFSET>(r<BASE>)"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
{
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
Prefetch(uncached,paddr,vaddr,isDATA,HINT);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-27 23:46:35 +01:00
|
|
|
|
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
|
|
|
|
|
{
|
|
|
|
|
unsigned64 result;
|
|
|
|
|
|
|
|
|
|
y &= 31;
|
|
|
|
|
TRACE_ALU_INPUT2 (x, y);
|
|
|
|
|
result = EXTEND32 (ROTR32 (x, y));
|
|
|
|
|
TRACE_ALU_RESULT (result);
|
|
|
|
|
return result;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
|
|
|
|
|
"ror r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
2006-08-29 14:45:26 +02:00
|
|
|
|
*smartmips:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*vr5400:
|
|
|
|
|
*vr5500:
|
|
|
|
|
{
|
|
|
|
|
GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
|
|
|
|
|
"rorv r<RD>, r<RT>, r<RS>"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
*mips64r2:
|
2006-08-29 14:45:26 +02:00
|
|
|
|
*smartmips:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*vr5400:
|
|
|
|
|
*vr5500:
|
|
|
|
|
{
|
|
|
|
|
GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
|
|
|
|
|
{
|
|
|
|
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
if ((vaddr & access) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
|
|
|
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
|
|
|
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
|
|
|
|
memval = (word << (8 * byte));
|
|
|
|
|
StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-27 23:46:35 +01:00
|
|
|
|
:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
|
|
|
|
|
{
|
|
|
|
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
unsigned int word;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
int nr_lhs_bits;
|
|
|
|
|
int nr_rhs_bits;
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
2002-02-27 23:46:35 +01:00
|
|
|
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
|
|
|
|
paddr = (paddr ^ (reverseendian & mask));
|
|
|
|
|
if (BigEndianMem == 0)
|
|
|
|
|
paddr = paddr & ~access;
|
|
|
|
|
|
|
|
|
|
/* compute where within the word/mem we are */
|
|
|
|
|
byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
|
|
|
|
|
word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
|
|
|
|
|
nr_lhs_bits = 8 * byte + 8;
|
|
|
|
|
nr_rhs_bits = 8 * access - 8 * byte;
|
|
|
|
|
/* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
|
|
|
|
|
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
|
|
|
|
|
(long) ((unsigned64) vaddr >> 32), (long) vaddr,
|
|
|
|
|
(long) ((unsigned64) paddr >> 32), (long) paddr,
|
|
|
|
|
word, byte, nr_lhs_bits, nr_rhs_bits); */
|
|
|
|
|
|
|
|
|
|
if (word == 0)
|
|
|
|
|
{
|
|
|
|
|
memval = (rt >> nr_rhs_bits);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
memval = (rt << nr_lhs_bits);
|
|
|
|
|
}
|
|
|
|
|
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
|
|
|
|
|
(long) ((unsigned64) rt >> 32), (long) rt,
|
|
|
|
|
(long) ((unsigned64) memval >> 32), (long) memval); */
|
|
|
|
|
StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
|
|
|
|
|
{
|
|
|
|
|
address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? -1 : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
2002-02-27 23:46:35 +01:00
|
|
|
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
|
|
|
|
|
paddr = (paddr ^ (reverseendian & mask));
|
|
|
|
|
if (BigEndianMem != 0)
|
|
|
|
|
paddr &= ~access;
|
|
|
|
|
byte = ((vaddr & mask) ^ (bigendiancpu & mask));
|
|
|
|
|
memval = (rt << (byte * 8));
|
|
|
|
|
StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
|
|
|
|
|
"sb r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
|
|
|
|
|
"sc r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
unsigned32 instruction = instruction_0;
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if ((vaddr & 3) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
|
|
|
|
{
|
|
|
|
|
unsigned64 memval = 0;
|
|
|
|
|
unsigned64 memval1 = 0;
|
2007-10-07 11:04:43 +02:00
|
|
|
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
unsigned int byte;
|
2007-10-07 11:04:43 +02:00
|
|
|
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
|
|
|
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
memval = ((unsigned64) GPR[RT] << (8 * byte));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
if (LLBIT)
|
|
|
|
|
{
|
|
|
|
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
|
|
|
|
}
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
GPR[RT] = LLBIT;
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
|
|
|
|
|
"scd r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if ((vaddr & 7) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
|
|
|
|
{
|
|
|
|
|
unsigned64 memval = 0;
|
|
|
|
|
unsigned64 memval1 = 0;
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
memval = GPR[RT];
|
1999-04-16 03:35:26 +02:00
|
|
|
|
if (LLBIT)
|
|
|
|
|
{
|
|
|
|
|
StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
|
|
|
|
|
}
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
GPR[RT] = LLBIT;
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
|
|
|
|
|
"sd r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
|
|
|
|
|
"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
|
|
|
|
|
"sdl r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
|
|
|
|
|
"sdr r<RT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
|
|
|
|
|
"sh r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_sll:int rt, int rd, int shift
|
|
|
|
|
{
|
|
|
|
|
unsigned32 temp = (GPR[rt] << shift);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
|
|
|
|
GPR[rd] = EXTEND32 (temp);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
|
2002-02-11 03:19:38 +01:00
|
|
|
|
"nop":RD == 0 && RT == 0 && SHIFT == 0
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sll r<RD>, r<RT>, <SHIFT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-02-11 03:19:38 +01:00
|
|
|
|
/* Skip shift for NOP, so that there won't be lots of extraneous
|
|
|
|
|
trace output. */
|
|
|
|
|
if (RD != 0 || RT != 0 || SHIFT != 0)
|
|
|
|
|
do_sll (SD_, RT, RD, SHIFT);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
|
|
|
|
|
"nop":RD == 0 && RT == 0 && SHIFT == 0
|
|
|
|
|
"ssnop":RD == 0 && RT == 0 && SHIFT == 1
|
|
|
|
|
"sll r<RD>, r<RT>, <SHIFT>"
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
/* Skip shift for NOP and SSNOP, so that there won't be lots of
|
|
|
|
|
extraneous trace output. */
|
|
|
|
|
if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
|
|
|
|
|
do_sll (SD_, RT, RD, SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
:function:::void:do_sllv:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
int s = MASKED (GPR[rs], 4, 0);
|
|
|
|
|
unsigned32 temp = (GPR[rt] << s);
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
|
|
|
|
GPR[rd] = EXTEND32 (temp);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sllv r<RD>, r<RT>, r<RS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_sllv (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_slt:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"slt r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_slt (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_slti:int rs, int rt, unsigned16 immediate
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
|
|
|
|
GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rt]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
|
|
|
|
|
"slti r<RT>, r<RS>, <IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_slti (SD_, RS, RT, IMMEDIATE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
|
|
|
|
|
GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rt]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
|
|
|
|
|
"sltiu r<RT>, r<RS>, <IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_sltiu (SD_, RS, RT, IMMEDIATE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_sltu:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sltu r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_sltu (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_sra:int rt, int rd, int shift
|
|
|
|
|
{
|
|
|
|
|
signed32 temp = (signed32) GPR[rt] >> shift;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
|
|
|
|
GPR[rd] = EXTEND32 (temp);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
|
|
|
|
|
"sra r<RD>, r<RT>, <SHIFT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_sra (SD_, RT, RD, SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_srav:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
int s = MASKED (GPR[rs], 4, 0);
|
|
|
|
|
signed32 temp = (signed32) GPR[rt] >> s;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
|
|
|
|
GPR[rd] = EXTEND32 (temp);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"srav r<RD>, r<RT>, r<RS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_srav (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_srl:int rt, int rd, int shift
|
|
|
|
|
{
|
|
|
|
|
unsigned32 temp = (unsigned32) GPR[rt] >> shift;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], shift);
|
|
|
|
|
GPR[rd] = EXTEND32 (temp);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
|
|
|
|
|
"srl r<RD>, r<RT>, <SHIFT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_srl (SD_, RT, RD, SHIFT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_srlv:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
int s = MASKED (GPR[rs], 4, 0);
|
|
|
|
|
unsigned32 temp = (unsigned32) GPR[rt] >> s;
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rt], s);
|
|
|
|
|
GPR[rd] = EXTEND32 (temp);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"srlv r<RD>, r<RT>, r<RS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_srlv (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sub r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
|
|
|
|
|
{
|
|
|
|
|
ALU32_BEGIN (GPR[RS]);
|
|
|
|
|
ALU32_SUB (GPR[RT]);
|
2002-02-11 23:49:45 +01:00
|
|
|
|
ALU32_END (GPR[RD]); /* This checks for overflow. */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RD]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_subu:int rs, int rt, int rd
|
|
|
|
|
{
|
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
2002-05-01 19:26:14 +02:00
|
|
|
|
if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"subu r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_subu (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
|
|
|
|
|
"sw r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*r3900:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
|
|
|
|
|
"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
|
|
|
|
|
"swl r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
|
|
|
|
|
"swr r<RT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sync":STYPE == 0
|
|
|
|
|
"sync <STYPE>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
SyncOperation (STYPE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,20.CODE,001100:SPECIAL:32::SYSCALL
|
2002-03-08 01:37:14 +01:00
|
|
|
|
"syscall %#lx<CODE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (SystemCall, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
|
|
|
|
|
"teq r<RS>, r<RT>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
|
|
|
|
|
"teqi r<RS>, <IMMEDIATE>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
|
|
|
|
|
"tge r<RS>, r<RT>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
|
|
|
|
|
"tgei r<RS>, <IMMEDIATE>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
|
|
|
|
|
"tgeiu r<RS>, <IMMEDIATE>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
|
|
|
|
|
"tgeu r<RS>, r<RT>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
|
|
|
|
|
"tlt r<RS>, r<RT>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
|
|
|
|
|
"tlti r<RS>, <IMMEDIATE>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
|
|
|
|
|
"tltiu r<RS>, <IMMEDIATE>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
|
|
|
|
|
"tltu r<RS>, r<RT>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
|
|
|
|
|
"tne r<RS>, r<RT>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
|
2002-06-13 01:20:56 +02:00
|
|
|
|
"tnei r<RS>, <IMMEDIATE>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
|
2002-03-05 23:24:24 +01:00
|
|
|
|
SignalException (Trap, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_xor:int rs, int rt, int rd
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
|
|
|
|
|
GPR[rd] = GPR[rs] ^ GPR[rt];
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rd]);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"xor r<RD>, r<RS>, r<RT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_xor (SD_, RS, RT, RD);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:function:::void:do_xori:int rs, int rt, unsigned16 immediate
|
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT2 (GPR[rs], immediate);
|
|
|
|
|
GPR[rt] = GPR[rs] ^ immediate;
|
|
|
|
|
TRACE_ALU_RESULT (GPR[rt]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
|
2002-03-08 01:37:14 +01:00
|
|
|
|
"xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
do_xori (SD_, RS, RT, IMMEDIATE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// MIPS Architecture:
|
|
|
|
|
//
|
|
|
|
|
// FPU Instruction Set (COP1 & COP1X)
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
:%s::::FMT:int fmt
|
|
|
|
|
{
|
|
|
|
|
switch (fmt)
|
|
|
|
|
{
|
|
|
|
|
case fmt_single: return "s";
|
|
|
|
|
case fmt_double: return "d";
|
|
|
|
|
case fmt_word: return "w";
|
|
|
|
|
case fmt_long: return "l";
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
case fmt_ps: return "ps";
|
1999-04-16 03:35:26 +02:00
|
|
|
|
default: return "?";
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:%s::::TF:int tf
|
|
|
|
|
{
|
|
|
|
|
if (tf)
|
|
|
|
|
return "t";
|
|
|
|
|
else
|
|
|
|
|
return "f";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:%s::::ND:int nd
|
|
|
|
|
{
|
|
|
|
|
if (nd)
|
|
|
|
|
return "l";
|
|
|
|
|
else
|
|
|
|
|
return "";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
:%s::::COND:int cond
|
|
|
|
|
{
|
|
|
|
|
switch (cond)
|
|
|
|
|
{
|
|
|
|
|
case 00: return "f";
|
|
|
|
|
case 01: return "un";
|
|
|
|
|
case 02: return "eq";
|
|
|
|
|
case 03: return "ueq";
|
|
|
|
|
case 04: return "olt";
|
|
|
|
|
case 05: return "ult";
|
|
|
|
|
case 06: return "ole";
|
|
|
|
|
case 07: return "ule";
|
|
|
|
|
case 010: return "sf";
|
|
|
|
|
case 011: return "ngle";
|
|
|
|
|
case 012: return "seq";
|
|
|
|
|
case 013: return "ngl";
|
|
|
|
|
case 014: return "lt";
|
|
|
|
|
case 015: return "nge";
|
|
|
|
|
case 016: return "le";
|
|
|
|
|
case 017: return "ngt";
|
|
|
|
|
default: return "?";
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
|
|
|
|
|
// Helpers:
|
|
|
|
|
//
|
|
|
|
|
// Check that the given FPU format is usable, and signal a
|
|
|
|
|
// ReservedInstruction exception if not.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
// check_fmt_p checks that the format is single, double, or paired single.
|
|
|
|
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
/* None of these ISAs support Paired Single, so just fall back to
|
|
|
|
|
the single/double check. */
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
if ((fmt != fmt_single) && (fmt != fmt_double))
|
|
|
|
|
SignalException (ReservedInstruction, insn);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
}
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
|
|
|
|
*mips32r2:
|
|
|
|
|
{
|
|
|
|
|
if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
|
|
|
|
|
SignalException (ReservedInstruction, insn);
|
|
|
|
|
}
|
|
|
|
|
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
:function:::void:check_fmt_p:int fmt, instruction_word insn
|
|
|
|
|
*mipsV:
|
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
{
|
|
|
|
|
if ((fmt != fmt_single) && (fmt != fmt_double)
|
|
|
|
|
&& (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
|
|
|
|
|
SignalException (ReservedInstruction, insn);
|
|
|
|
|
}
|
|
|
|
|
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
// Helper:
|
2002-03-04 04:19:49 +01:00
|
|
|
|
//
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
// Check that the FPU is currently usable, and signal a CoProcessorUnusable
|
|
|
|
|
// exception if not.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
:function:::void:check_fpu:
|
2002-03-04 04:19:49 +01:00
|
|
|
|
*mipsI:
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
if (! COP_Usable (1))
|
|
|
|
|
SignalExceptionCoProcessorUnusable (1);
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2002-07-31 07:44:54 +02:00
|
|
|
|
// Helper:
|
|
|
|
|
//
|
|
|
|
|
// Load a double word FP value using 2 32-bit memory cycles a la MIPS II
|
|
|
|
|
// or MIPS32. do_load cannot be used instead because it returns an
|
|
|
|
|
// unsigned_word, which is limited to the size of the machine's registers.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
:function:::unsigned64:do_load_double:address_word base, address_word offset
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-07-31 07:44:54 +02:00
|
|
|
|
{
|
|
|
|
|
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
unsigned64 v;
|
|
|
|
|
|
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
|
|
|
|
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
|
|
|
|
|
AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
|
|
|
|
|
sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
|
|
|
|
|
isREAL);
|
|
|
|
|
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
|
|
|
|
|
isDATA, isREAL);
|
|
|
|
|
v = (unsigned64)memval;
|
|
|
|
|
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
|
|
|
|
|
isDATA, isREAL);
|
|
|
|
|
return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// Helper:
|
|
|
|
|
//
|
|
|
|
|
// Store a double word FP value using 2 32-bit memory cycles a la MIPS II
|
|
|
|
|
// or MIPS32. do_load cannot be used instead because it returns an
|
|
|
|
|
// unsigned_word, which is limited to the size of the machine's registers.
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
:function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-07-31 07:44:54 +02:00
|
|
|
|
{
|
|
|
|
|
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
|
|
|
|
|
address_word vaddr;
|
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
unsigned64 memval;
|
|
|
|
|
|
|
|
|
|
vaddr = loadstore_ea (SD_, base, offset);
|
|
|
|
|
if ((vaddr & AccessLength_DOUBLEWORD) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
|
|
|
|
|
AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
|
|
|
|
|
sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
|
|
|
|
|
isREAL);
|
|
|
|
|
memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
|
|
|
|
|
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
|
|
|
|
|
isREAL);
|
|
|
|
|
memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
|
|
|
|
|
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
|
|
|
|
|
isREAL);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"abs.%s<FMT> f<FD>, f<FS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"add.%s<FMT> f<FD>, f<FS>, f<FT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
unsigned64 fs;
|
|
|
|
|
unsigned64 ft;
|
|
|
|
|
unsigned64 fd;
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
fs = ValueFPR (FS, fmt_ps);
|
|
|
|
|
if ((GPR[RS] & 0x3) != 0)
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
if ((GPR[RS] & 0x4) == 0)
|
|
|
|
|
fd = fs;
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
ft = ValueFPR (FT, fmt_ps);
|
|
|
|
|
if (BigEndianCPU)
|
|
|
|
|
fd = PackPS (PSLower (fs), PSUpper (ft));
|
|
|
|
|
else
|
|
|
|
|
fd = PackPS (PSLower (ft), PSUpper (fs));
|
|
|
|
|
}
|
|
|
|
|
StoreFPR (FD, fmt_ps, fd);
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
// BC1F
|
|
|
|
|
// BC1FL
|
|
|
|
|
// BC1T
|
|
|
|
|
// BC1TL
|
|
|
|
|
|
|
|
|
|
010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
|
|
|
|
|
"bc1%s<TF>%s<ND> <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
TRACE_BRANCH_INPUT (PREVCOC1());
|
|
|
|
|
if (PREVCOC1() == TF)
|
|
|
|
|
{
|
|
|
|
|
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
|
|
|
|
|
TRACE_BRANCH_RESULT (dest);
|
|
|
|
|
DELAY_SLOT (dest);
|
|
|
|
|
}
|
|
|
|
|
else if (ND)
|
|
|
|
|
{
|
|
|
|
|
TRACE_BRANCH_RESULT (0);
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
TRACE_BRANCH_RESULT (NIA);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
|
|
|
|
|
"bc1%s<TF>%s<ND> <OFFSET>":CC == 0
|
|
|
|
|
"bc1%s<TF>%s<ND> <CC>, <OFFSET>"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
#*vr4100:
|
2002-02-12 00:35:07 +01:00
|
|
|
|
*vr5000:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
if (GETFCC(CC) == TF)
|
|
|
|
|
{
|
|
|
|
|
address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
|
|
|
|
|
DELAY_SLOT (dest);
|
|
|
|
|
}
|
|
|
|
|
else if (ND)
|
|
|
|
|
{
|
|
|
|
|
NULLIFY_NEXT_INSTRUCTION ();
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
|
|
|
|
|
TRACE_ALU_RESULT (ValueFCR (31));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
|
|
|
|
|
"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
|
|
|
|
|
TRACE_ALU_RESULT (ValueFCR (31));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"ceil.l.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_long));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
|
2002-06-13 01:20:56 +02:00
|
|
|
|
"ceil.w.%s<FMT> f<FD>, f<FS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_word));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
|
|
|
|
|
"cfc1 r<RT>, f<FS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
if (FS == 0)
|
|
|
|
|
PENDING_FILL (RT, EXTEND32 (FCR0));
|
|
|
|
|
else if (FS == 31)
|
|
|
|
|
PENDING_FILL (RT, EXTEND32 (FCR31));
|
|
|
|
|
/* else NOP */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
|
|
|
|
|
"cfc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
if (FS == 0 || FS == 31)
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
unsigned_word fcr = ValueFCR (FS);
|
|
|
|
|
TRACE_ALU_INPUT1 (fcr);
|
|
|
|
|
GPR[RT] = fcr;
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
/* else NOP */
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
|
|
|
|
|
010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
|
|
|
|
|
"cfc1 r<RT>, f<FS>"
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
|
|
|
|
|
{
|
|
|
|
|
unsigned_word fcr = ValueFCR (FS);
|
|
|
|
|
TRACE_ALU_INPUT1 (fcr);
|
|
|
|
|
GPR[RT] = fcr;
|
|
|
|
|
}
|
|
|
|
|
/* else NOP */
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
|
|
|
|
|
"ctc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
if (FS == 31)
|
|
|
|
|
PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
|
|
|
|
|
/* else NOP */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
|
|
|
|
|
"ctc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsIV:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
TRACE_ALU_INPUT1 (GPR[RT]);
|
|
|
|
|
if (FS == 31)
|
|
|
|
|
StoreFCR (FS, GPR[RT]);
|
|
|
|
|
/* else NOP */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
|
|
|
|
|
"ctc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsV:
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
TRACE_ALU_INPUT1 (GPR[RT]);
|
|
|
|
|
if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
|
|
|
|
|
StoreFCR (FS, GPR[RT]);
|
|
|
|
|
/* else NOP */
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// FIXME: Does not correctly differentiate between mips*
|
|
|
|
|
//
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"cvt.d.%s<FMT> f<FD>, f<FS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
if ((fmt == fmt_double) | 0)
|
|
|
|
|
SignalException (ReservedInstruction, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_double));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"cvt.l.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
|
|
|
|
|
SignalException (ReservedInstruction, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_long));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"cvt.ps.s f<FD>, f<FS>, f<FT>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
|
|
|
|
|
ValueFPR (FT, fmt_single)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
//
|
|
|
|
|
// FIXME: Does not correctly differentiate between mips*
|
|
|
|
|
//
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"cvt.s.%s<FMT> f<FD>, f<FS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
if ((fmt == fmt_single) | 0)
|
|
|
|
|
SignalException (ReservedInstruction, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_single));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"cvt.s.pl f<FD>, f<FS>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"cvt.s.pu f<FD>, f<FS>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"cvt.w.%s<FMT> f<FD>, f<FS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
|
|
|
|
|
SignalException (ReservedInstruction, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_word));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"div.%s<FMT> f<FD>, f<FS>, f<FT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
|
|
|
|
|
"dmfc1 r<RT>, f<FS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
{
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
unsigned64 v;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
if (SizeFGR () == 64)
|
|
|
|
|
v = FGR[FS];
|
|
|
|
|
else if ((FS & 0x1) == 0)
|
|
|
|
|
v = SET64HI (FGR[FS+1]) | FGR[FS];
|
1999-04-16 03:35:26 +02:00
|
|
|
|
else
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
|
|
|
|
|
PENDING_FILL (RT, v);
|
|
|
|
|
TRACE_ALU_RESULT (v);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
|
|
|
|
|
010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
|
|
|
|
|
"dmfc1 r<RT>, f<FS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
if (SizeFGR () == 64)
|
|
|
|
|
GPR[RT] = FGR[FS];
|
|
|
|
|
else if ((FS & 0x1) == 0)
|
|
|
|
|
GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
|
1999-04-16 03:35:26 +02:00
|
|
|
|
else
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
|
|
|
|
|
"dmtc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
{
|
|
|
|
|
unsigned64 v;
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
if (SizeFGR () == 64)
|
|
|
|
|
PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
|
|
|
|
|
else if ((FS & 0x1) == 0)
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
|
|
|
|
|
PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
else
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
TRACE_FP_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
|
|
|
|
|
"dmtc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
if (SizeFGR () == 64)
|
|
|
|
|
StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
|
|
|
|
|
else if ((FS & 0x1) == 0)
|
|
|
|
|
StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
|
|
|
|
|
else
|
|
|
|
|
Unpredictable ();
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"floor.l.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_long));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"floor.w.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_word));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-07-31 07:44:54 +02:00
|
|
|
|
110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsII:
|
2002-07-31 07:44:54 +02:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-07-31 07:44:54 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
|
|
|
|
|
"ldc1 f<FT>, <OFFSET>(r<BASE>)"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
|
|
|
|
|
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-28 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
LWC1, SWC1): Add "f" to filter, since these are FP instructions.
2002-03-01 08:53:46 +01:00
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"ldxc1 f<FD>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
|
|
|
|
|
"luxc1 f<FD>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
{
|
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word index = GPR[INDEX];
|
|
|
|
|
address_word vaddr = base + index;
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
if (SizeFGR () != 64)
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
|
|
|
|
if ((vaddr & 0x7) != 0)
|
|
|
|
|
index -= (vaddr & 0x7);
|
|
|
|
|
COP_LD (1, FD, do_load_double (SD_, base, index));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2003-01-14 20:01:41 +01:00
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
|
|
|
|
|
"luxc1 f<FD>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mipsV:
|
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2003-01-14 20:01:41 +01:00
|
|
|
|
{
|
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word index = GPR[INDEX];
|
|
|
|
|
address_word vaddr = base + index;
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
if (SizeFGR () != 64)
|
|
|
|
|
Unpredictable ();
|
2003-01-14 20:01:41 +01:00
|
|
|
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
|
|
|
|
if ((vaddr & 0x7) != 0)
|
|
|
|
|
index -= (vaddr & 0x7);
|
|
|
|
|
COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
2002-03-04 04:19:49 +01:00
|
|
|
|
110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"lwc1 f<FT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"lwxc1 f<FD>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
|
|
|
|
ValueFPR (FR, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
|
|
|
|
|
"mfc1 r<RT>, f<FS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
{
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
unsigned64 v;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
v = EXTEND32 (FGR[FS]);
|
|
|
|
|
PENDING_FILL (RT, v);
|
|
|
|
|
TRACE_ALU_RESULT (v);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
|
|
|
|
|
010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
|
|
|
|
|
"mfc1 r<RT>, f<FS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
GPR[RT] = EXTEND32 (FGR[FS]);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"mov.%s<FMT> f<FD>, f<FS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// MOVF
|
1999-12-07 04:56:43 +01:00
|
|
|
|
// MOVT
|
2002-02-28 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
LWC1, SWC1): Add "f" to filter, since these are FP instructions.
2002-03-01 08:53:46 +01:00
|
|
|
|
000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"mov%s<TF> r<RD>, r<RS>, <CC>"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
if (GETFCC(CC) == TF)
|
|
|
|
|
GPR[RD] = GPR[RS];
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// MOVF.fmt
|
1999-12-07 04:56:43 +01:00
|
|
|
|
// MOVT.fmt
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
if (fmt != fmt_ps)
|
|
|
|
|
{
|
|
|
|
|
if (GETFCC(CC) == TF)
|
|
|
|
|
StoreFPR (FD, fmt, ValueFPR (FS, fmt));
|
|
|
|
|
else
|
|
|
|
|
StoreFPR (FD, fmt, ValueFPR (FD, fmt)); /* set fmt */
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
unsigned64 fd;
|
|
|
|
|
fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
|
|
|
|
|
fmt_ps)),
|
|
|
|
|
PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
|
|
|
|
|
fmt_ps)));
|
|
|
|
|
StoreFPR (FD, fmt_ps, fd);
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
|
2000-07-04 04:32:58 +02:00
|
|
|
|
"movn.%s<FMT> f<FD>, f<FS>, r<RT>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2000-07-04 04:32:58 +02:00
|
|
|
|
if (GPR[RT] != 0)
|
|
|
|
|
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
|
|
|
|
|
else
|
|
|
|
|
StoreFPR (FD, FMT, ValueFPR (FD, FMT));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// MOVT see MOVtf
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// MOVT.fmt see MOVtf.fmt
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"movz.%s<FMT> f<FD>, f<FS>, r<RT>"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2000-07-04 04:32:58 +02:00
|
|
|
|
if (GPR[RT] == 0)
|
|
|
|
|
StoreFPR (FD, FMT, ValueFPR (FS, FMT));
|
|
|
|
|
else
|
|
|
|
|
StoreFPR (FD, FMT, ValueFPR (FD, FMT));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
|
|
|
|
ValueFPR (FR, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
|
|
|
|
|
"mtc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
if (SizeFGR () == 64)
|
|
|
|
|
PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
|
|
|
|
|
else
|
|
|
|
|
PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
|
|
|
|
|
TRACE_FP_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
|
|
|
|
|
"mtc1 r<RT>, f<FS>"
|
|
|
|
|
*mipsIV:
|
|
|
|
|
*mipsV:
|
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-06 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.h: New file.
* sim-main.h: Include cp1.h.
(SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
(FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
(FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
(FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
(value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
(ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
* cp1.c: Don't include sim-fpu.h; already included by
sim-main.h. Clean up formatting of some comments.
(NaN, Equal, Less): Remove.
(test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
(fp_cmp): New functions.
* mips.igen (do_c_cond_fmt): Remove.
(C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
Compare. Add result tracing.
(CxC1): Remove, replace with...
(CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
(DMxC1): Remove, replace with...
(DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
(MxC1): Remove, replace with...
(MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
2002-06-07 02:13:24 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
|
|
|
|
|
}
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"mul.%s<FMT> f<FD>, f<FS>, f<FT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"neg.%s<FMT> f<FD>, f<FS>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
|
|
|
|
ValueFPR (FR, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
|
|
|
|
|
ValueFPR (FR, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"pll.ps f<FD>, f<FS>, f<FT>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
|
|
|
|
PSLower (ValueFPR (FT, fmt_ps))));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"plu.ps f<FD>, f<FS>, f<FT>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
|
|
|
|
|
PSUpper (ValueFPR (FT, fmt_ps))));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"prefx <HINT>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word index = GPR[INDEX];
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, index);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
Prefetch(uncached,paddr,vaddr,isDATA,HINT);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"pul.ps f<FD>, f<FS>, f<FT>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
|
|
|
|
PSLower (ValueFPR (FT, fmt_ps))));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
"puu.ps f<FD>, f<FS>, f<FT>"
|
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2002-06-13 Chris Demetriou <cgd@broadcom.com>
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
2002-06-14 06:44:11 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
|
|
|
|
StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
|
|
|
|
|
PSUpper (ValueFPR (FT, fmt_ps))));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"recip.%s<FMT> f<FD>, f<FS>"
|
1999-10-26 05:43:48 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"round.l.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_long));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"round.w.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_word));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
|
2002-06-13 01:20:56 +02:00
|
|
|
|
"rsqrt.%s<FMT> f<FD>, f<FS>"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-07 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
(fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
* sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
(fp_nmsub): New prototypes.
(RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
(NegMultiplySub): New defines.
* mips.igen (RSQRT.fmt): Use RSquareRoot().
(MADD.D, MADD.S): Replace with...
(MADD.fmt): New instruction.
(MSUB.D, MSUB.S): Replace with...
(MSUB.fmt): New instruction.
(NMADD.D, NMADD.S): Replace with...
(NMADD.fmt): New instruction.
(NMSUB.D, MSUB.S): Replace with...
(NMSUB.fmt): New instruction.
2002-06-08 05:05:23 +02:00
|
|
|
|
StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-07-31 07:44:54 +02:00
|
|
|
|
111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
|
|
|
|
|
*mipsII:
|
2002-07-31 07:44:54 +02:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-07-31 07:44:54 +02:00
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
|
|
|
|
|
"sdc1 f<FT>, <OFFSET>(r<BASE>)"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
|
|
|
|
|
"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mips32r2
|
|
|
|
|
{
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-28 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
LWC1, SWC1): Add "f" to filter, since these are FP instructions.
2002-03-01 08:53:46 +01:00
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
|
2002-03-01 07:40:28 +01:00
|
|
|
|
"sdxc1 f<FS>, r<INDEX>(r<BASE>)"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
|
|
|
|
|
"suxc1 f<FS>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mips32r2:
|
|
|
|
|
{
|
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word index = GPR[INDEX];
|
|
|
|
|
address_word vaddr = base + index;
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
if (SizeFGR () != 64)
|
|
|
|
|
Unpredictable ();
|
|
|
|
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
|
|
|
|
if ((vaddr & 0x7) != 0)
|
|
|
|
|
index -= (vaddr & 0x7);
|
|
|
|
|
do_store_double (SD_, base, index, COP_SD (1, FS));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2003-01-14 20:01:41 +01:00
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
|
|
|
|
|
"suxc1 f<FS>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mipsV:
|
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
2003-01-14 20:01:41 +01:00
|
|
|
|
{
|
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word index = GPR[INDEX];
|
|
|
|
|
address_word vaddr = base + index;
|
|
|
|
|
check_fpu (SD_);
|
|
|
|
|
check_u64 (SD_, instruction_0);
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
if (SizeFGR () != 64)
|
|
|
|
|
Unpredictable ();
|
2003-01-14 20:01:41 +01:00
|
|
|
|
/* Arrange for the bottom 3 bits of (base + index) to be 0. */
|
|
|
|
|
if ((vaddr & 0x7) != 0)
|
|
|
|
|
index -= (vaddr & 0x7);
|
|
|
|
|
do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sqrt.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, (SquareRoot (ValueFPR (FS, fmt), fmt)));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"sub.%s<FMT> f<FD>, f<FS>, f<FT>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-04 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
2002-03-05 04:14:56 +01:00
|
|
|
|
check_fmt_p (SD_, fmt, instruction_0);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-02-28 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
LWC1, SWC1): Add "f" to filter, since these are FP instructions.
2002-03-01 08:53:46 +01:00
|
|
|
|
111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"swc1 f<FT>, <OFFSET>(r<BASE>)"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET);
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if ((vaddr & 3) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
|
|
|
|
{
|
|
|
|
|
uword64 memval = 0;
|
|
|
|
|
uword64 memval1 = 0;
|
|
|
|
|
uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
|
|
|
|
|
unsigned int byte;
|
|
|
|
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
|
|
|
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-28 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
(MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
LWC1, SWC1): Add "f" to filter, since these are FP instructions.
2002-03-01 08:53:46 +01:00
|
|
|
|
010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"swxc1 f<FS>, r<INDEX>(r<BASE>)"
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
|
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word index = GPR[INDEX];
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, index);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if ((vaddr & 3) != 0)
|
|
|
|
|
{
|
|
|
|
|
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
|
|
|
|
|
{
|
|
|
|
|
unsigned64 memval = 0;
|
|
|
|
|
unsigned64 memval1 = 0;
|
2007-10-07 11:04:43 +02:00
|
|
|
|
unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
|
|
|
|
|
address_word reverseendian = (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
|
|
|
|
|
address_word bigendiancpu = (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
unsigned int byte;
|
2007-10-07 11:04:43 +02:00
|
|
|
|
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
|
|
|
|
|
byte = ((vaddr & mask) ^ bigendiancpu);
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
sim/mips/
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
2007-10-22 22:02:25 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"trunc.l.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
* mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
for mips32r2.
2007-05-14 18:24:25 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_long));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2004-04-09 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_fmt): Remove.
(ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
(CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
(MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
(ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
(TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
(check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
(SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
(C.cnd.fmta): Remove incorrect call to check_fmt_p.
2004-04-10 08:51:49 +02:00
|
|
|
|
010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"trunc.w.%s<FMT> f<FD>, f<FS>"
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
int fmt = FMT;
|
2002-03-04 05:14:51 +01:00
|
|
|
|
check_fpu (SD_);
|
2002-06-13 01:32:05 +02:00
|
|
|
|
StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
|
|
|
|
|
fmt_word));
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//
|
|
|
|
|
// MIPS Architecture:
|
|
|
|
|
//
|
|
|
|
|
// System Control Instruction Set (COP0)
|
|
|
|
|
//
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010000,01000,00000,16.OFFSET:COP0:32::BC0F
|
|
|
|
|
"bc0f <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
|
1999-04-26 20:34:20 +02:00
|
|
|
|
010000,01000,00000,16.OFFSET:COP0:32::BC0F
|
|
|
|
|
"bc0f <OFFSET>"
|
|
|
|
|
// stub needed for eCos as tx39 hardware bug workaround
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
/* do nothing */
|
|
|
|
|
}
|
|
|
|
|
|
1999-04-16 03:35:26 +02:00
|
|
|
|
|
|
|
|
|
010000,01000,00010,16.OFFSET:COP0:32::BC0FL
|
|
|
|
|
"bc0fl <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010000,01000,00001,16.OFFSET:COP0:32::BC0T
|
|
|
|
|
"bc0t <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
|
|
|
|
|
"bc0tl <OFFSET>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
|
2002-03-01 20:55:42 +01:00
|
|
|
|
"cache <OP>, <OFFSET>(r<BASE>)"
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
address_word base = GPR[BASE];
|
|
|
|
|
address_word offset = EXTEND16 (OFFSET);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
2002-03-03 08:36:42 +01:00
|
|
|
|
address_word vaddr = loadstore_ea (SD_, base, offset);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
address_word paddr;
|
|
|
|
|
int uncached;
|
|
|
|
|
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
|
2002-03-02 Chris Demetriou <cgd@broadcom.com>
* mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
Don't split opcode fields by hand, use the opcode field values
provided by igen.
2002-03-03 03:11:23 +01:00
|
|
|
|
CacheOp(OP,vaddr,paddr,instruction_0);
|
1999-04-16 03:35:26 +02:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
|
1999-07-07 19:31:57 +02:00
|
|
|
|
"dmfc0 r<RT>, r<RD>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-07-07 19:31:57 +02:00
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-07-07 19:31:57 +02:00
|
|
|
|
DecodeCoproc (instruction_0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
|
1999-07-07 19:31:57 +02:00
|
|
|
|
"dmtc0 r<RT>, r<RD>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-07-07 19:31:57 +02:00
|
|
|
|
{
|
2002-02-27 Chris Demetriou <cgd@broadcom.com>
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
2002-02-28 03:57:34 +01:00
|
|
|
|
check_u64 (SD_, instruction_0);
|
1999-07-07 19:31:57 +02:00
|
|
|
|
DecodeCoproc (instruction_0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,1,0000000000000000000,011000:COP0:32::ERET
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"eret"
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
{
|
|
|
|
|
if (SR & status_ERL)
|
|
|
|
|
{
|
|
|
|
|
/* Oops, not yet available */
|
|
|
|
|
sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
|
|
|
|
|
NIA = EPC;
|
|
|
|
|
SR &= ~status_ERL;
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
NIA = EPC;
|
|
|
|
|
SR &= ~status_EXL;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
|
|
|
|
|
"mfc0 r<RT>, r<RD> # <REGX>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
2002-02-12 00:35:07 +01:00
|
|
|
|
*r3900:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
TRACE_ALU_INPUT0 ();
|
|
|
|
|
DecodeCoproc (instruction_0);
|
|
|
|
|
TRACE_ALU_RESULT (GPR[RT]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
|
|
|
|
|
"mtc0 r<RT>, r<RD> # <REGX>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
2002-02-12 00:35:07 +01:00
|
|
|
|
*r3900:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
DecodeCoproc (instruction_0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,1,0000000000000000000,010000:COP0:32::RFE
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"rfe"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
2002-02-12 00:35:07 +01:00
|
|
|
|
*r3900:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
{
|
|
|
|
|
DecodeCoproc (instruction_0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
|
|
|
|
|
"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*r3900:
|
|
|
|
|
{
|
|
|
|
|
DecodeCoproc (instruction_0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,1,0000000000000000000,001000:COP0:32::TLBP
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"tlbp"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,1,0000000000000000000,000001:COP0:32::TLBR
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"tlbr"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,1,0000000000000000000,000010:COP0:32::TLBWI
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"tlbwi"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips32:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips32r2:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
|
|
|
|
*mips64:
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
|
|
|
|
*mips64r2:
|
1999-04-16 03:35:26 +02:00
|
|
|
|
*vr4100:
|
|
|
|
|
*vr5000:
|
|
|
|
|
|
|
|
|
|
|
2002-02-10 Chris Demetriou <cgd@broadcom.com>
* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
fields (i.e., add and move commas) so that they more closely
match the MIPS ISA documentation opcode partitioning.
2002-02-11 07:13:49 +01:00
|
|
|
|
010000,1,0000000000000000000,000110:COP0:32::TLBWR
|
1999-04-16 03:35:26 +02:00
|
|
|
|
"tlbwr"
|
2002-02-19 09:10:44 +01:00
|
|
|
|
*mipsI:
|
|
|
|
|
*mipsII:
|
|
|
|
|
*mipsIII:
|
|
|
|
|
*mipsIV:
|
2002-02-27 22:52:52 +01:00
|
|
|
|
*mipsV:
|
2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
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*mips32:
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2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
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*mips32r2:
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2002-03-12 Chris Demetriou <cgd@broadcom.com>
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
2002-03-12 23:53:01 +01:00
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*mips64:
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2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
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*mips64r2:
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1999-04-16 03:35:26 +02:00
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*vr4100:
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*vr5000:
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2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
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:include:::mips3264r2.igen
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1999-04-16 03:35:26 +02:00
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:include:::m16.igen
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2005-06-16 17:15:49 +02:00
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:include:::m16e.igen
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2002-06-02 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips.igen (mdmx): New (pseudo-)model.
* mdmx.c, mdmx.igen: New files.
* Makefile.in (SIM_OBJS): Add mdmx.o.
* sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
New typedefs.
(ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
(MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
(MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
(MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
(MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
(MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
(MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
(MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
(MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
(MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
(MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
(MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
(SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
(qh_fmtsel): New macros.
(_sim_cpu): New member "acc".
(mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
(mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
2002-06-02 09:39:26 +02:00
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:include:::mdmx.igen
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2002-06-14 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
2002-06-14 20:49:09 +02:00
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:include:::mips3d.igen
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2002-06-03 23:00:29 +02:00
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:include:::sb1.igen
|
1999-04-16 03:35:26 +02:00
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:include:::tx.igen
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:include:::vr.igen
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* Makefile.in (SIM_OBJS): Add dsp.o.
(dsp.o): New dependency.
(IGEN_INCLUDE): Add dsp.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
mipsisa64*-*-*): Add dsp to sim_igen_machine.
* configure: Regenerate.
* mips.igen: Add dsp model and include dsp.igen.
(MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
because these instructions are extended in DSP ASE.
* sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
adding 6 DSP accumulator registers and 1 DSP control register.
(AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
DSPCR_CCOND_SMASK): New define.
(DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
* dsp.c, dsp.igen: New files for MIPS DSP ASE.
2005-12-15 00:07:56 +01:00
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:include:::dsp.igen
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[ gas/ChangeLog ]
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
2007-02-20 14:28:56 +01:00
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:include:::dsp2.igen
|
2006-08-29 14:45:26 +02:00
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:include:::smartmips.igen
|
2005-05-26 David Ung <davidu@mips.com>
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
2005-05-26 23:31:57 +02:00
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