binutils-gdb/gdb/riscv-tdep.c

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/* Target-dependent code for the RISC-V architecture, for GDB.
Copyright (C) 2018-2020 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "defs.h"
#include "frame.h"
#include "inferior.h"
#include "symtab.h"
#include "value.h"
#include "gdbcmd.h"
#include "language.h"
#include "gdbcore.h"
#include "symfile.h"
#include "objfiles.h"
#include "gdbtypes.h"
#include "target.h"
#include "arch-utils.h"
#include "regcache.h"
#include "osabi.h"
#include "riscv-tdep.h"
#include "block.h"
#include "reggroups.h"
#include "opcode/riscv.h"
#include "elf/riscv.h"
#include "elf-bfd.h"
#include "symcat.h"
#include "dis-asm.h"
#include "frame-unwind.h"
#include "frame-base.h"
#include "trad-frame.h"
#include "infcall.h"
#include "floatformat.h"
#include "remote.h"
#include "target-descriptions.h"
#include "dwarf2-frame.h"
#include "user-regs.h"
#include "valprint.h"
Rename common to gdbsupport This is the next patch in the ongoing series to move gdbsever to the top level. This patch just renames the "common" directory. The idea is to do this move in two parts: first rename the directory (this patch), then move the directory to the top. This approach makes the patches a bit more tractable. I chose the name "gdbsupport" for the directory. However, as this patch was largely written by sed, we could pick a new name without too much difficulty. Tested by the buildbot. gdb/ChangeLog 2019-07-09 Tom Tromey <tom@tromey.com> * contrib/ari/gdb_ari.sh: Change common to gdbsupport. * configure: Rebuild. * configure.ac: Change common to gdbsupport. * gdbsupport: Rename from common. * acinclude.m4: Change common to gdbsupport. * Makefile.in (CONFIG_SRC_SUBDIR, COMMON_SFILES) (HFILES_NO_SRCDIR, stamp-version, ALLDEPFILES): Change common to gdbsupport. * aarch64-tdep.c, ada-lang.c, ada-lang.h, agent.c, alloc.c, amd64-darwin-tdep.c, amd64-dicos-tdep.c, amd64-fbsd-nat.c, amd64-fbsd-tdep.c, amd64-linux-nat.c, amd64-linux-tdep.c, amd64-nbsd-tdep.c, amd64-obsd-tdep.c, amd64-sol2-tdep.c, amd64-tdep.c, amd64-windows-tdep.c, arch-utils.c, arch/aarch64-insn.c, arch/aarch64.c, arch/aarch64.h, arch/amd64.c, arch/amd64.h, arch/arm-get-next-pcs.c, arch/arm-linux.c, arch/arm.c, arch/i386.c, arch/i386.h, arch/ppc-linux-common.c, arch/riscv.c, arch/riscv.h, arch/tic6x.c, arm-tdep.c, auto-load.c, auxv.c, ax-gdb.c, ax-general.c, ax.h, breakpoint.c, breakpoint.h, btrace.c, btrace.h, build-id.c, build-id.h, c-lang.h, charset.c, charset.h, cli/cli-cmds.c, cli/cli-cmds.h, cli/cli-decode.c, cli/cli-dump.c, cli/cli-option.h, cli/cli-script.c, coff-pe-read.c, command.h, compile/compile-c-support.c, compile/compile-c.h, compile/compile-cplus-symbols.c, compile/compile-cplus-types.c, compile/compile-cplus.h, compile/compile-loc2c.c, compile/compile.c, completer.c, completer.h, contrib/ari/gdb_ari.sh, corefile.c, corelow.c, cp-support.c, cp-support.h, cp-valprint.c, csky-tdep.c, ctf.c, darwin-nat.c, debug.c, defs.h, disasm-selftests.c, disasm.c, disasm.h, dtrace-probe.c, dwarf-index-cache.c, dwarf-index-cache.h, dwarf-index-write.c, dwarf2-frame.c, dwarf2expr.c, dwarf2loc.c, dwarf2read.c, event-loop.c, event-top.c, exceptions.c, exec.c, extension.h, fbsd-nat.c, features/aarch64-core.c, features/aarch64-fpu.c, features/aarch64-pauth.c, features/aarch64-sve.c, features/i386/32bit-avx.c, features/i386/32bit-avx512.c, features/i386/32bit-core.c, features/i386/32bit-linux.c, features/i386/32bit-mpx.c, features/i386/32bit-pkeys.c, features/i386/32bit-segments.c, features/i386/32bit-sse.c, features/i386/64bit-avx.c, features/i386/64bit-avx512.c, features/i386/64bit-core.c, features/i386/64bit-linux.c, features/i386/64bit-mpx.c, features/i386/64bit-pkeys.c, features/i386/64bit-segments.c, features/i386/64bit-sse.c, features/i386/x32-core.c, features/riscv/32bit-cpu.c, features/riscv/32bit-csr.c, features/riscv/32bit-fpu.c, features/riscv/64bit-cpu.c, features/riscv/64bit-csr.c, features/riscv/64bit-fpu.c, features/tic6x-c6xp.c, features/tic6x-core.c, features/tic6x-gp.c, filename-seen-cache.h, findcmd.c, findvar.c, fork-child.c, gcore.c, gdb_bfd.c, gdb_bfd.h, gdb_proc_service.h, gdb_regex.c, gdb_select.h, gdb_usleep.c, gdbarch-selftests.c, gdbthread.h, gdbtypes.h, gnu-nat.c, go32-nat.c, guile/guile.c, guile/scm-ports.c, guile/scm-safe-call.c, guile/scm-type.c, i386-fbsd-nat.c, i386-fbsd-tdep.c, i386-go32-tdep.c, i386-linux-nat.c, i386-linux-tdep.c, i386-tdep.c, i387-tdep.c, ia64-libunwind-tdep.c, ia64-linux-nat.c, inf-child.c, inf-ptrace.c, infcall.c, infcall.h, infcmd.c, inferior-iter.h, inferior.c, inferior.h, inflow.c, inflow.h, infrun.c, infrun.h, inline-frame.c, language.h, linespec.c, linux-fork.c, linux-nat.c, linux-tdep.c, linux-thread-db.c, location.c, machoread.c, macrotab.h, main.c, maint.c, maint.h, memattr.c, memrange.h, mi/mi-cmd-break.h, mi/mi-cmd-env.c, mi/mi-cmd-stack.c, mi/mi-cmd-var.c, mi/mi-interp.c, mi/mi-main.c, mi/mi-parse.h, minsyms.c, mips-linux-tdep.c, namespace.h, nat/aarch64-linux-hw-point.c, nat/aarch64-linux-hw-point.h, nat/aarch64-linux.c, nat/aarch64-sve-linux-ptrace.c, nat/amd64-linux-siginfo.c, nat/fork-inferior.c, nat/linux-btrace.c, nat/linux-btrace.h, nat/linux-namespaces.c, nat/linux-nat.h, nat/linux-osdata.c, nat/linux-personality.c, nat/linux-procfs.c, nat/linux-ptrace.c, nat/linux-ptrace.h, nat/linux-waitpid.c, nat/mips-linux-watch.c, nat/mips-linux-watch.h, nat/ppc-linux.c, nat/x86-dregs.c, nat/x86-dregs.h, nat/x86-linux-dregs.c, nat/x86-linux.c, nto-procfs.c, nto-tdep.c, objfile-flags.h, objfiles.c, objfiles.h, obsd-nat.c, observable.h, osdata.c, p-valprint.c, parse.c, parser-defs.h, ppc-linux-nat.c, printcmd.c, probe.c, proc-api.c, procfs.c, producer.c, progspace.h, psymtab.h, python/py-framefilter.c, python/py-inferior.c, python/py-ref.h, python/py-type.c, python/python.c, record-btrace.c, record-full.c, record.c, record.h, regcache-dump.c, regcache.c, regcache.h, remote-fileio.c, remote-fileio.h, remote-sim.c, remote.c, riscv-tdep.c, rs6000-aix-tdep.c, rust-exp.y, s12z-tdep.c, selftest-arch.c, ser-base.c, ser-event.c, ser-pipe.c, ser-tcp.c, ser-unix.c, skip.c, solib-aix.c, solib-target.c, solib.c, source-cache.c, source.c, source.h, sparc-nat.c, spu-linux-nat.c, stack.c, stap-probe.c, symfile-add-flags.h, symfile.c, symfile.h, symtab.c, symtab.h, target-descriptions.c, target-descriptions.h, target-memory.c, target.c, target.h, target/waitstatus.c, target/waitstatus.h, thread-iter.h, thread.c, tilegx-tdep.c, top.c, top.h, tracefile-tfile.c, tracefile.c, tracepoint.c, tracepoint.h, tui/tui-io.c, ui-file.c, ui-out.h, unittests/array-view-selftests.c, unittests/child-path-selftests.c, unittests/cli-utils-selftests.c, unittests/common-utils-selftests.c, unittests/copy_bitwise-selftests.c, unittests/environ-selftests.c, unittests/format_pieces-selftests.c, unittests/function-view-selftests.c, unittests/lookup_name_info-selftests.c, unittests/memory-map-selftests.c, unittests/memrange-selftests.c, unittests/mkdir-recursive-selftests.c, unittests/observable-selftests.c, unittests/offset-type-selftests.c, unittests/optional-selftests.c, unittests/parse-connection-spec-selftests.c, unittests/ptid-selftests.c, unittests/rsp-low-selftests.c, unittests/scoped_fd-selftests.c, unittests/scoped_mmap-selftests.c, unittests/scoped_restore-selftests.c, unittests/string_view-selftests.c, unittests/style-selftests.c, unittests/tracepoint-selftests.c, unittests/unpack-selftests.c, unittests/utils-selftests.c, unittests/xml-utils-selftests.c, utils.c, utils.h, valarith.c, valops.c, valprint.c, value.c, value.h, varobj.c, varobj.h, windows-nat.c, x86-linux-nat.c, xml-support.c, xml-support.h, xml-tdesc.h, xstormy16-tdep.c, xtensa-linux-nat.c, dwarf2read.h: Change common to gdbsupport. gdb/gdbserver/ChangeLog 2019-07-09 Tom Tromey <tom@tromey.com> * configure: Rebuild. * configure.ac: Change common to gdbsupport. * acinclude.m4: Change common to gdbsupport. * Makefile.in (SFILES, OBS, GDBREPLAY_OBS, IPA_OBJS) (version-generated.c, gdbsupport/%-ipa.o, gdbsupport/%.o): Change common to gdbsupport. * ax.c, event-loop.c, fork-child.c, gdb_proc_service.h, gdbreplay.c, gdbthread.h, hostio-errno.c, hostio.c, i387-fp.c, inferiors.c, inferiors.h, linux-aarch64-tdesc-selftest.c, linux-amd64-ipa.c, linux-i386-ipa.c, linux-low.c, linux-tic6x-low.c, linux-x86-low.c, linux-x86-tdesc-selftest.c, linux-x86-tdesc.c, lynx-i386-low.c, lynx-low.c, mem-break.h, nto-x86-low.c, regcache.c, regcache.h, remote-utils.c, server.c, server.h, spu-low.c, symbol.c, target.h, tdesc.c, tdesc.h, thread-db.c, tracepoint.c, win32-i386-low.c, win32-low.c: Change common to gdbsupport.
2019-05-06 04:29:24 +02:00
#include "gdbsupport/common-defs.h"
#include "opcode/riscv-opc.h"
#include "cli/cli-decode.h"
Convert observers to C++ This converts observers from using a special source-generating script to be plain C++. This version of the patch takes advantage of C++11 by using std::function and variadic templates; incorporates Pedro's patches; and renames the header file to "observable.h" (this change eliminates the need for a clean rebuild). Note that Pedro's patches used a template lambda in tui-hooks.c, but this failed to compile on some buildbot instances (presumably due to differing C++ versions); I replaced this with an ordinary template function. Regression tested on the buildbot. gdb/ChangeLog 2018-03-19 Pedro Alves <palves@redhat.com> Tom Tromey <tom@tromey.com> * unittests/observable-selftests.c: New file. * common/observable.h: New file. * observable.h: New file. * ada-lang.c, ada-tasks.c, agent.c, aix-thread.c, annotate.c, arm-tdep.c, auto-load.c, auxv.c, break-catch-syscall.c, breakpoint.c, bsd-uthread.c, cli/cli-interp.c, cli/cli-setshow.c, corefile.c, dummy-frame.c, event-loop.c, event-top.c, exec.c, extension.c, frame.c, gdbarch.c, guile/scm-breakpoint.c, infcall.c, infcmd.c, inferior.c, inflow.c, infrun.c, jit.c, linux-tdep.c, linux-thread-db.c, m68klinux-tdep.c, mi/mi-cmd-break.c, mi/mi-interp.c, mi/mi-main.c, objfiles.c, ppc-linux-nat.c, ppc-linux-tdep.c, printcmd.c, procfs.c, python/py-breakpoint.c, python/py-finishbreakpoint.c, python/py-inferior.c, python/py-unwind.c, ravenscar-thread.c, record-btrace.c, record-full.c, record.c, regcache.c, remote.c, riscv-tdep.c, sol-thread.c, solib-aix.c, solib-spu.c, solib.c, spu-multiarch.c, spu-tdep.c, stack.c, symfile-mem.c, symfile.c, symtab.c, thread.c, top.c, tracepoint.c, tui/tui-hooks.c, tui/tui-interp.c, valops.c: Update all users. * tui/tui-hooks.c (tui_bp_created_observer) (tui_bp_deleted_observer, tui_bp_modified_observer) (tui_inferior_exit_observer, tui_before_prompt_observer) (tui_normal_stop_observer, tui_register_changed_observer): Remove. (tui_observers_token): New global. (attach_or_detach, tui_attach_detach_observers): New functions. (tui_install_hooks, tui_remove_hooks): Use tui_attach_detach_observers. * record-btrace.c (record_btrace_thread_observer): Remove. (record_btrace_thread_observer_token): New global. * observer.sh: Remove. * observer.c: Rename to observable.c. * observable.c (namespace gdb_observers): Define new objects. (observer_debug): Move into gdb_observers namespace. (struct observer, struct observer_list, xalloc_observer_list_node) (xfree_observer_list_node, generic_observer_attach) (generic_observer_detach, generic_observer_notify): Remove. (_initialize_observer): Update. Don't include observer.inc. * Makefile.in (generated_files): Remove observer.h, observer.inc. (clean mostlyclean): Likewise. (observer.h, observer.inc): Remove targets. (SUBDIR_UNITTESTS_SRCS): Add observable-selftests.c. (COMMON_SFILES): Use observable.c, not observer.c. * .gitignore: Remove observer.h. gdb/doc/ChangeLog 2018-03-19 Tom Tromey <tom@tromey.com> * observer.texi: Remove. gdb/testsuite/ChangeLog 2018-03-19 Tom Tromey <tom@tromey.com> * gdb.gdb/observer.exp: Remove.
2016-10-02 18:50:20 +02:00
#include "observable.h"
#include "prologue-value.h"
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
#include "arch/riscv.h"
#include "riscv-ravenscar-thread.h"
/* The stack must be 16-byte aligned. */
#define SP_ALIGNMENT 16
/* The biggest alignment that the target supports. */
#define BIGGEST_ALIGNMENT 16
/* Define a series of is_XXX_insn functions to check if the value INSN
is an instance of instruction XXX. */
#define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
static inline bool is_ ## INSN_NAME ## _insn (long insn) \
{ \
return (insn & INSN_MASK) == INSN_MATCH; \
}
#include "opcode/riscv-opc.h"
#undef DECLARE_INSN
/* Cached information about a frame. */
struct riscv_unwind_cache
{
/* The register from which we can calculate the frame base. This is
usually $sp or $fp. */
int frame_base_reg;
/* The offset from the current value in register FRAME_BASE_REG to the
actual frame base address. */
int frame_base_offset;
/* Information about previous register values. */
struct trad_frame_saved_reg *regs;
/* The id for this frame. */
struct frame_id this_id;
/* The base (stack) address for this frame. This is the stack pointer
value on entry to this frame before any adjustments are made. */
CORE_ADDR frame_base;
};
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* RISC-V specific register group for CSRs. */
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
static reggroup *csr_reggroup = NULL;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* A set of registers that we expect to find in a tdesc_feature. These
are use in RISCV_GDBARCH_INIT when processing the target description. */
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
struct riscv_register_feature
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Information for a single register. */
struct register_info
{
/* The GDB register number for this register. */
int regnum;
/* List of names for this register. The first name in this list is the
preferred name, the name GDB should use when describing this
register. */
std::vector <const char *> names;
/* When true this register is required in this feature set. */
bool required_p;
};
/* The name for this feature. This is the name used to find this feature
within the target description. */
const char *name;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* List of all the registers that we expect that we might find in this
register set. */
std::vector <struct register_info> registers;
};
/* The general x-registers feature set. */
static const struct riscv_register_feature riscv_xreg_feature =
{
"org.gnu.gdb.riscv.cpu",
{
{ RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true },
{ RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true },
{ RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, true },
{ RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, true },
{ RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, true },
{ RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, true },
{ RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, true },
{ RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, true },
{ RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, true },
{ RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, true },
{ RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, true },
{ RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, true },
{ RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, true },
{ RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, true },
{ RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, true },
{ RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, true },
{ RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, true },
{ RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, true },
{ RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, true },
{ RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, true },
{ RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, true },
{ RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, true },
{ RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, true },
{ RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, true },
{ RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, true },
{ RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, true },
{ RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, true },
{ RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, true },
{ RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, true },
{ RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, true },
{ RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, true },
{ RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, true },
{ RISCV_ZERO_REGNUM + 32, { "pc" }, true }
}
};
/* The f-registers feature set. */
static const struct riscv_register_feature riscv_freg_feature =
{
"org.gnu.gdb.riscv.fpu",
{
{ RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, true },
{ RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, true },
{ RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, true },
{ RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, true },
{ RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, true },
{ RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
{ RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
{ RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
{ RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8" }, true },
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
{ RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
{ RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
{ RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },
{ RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, true },
{ RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, true },
{ RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, true },
{ RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, true },
{ RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, true },
{ RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, true },
{ RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, true },
{ RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, true },
{ RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, true },
{ RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, true },
{ RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, true },
{ RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, true },
{ RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, true },
{ RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, true },
{ RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, true },
{ RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, true },
{ RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, true },
{ RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, true },
{ RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, true },
{ RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, true },
{ RISCV_CSR_FFLAGS_REGNUM, { "fflags" }, true },
{ RISCV_CSR_FRM_REGNUM, { "frm" }, true },
{ RISCV_CSR_FCSR_REGNUM, { "fcsr" }, true },
}
};
/* Set of virtual registers. These are not physical registers on the
hardware, but might be available from the target. These are not pseudo
registers, reading these really does result in a register read from the
target, it is just that there might not be a physical register backing
the result. */
static const struct riscv_register_feature riscv_virtual_feature =
{
"org.gnu.gdb.riscv.virtual",
{
{ RISCV_PRIV_REGNUM, { "priv" }, false }
}
};
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Feature set for CSRs. This set is NOT constant as the register names
list for each register is not complete. The aliases are computed
during RISCV_CREATE_CSR_ALIASES. */
static struct riscv_register_feature riscv_csr_feature =
{
"org.gnu.gdb.riscv.csr",
{
#define DECLARE_CSR(NAME,VALUE) \
{ RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
};
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
to the name list for each register. */
static void
riscv_create_csr_aliases ()
{
for (auto &reg : riscv_csr_feature.registers)
{
int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
const char *alias = xstrprintf ("csr%d", csr_num);
reg.names.push_back (alias);
}
}
/* Controls whether we place compressed breakpoints or not. When in auto
mode GDB tries to determine if the target supports compressed
breakpoints, and uses them if it does. */
static enum auto_boolean use_compressed_breakpoints;
/* The show callback for 'show riscv use-compressed-breakpoints'. */
static void
show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
struct cmd_list_element *c,
const char *value)
{
fprintf_filtered (file,
_("Debugger's use of compressed breakpoints is set "
Use the existing instruction to determine the RISC-V breakpoint kind. RISC-V supports instructions of varying lengths. Standard existing instructions in the base ISA are 4 bytes in length, but the 'C' extension adds support for compressed, 2 byte instructions. RISC-V supports two different breakpoint instructions: EBREAK is a 4 byte instruction in the base ISA, and C.EBREAK is a 2 byte instruction only available on processors implementing the 'C' extension. Using EBREAK to set breakpoints on compressed instructions causes problems as the second half of EBREAK will overwrite the first 2 bytes of the following instruction breaking other threads in the process if their PC is the following instruction. Thus, breakpoints on compressed instructions need to use C.EBREAK instead of EBREAK. Previously, the riscv architecture checked the MISA register to determine if the 'C' extension was available. If so, it used C.EBREAK for all breakpoints. However, the MISA register is not necessarily available to supervisor mode operating systems. While native targets could provide a fake MISA register value, this patch instead examines the existing instruction at a breakpoint target to determine which breakpoint instruction to use. If the existing instruction is a compressed instruction, C.EBREAK is used, otherwise EBREAK is used. gdb/ChangeLog: * disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to case with explicit breakpoint kind. * riscv-tdep.c (show_use_compressed_breakpoints): Remove 'additional_info' and related logic. (riscv_debug_breakpoints): New variable. (riscv_breakpoint_kind_from_pc): Use the length of the existing instruction to determine the breakpoint kind. (_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints' flag. Update description of 'set/show riscv use-compressed-breakpoints' flag.
2018-09-28 23:15:54 +02:00
"to %s.\n"), value);
}
/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
static struct cmd_list_element *setriscvcmdlist = NULL;
static struct cmd_list_element *showriscvcmdlist = NULL;
/* The show callback for the 'show riscv' prefix command. */
static void
show_riscv_command (const char *args, int from_tty)
{
help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
}
/* The set callback for the 'set riscv' prefix command. */
static void
set_riscv_command (const char *args, int from_tty)
{
printf_unfiltered
(_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
}
/* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
static struct cmd_list_element *setdebugriscvcmdlist = NULL;
static struct cmd_list_element *showdebugriscvcmdlist = NULL;
/* The show callback for the 'show debug riscv' prefix command. */
static void
show_debug_riscv_command (const char *args, int from_tty)
{
help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
}
/* The set callback for the 'set debug riscv' prefix command. */
static void
set_debug_riscv_command (const char *args, int from_tty)
{
printf_unfiltered
(_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
}
/* The show callback for all 'show debug riscv VARNAME' variables. */
static void
show_riscv_debug_variable (struct ui_file *file, int from_tty,
struct cmd_list_element *c,
const char *value)
{
fprintf_filtered (file,
_("RiscV debug variable `%s' is set to: %s\n"),
c->name, value);
}
Use the existing instruction to determine the RISC-V breakpoint kind. RISC-V supports instructions of varying lengths. Standard existing instructions in the base ISA are 4 bytes in length, but the 'C' extension adds support for compressed, 2 byte instructions. RISC-V supports two different breakpoint instructions: EBREAK is a 4 byte instruction in the base ISA, and C.EBREAK is a 2 byte instruction only available on processors implementing the 'C' extension. Using EBREAK to set breakpoints on compressed instructions causes problems as the second half of EBREAK will overwrite the first 2 bytes of the following instruction breaking other threads in the process if their PC is the following instruction. Thus, breakpoints on compressed instructions need to use C.EBREAK instead of EBREAK. Previously, the riscv architecture checked the MISA register to determine if the 'C' extension was available. If so, it used C.EBREAK for all breakpoints. However, the MISA register is not necessarily available to supervisor mode operating systems. While native targets could provide a fake MISA register value, this patch instead examines the existing instruction at a breakpoint target to determine which breakpoint instruction to use. If the existing instruction is a compressed instruction, C.EBREAK is used, otherwise EBREAK is used. gdb/ChangeLog: * disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to case with explicit breakpoint kind. * riscv-tdep.c (show_use_compressed_breakpoints): Remove 'additional_info' and related logic. (riscv_debug_breakpoints): New variable. (riscv_breakpoint_kind_from_pc): Use the length of the existing instruction to determine the breakpoint kind. (_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints' flag. Update description of 'set/show riscv use-compressed-breakpoints' flag.
2018-09-28 23:15:54 +02:00
/* When this is set to non-zero debugging information about breakpoint
kinds will be printed. */
static unsigned int riscv_debug_breakpoints = 0;
/* When this is set to non-zero debugging information about inferior calls
will be printed. */
static unsigned int riscv_debug_infcall = 0;
/* When this is set to non-zero debugging information about stack unwinding
will be printed. */
static unsigned int riscv_debug_unwinder = 0;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* When this is set to non-zero debugging information about gdbarch
initialisation will be printed. */
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
static unsigned int riscv_debug_gdbarch = 0;
/* See riscv-tdep.h. */
int
riscv_isa_xlen (struct gdbarch *gdbarch)
{
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
return gdbarch_tdep (gdbarch)->isa_features.xlen;
}
/* See riscv-tdep.h. */
int
riscv_abi_xlen (struct gdbarch *gdbarch)
{
return gdbarch_tdep (gdbarch)->abi_features.xlen;
}
/* See riscv-tdep.h. */
int
riscv_isa_flen (struct gdbarch *gdbarch)
{
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
return gdbarch_tdep (gdbarch)->isa_features.flen;
}
/* See riscv-tdep.h. */
int
riscv_abi_flen (struct gdbarch *gdbarch)
{
return gdbarch_tdep (gdbarch)->abi_features.flen;
}
/* Return true if the target for GDBARCH has floating point hardware. */
static bool
riscv_has_fp_regs (struct gdbarch *gdbarch)
{
return (riscv_isa_flen (gdbarch) > 0);
}
/* Return true if GDBARCH is using any of the floating point hardware ABIs. */
static bool
riscv_has_fp_abi (struct gdbarch *gdbarch)
{
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
return gdbarch_tdep (gdbarch)->abi_features.flen > 0;
}
/* Return true if REGNO is a floating pointer register. */
static bool
riscv_is_fp_regno_p (int regno)
{
return (regno >= RISCV_FIRST_FP_REGNUM
&& regno <= RISCV_LAST_FP_REGNUM);
}
/* Implement the breakpoint_kind_from_pc gdbarch method. */
static int
riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
{
if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
{
bool unaligned_p = false;
Use the existing instruction to determine the RISC-V breakpoint kind. RISC-V supports instructions of varying lengths. Standard existing instructions in the base ISA are 4 bytes in length, but the 'C' extension adds support for compressed, 2 byte instructions. RISC-V supports two different breakpoint instructions: EBREAK is a 4 byte instruction in the base ISA, and C.EBREAK is a 2 byte instruction only available on processors implementing the 'C' extension. Using EBREAK to set breakpoints on compressed instructions causes problems as the second half of EBREAK will overwrite the first 2 bytes of the following instruction breaking other threads in the process if their PC is the following instruction. Thus, breakpoints on compressed instructions need to use C.EBREAK instead of EBREAK. Previously, the riscv architecture checked the MISA register to determine if the 'C' extension was available. If so, it used C.EBREAK for all breakpoints. However, the MISA register is not necessarily available to supervisor mode operating systems. While native targets could provide a fake MISA register value, this patch instead examines the existing instruction at a breakpoint target to determine which breakpoint instruction to use. If the existing instruction is a compressed instruction, C.EBREAK is used, otherwise EBREAK is used. gdb/ChangeLog: * disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to case with explicit breakpoint kind. * riscv-tdep.c (show_use_compressed_breakpoints): Remove 'additional_info' and related logic. (riscv_debug_breakpoints): New variable. (riscv_breakpoint_kind_from_pc): Use the length of the existing instruction to determine the breakpoint kind. (_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints' flag. Update description of 'set/show riscv use-compressed-breakpoints' flag.
2018-09-28 23:15:54 +02:00
gdb_byte buf[1];
/* Some targets don't support unaligned reads. The address can only
be unaligned if the C extension is supported. So it is safe to
use a compressed breakpoint in this case. */
if (*pcptr & 0x2)
unaligned_p = true;
else
{
/* Read the opcode byte to determine the instruction length. If
the read fails this may be because we tried to set the
breakpoint at an invalid address, in this case we provide a
fake result which will give a breakpoint length of 4.
Hopefully when we try to actually insert the breakpoint we
will see a failure then too which will be reported to the
user. */
if (target_read_code (*pcptr, buf, 1) == -1)
buf[0] = 0;
read_code (*pcptr, buf, 1);
}
Use the existing instruction to determine the RISC-V breakpoint kind. RISC-V supports instructions of varying lengths. Standard existing instructions in the base ISA are 4 bytes in length, but the 'C' extension adds support for compressed, 2 byte instructions. RISC-V supports two different breakpoint instructions: EBREAK is a 4 byte instruction in the base ISA, and C.EBREAK is a 2 byte instruction only available on processors implementing the 'C' extension. Using EBREAK to set breakpoints on compressed instructions causes problems as the second half of EBREAK will overwrite the first 2 bytes of the following instruction breaking other threads in the process if their PC is the following instruction. Thus, breakpoints on compressed instructions need to use C.EBREAK instead of EBREAK. Previously, the riscv architecture checked the MISA register to determine if the 'C' extension was available. If so, it used C.EBREAK for all breakpoints. However, the MISA register is not necessarily available to supervisor mode operating systems. While native targets could provide a fake MISA register value, this patch instead examines the existing instruction at a breakpoint target to determine which breakpoint instruction to use. If the existing instruction is a compressed instruction, C.EBREAK is used, otherwise EBREAK is used. gdb/ChangeLog: * disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to case with explicit breakpoint kind. * riscv-tdep.c (show_use_compressed_breakpoints): Remove 'additional_info' and related logic. (riscv_debug_breakpoints): New variable. (riscv_breakpoint_kind_from_pc): Use the length of the existing instruction to determine the breakpoint kind. (_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints' flag. Update description of 'set/show riscv use-compressed-breakpoints' flag.
2018-09-28 23:15:54 +02:00
if (riscv_debug_breakpoints)
{
const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
? "C.EBREAK" : "EBREAK");
fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
bp, paddress (gdbarch, *pcptr));
if (unaligned_p)
fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
else
fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
riscv_insn_length (buf[0]));
}
if (unaligned_p || riscv_insn_length (buf[0]) == 2)
return 2;
else
return 4;
}
else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
return 2;
else
return 4;
}
/* Implement the sw_breakpoint_from_kind gdbarch method. */
static const gdb_byte *
riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
{
static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
*size = kind;
switch (kind)
{
case 2:
return c_ebreak;
case 4:
return ebreak;
default:
gdb_assert_not_reached (_("unhandled breakpoint kind"));
}
}
/* Callback function for user_reg_add. */
static struct value *
value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
{
const int *reg_p = (const int *) baton;
return value_of_register (*reg_p, frame);
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Implement the register_name gdbarch method. This is used instead of
the function supplied by calling TDESC_USE_REGISTERS so that we can
ensure the preferred names are offered. */
static const char *
riscv_register_name (struct gdbarch *gdbarch, int regnum)
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Lookup the name through the target description. If we get back NULL
then this is an unknown register. If we do get a name back then we
look up the registers preferred name below. */
const char *name = tdesc_register_name (gdbarch, regnum);
if (name == NULL || name[0] == '\0')
return NULL;
if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM)
{
gdb_assert (regnum < riscv_xreg_feature.registers.size ());
return riscv_xreg_feature.registers[regnum].names[0];
}
if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
if (riscv_has_fp_regs (gdbarch))
{
regnum -= RISCV_FIRST_FP_REGNUM;
gdb_assert (regnum < riscv_freg_feature.registers.size ());
return riscv_freg_feature.registers[regnum].names[0];
}
else
return NULL;
}
/* Check that there's no gap between the set of registers handled above,
and the set of registers handled next. */
gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
{
#define DECLARE_CSR(NAME,VALUE) \
case RISCV_ ## VALUE ## _REGNUM: return # NAME;
switch (regnum)
{
#include "opcode/riscv-opc.h"
}
#undef DECLARE_CSR
}
if (regnum == RISCV_PRIV_REGNUM)
return "priv";
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* It is possible that that the target provides some registers that GDB
is unaware of, in that case just return the NAME from the target
description. */
return name;
}
/* Construct a type for 64-bit FP registers. */
static struct type *
riscv_fpreg_d_type (struct gdbarch *gdbarch)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
if (tdep->riscv_fpreg_d_type == nullptr)
{
const struct builtin_type *bt = builtin_type (gdbarch);
/* The type we're building is this: */
#if 0
union __gdb_builtin_type_fpreg_d
{
float f;
double d;
};
#endif
struct type *t;
t = arch_composite_type (gdbarch,
"__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
append_composite_type_field (t, "float", bt->builtin_float);
append_composite_type_field (t, "double", bt->builtin_double);
TYPE_VECTOR (t) = 1;
TYPE_NAME (t) = "builtin_type_fpreg_d";
tdep->riscv_fpreg_d_type = t;
}
return tdep->riscv_fpreg_d_type;
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Implement the register_type gdbarch method. This is installed as an
for the override setup by TDESC_USE_REGISTERS, for most registers we
delegate the type choice to the target description, but for a few
registers we try to improve the types if the target description has
taken a simplistic approach. */
static struct type *
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
riscv_register_type (struct gdbarch *gdbarch, int regnum)
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
struct type *type = tdesc_register_type (gdbarch, regnum);
int xlen = riscv_isa_xlen (gdbarch);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* We want to perform some specific type "fixes" in cases where we feel
that we really can do better than the target description. For all
other cases we just return what the target description says. */
if (riscv_is_fp_regno_p (regnum))
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* This spots the case for RV64 where the double is defined as
either 'ieee_double' or 'float' (which is the generic name that
converts to 'double' on 64-bit). In these cases its better to
present the registers using a union type. */
int flen = riscv_isa_flen (gdbarch);
if (flen == 8
&& TYPE_CODE (type) == TYPE_CODE_FLT
&& TYPE_LENGTH (type) == flen
&& (strcmp (TYPE_NAME (type), "builtin_type_ieee_double") == 0
|| strcmp (TYPE_NAME (type), "double") == 0))
type = riscv_fpreg_d_type (gdbarch);
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
if ((regnum == gdbarch_pc_regnum (gdbarch)
|| regnum == RISCV_RA_REGNUM
|| regnum == RISCV_FP_REGNUM
|| regnum == RISCV_SP_REGNUM
|| regnum == RISCV_GP_REGNUM
|| regnum == RISCV_TP_REGNUM)
&& TYPE_CODE (type) == TYPE_CODE_INT
&& TYPE_LENGTH (type) == xlen)
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* This spots the case where some interesting registers are defined
as simple integers of the expected size, we force these registers
to be pointers as we believe that is more useful. */
if (regnum == gdbarch_pc_regnum (gdbarch)
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
|| regnum == RISCV_RA_REGNUM)
type = builtin_type (gdbarch)->builtin_func_ptr;
else if (regnum == RISCV_FP_REGNUM
|| regnum == RISCV_SP_REGNUM
|| regnum == RISCV_GP_REGNUM
|| regnum == RISCV_TP_REGNUM)
type = builtin_type (gdbarch)->builtin_data_ptr;
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
return type;
}
/* Helper for riscv_print_registers_info, prints info for a single register
REGNUM. */
static void
riscv_print_one_register_info (struct gdbarch *gdbarch,
struct ui_file *file,
struct frame_info *frame,
int regnum)
{
const char *name = gdbarch_register_name (gdbarch, regnum);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
struct value *val;
struct type *regtype;
int print_raw_format;
enum tab_stops { value_column_1 = 15 };
fputs_filtered (name, file);
print_spaces_filtered (value_column_1 - strlen (name), file);
Rewrite TRY/CATCH This rewrites gdb's TRY/CATCH to plain C++ try/catch. The patch was largely written by script, though one change (to a comment in common-exceptions.h) was reverted by hand. gdb/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * xml-support.c: Use C++ exception handling. * x86-linux-nat.c: Use C++ exception handling. * windows-nat.c: Use C++ exception handling. * varobj.c: Use C++ exception handling. * value.c: Use C++ exception handling. * valprint.c: Use C++ exception handling. * valops.c: Use C++ exception handling. * unittests/parse-connection-spec-selftests.c: Use C++ exception handling. * unittests/cli-utils-selftests.c: Use C++ exception handling. * typeprint.c: Use C++ exception handling. * tui/tui.c: Use C++ exception handling. * tracefile-tfile.c: Use C++ exception handling. * top.c: Use C++ exception handling. * thread.c: Use C++ exception handling. * target.c: Use C++ exception handling. * symmisc.c: Use C++ exception handling. * symfile-mem.c: Use C++ exception handling. * stack.c: Use C++ exception handling. * sparc64-linux-tdep.c: Use C++ exception handling. * solib.c: Use C++ exception handling. * solib-svr4.c: Use C++ exception handling. * solib-spu.c: Use C++ exception handling. * solib-frv.c: Use C++ exception handling. * solib-dsbt.c: Use C++ exception handling. * selftest-arch.c: Use C++ exception handling. * s390-tdep.c: Use C++ exception handling. * rust-lang.c: Use C++ exception handling. * rust-exp.y: Use C++ exception handling. * rs6000-tdep.c: Use C++ exception handling. * rs6000-aix-tdep.c: Use C++ exception handling. * riscv-tdep.c: Use C++ exception handling. * remote.c: Use C++ exception handling. * remote-fileio.c: Use C++ exception handling. * record-full.c: Use C++ exception handling. * record-btrace.c: Use C++ exception handling. * python/python.c: Use C++ exception handling. * python/py-value.c: Use C++ exception handling. * python/py-utils.c: Use C++ exception handling. * python/py-unwind.c: Use C++ exception handling. * python/py-type.c: Use C++ exception handling. * python/py-symbol.c: Use C++ exception handling. * python/py-record.c: Use C++ exception handling. * python/py-record-btrace.c: Use C++ exception handling. * python/py-progspace.c: Use C++ exception handling. * python/py-prettyprint.c: Use C++ exception handling. * python/py-param.c: Use C++ exception handling. * python/py-objfile.c: Use C++ exception handling. * python/py-linetable.c: Use C++ exception handling. * python/py-lazy-string.c: Use C++ exception handling. * python/py-infthread.c: Use C++ exception handling. * python/py-inferior.c: Use C++ exception handling. * python/py-gdb-readline.c: Use C++ exception handling. * python/py-framefilter.c: Use C++ exception handling. * python/py-frame.c: Use C++ exception handling. * python/py-finishbreakpoint.c: Use C++ exception handling. * python/py-cmd.c: Use C++ exception handling. * python/py-breakpoint.c: Use C++ exception handling. * python/py-arch.c: Use C++ exception handling. * printcmd.c: Use C++ exception handling. * ppc-linux-tdep.c: Use C++ exception handling. * parse.c: Use C++ exception handling. * p-valprint.c: Use C++ exception handling. * objc-lang.c: Use C++ exception handling. * mi/mi-main.c: Use C++ exception handling. * mi/mi-interp.c: Use C++ exception handling. * mi/mi-cmd-stack.c: Use C++ exception handling. * mi/mi-cmd-break.c: Use C++ exception handling. * main.c: Use C++ exception handling. * linux-thread-db.c: Use C++ exception handling. * linux-tdep.c: Use C++ exception handling. * linux-nat.c: Use C++ exception handling. * linux-fork.c: Use C++ exception handling. * linespec.c: Use C++ exception handling. * language.c: Use C++ exception handling. * jit.c: Use C++ exception handling. * infrun.c: Use C++ exception handling. * infcmd.c: Use C++ exception handling. * infcall.c: Use C++ exception handling. * inf-loop.c: Use C++ exception handling. * i386-tdep.c: Use C++ exception handling. * i386-linux-tdep.c: Use C++ exception handling. * guile/scm-value.c: Use C++ exception handling. * guile/scm-type.c: Use C++ exception handling. * guile/scm-symtab.c: Use C++ exception handling. * guile/scm-symbol.c: Use C++ exception handling. * guile/scm-pretty-print.c: Use C++ exception handling. * guile/scm-ports.c: Use C++ exception handling. * guile/scm-param.c: Use C++ exception handling. * guile/scm-math.c: Use C++ exception handling. * guile/scm-lazy-string.c: Use C++ exception handling. * guile/scm-frame.c: Use C++ exception handling. * guile/scm-disasm.c: Use C++ exception handling. * guile/scm-cmd.c: Use C++ exception handling. * guile/scm-breakpoint.c: Use C++ exception handling. * guile/scm-block.c: Use C++ exception handling. * guile/guile-internal.h: Use C++ exception handling. * gnu-v3-abi.c: Use C++ exception handling. * gdbtypes.c: Use C++ exception handling. * frame.c: Use C++ exception handling. * frame-unwind.c: Use C++ exception handling. * fbsd-tdep.c: Use C++ exception handling. * f-valprint.c: Use C++ exception handling. * exec.c: Use C++ exception handling. * event-top.c: Use C++ exception handling. * event-loop.c: Use C++ exception handling. * eval.c: Use C++ exception handling. * dwarf2read.c: Use C++ exception handling. * dwarf2loc.c: Use C++ exception handling. * dwarf2-frame.c: Use C++ exception handling. * dwarf2-frame-tailcall.c: Use C++ exception handling. * dwarf-index-write.c: Use C++ exception handling. * dwarf-index-cache.c: Use C++ exception handling. * dtrace-probe.c: Use C++ exception handling. * disasm-selftests.c: Use C++ exception handling. * darwin-nat.c: Use C++ exception handling. * cp-valprint.c: Use C++ exception handling. * cp-support.c: Use C++ exception handling. * cp-abi.c: Use C++ exception handling. * corelow.c: Use C++ exception handling. * completer.c: Use C++ exception handling. * compile/compile-object-run.c: Use C++ exception handling. * compile/compile-object-load.c: Use C++ exception handling. * compile/compile-cplus-symbols.c: Use C++ exception handling. * compile/compile-c-symbols.c: Use C++ exception handling. * common/selftest.c: Use C++ exception handling. * common/new-op.c: Use C++ exception handling. * cli/cli-script.c: Use C++ exception handling. * cli/cli-interp.c: Use C++ exception handling. * cli/cli-cmds.c: Use C++ exception handling. * c-varobj.c: Use C++ exception handling. * btrace.c: Use C++ exception handling. * breakpoint.c: Use C++ exception handling. * break-catch-throw.c: Use C++ exception handling. * arch-utils.c: Use C++ exception handling. * amd64-tdep.c: Use C++ exception handling. * ada-valprint.c: Use C++ exception handling. * ada-typeprint.c: Use C++ exception handling. * ada-lang.c: Use C++ exception handling. * aarch64-tdep.c: Use C++ exception handling. gdb/gdbserver/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * server.c: Use C++ exception handling. * linux-low.c: Use C++ exception handling. * gdbreplay.c: Use C++ exception handling.
2019-04-04 00:02:42 +02:00
try
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
{
val = value_of_register (regnum, frame);
regtype = value_type (val);
}
Rename gdb exception types This renames the gdb exception types. The old types were only needed due to the macros in common-exception.h that are now gone. The intermediate layer of gdb_exception_RETURN_MASK_ALL did not seem needed, so this patch removes it entirely. gdb/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * common/common-exceptions.h (gdb_exception_RETURN_MASK_ALL): Remove. (gdb_exception_error): Rename from gdb_exception_RETURN_MASK_ERROR. (gdb_exception_quit): Rename from gdb_exception_RETURN_MASK_QUIT. (gdb_quit_bad_alloc): Update. * aarch64-tdep.c: Update. * ada-lang.c: Update. * ada-typeprint.c: Update. * ada-valprint.c: Update. * amd64-tdep.c: Update. * arch-utils.c: Update. * break-catch-throw.c: Update. * breakpoint.c: Update. * btrace.c: Update. * c-varobj.c: Update. * cli/cli-cmds.c: Update. * cli/cli-interp.c: Update. * cli/cli-script.c: Update. * common/common-exceptions.c: Update. * common/new-op.c: Update. * common/selftest.c: Update. * compile/compile-c-symbols.c: Update. * compile/compile-cplus-symbols.c: Update. * compile/compile-object-load.c: Update. * compile/compile-object-run.c: Update. * completer.c: Update. * corelow.c: Update. * cp-abi.c: Update. * cp-support.c: Update. * cp-valprint.c: Update. * darwin-nat.c: Update. * disasm-selftests.c: Update. * dtrace-probe.c: Update. * dwarf-index-cache.c: Update. * dwarf-index-write.c: Update. * dwarf2-frame-tailcall.c: Update. * dwarf2-frame.c: Update. * dwarf2loc.c: Update. * dwarf2read.c: Update. * eval.c: Update. * event-loop.c: Update. * event-top.c: Update. * exec.c: Update. * f-valprint.c: Update. * fbsd-tdep.c: Update. * frame-unwind.c: Update. * frame.c: Update. * gdbtypes.c: Update. * gnu-v3-abi.c: Update. * guile/guile-internal.h: Update. * guile/scm-block.c: Update. * guile/scm-breakpoint.c: Update. * guile/scm-cmd.c: Update. * guile/scm-disasm.c: Update. * guile/scm-frame.c: Update. * guile/scm-lazy-string.c: Update. * guile/scm-math.c: Update. * guile/scm-param.c: Update. * guile/scm-ports.c: Update. * guile/scm-pretty-print.c: Update. * guile/scm-symbol.c: Update. * guile/scm-symtab.c: Update. * guile/scm-type.c: Update. * guile/scm-value.c: Update. * i386-linux-tdep.c: Update. * i386-tdep.c: Update. * inf-loop.c: Update. * infcall.c: Update. * infcmd.c: Update. * infrun.c: Update. * jit.c: Update. * language.c: Update. * linespec.c: Update. * linux-fork.c: Update. * linux-nat.c: Update. * linux-tdep.c: Update. * linux-thread-db.c: Update. * main.c: Update. * mi/mi-cmd-break.c: Update. * mi/mi-cmd-stack.c: Update. * mi/mi-interp.c: Update. * mi/mi-main.c: Update. * objc-lang.c: Update. * p-valprint.c: Update. * parse.c: Update. * ppc-linux-tdep.c: Update. * printcmd.c: Update. * python/py-arch.c: Update. * python/py-breakpoint.c: Update. * python/py-cmd.c: Update. * python/py-finishbreakpoint.c: Update. * python/py-frame.c: Update. * python/py-framefilter.c: Update. * python/py-gdb-readline.c: Update. * python/py-inferior.c: Update. * python/py-infthread.c: Update. * python/py-lazy-string.c: Update. * python/py-linetable.c: Update. * python/py-objfile.c: Update. * python/py-param.c: Update. * python/py-prettyprint.c: Update. * python/py-progspace.c: Update. * python/py-record-btrace.c: Update. * python/py-record.c: Update. * python/py-symbol.c: Update. * python/py-type.c: Update. * python/py-unwind.c: Update. * python/py-utils.c: Update. * python/py-value.c: Update. * python/python.c: Update. * record-btrace.c: Update. * record-full.c: Update. * remote-fileio.c: Update. * remote.c: Update. * riscv-tdep.c: Update. * rs6000-aix-tdep.c: Update. * rs6000-tdep.c: Update. * rust-exp.y: Update. * rust-lang.c: Update. * s390-tdep.c: Update. * selftest-arch.c: Update. * solib-dsbt.c: Update. * solib-frv.c: Update. * solib-spu.c: Update. * solib-svr4.c: Update. * solib.c: Update. * sparc64-linux-tdep.c: Update. * stack.c: Update. * symfile-mem.c: Update. * symmisc.c: Update. * target.c: Update. * thread.c: Update. * top.c: Update. * tracefile-tfile.c: Update. * tui/tui.c: Update. * typeprint.c: Update. * unittests/cli-utils-selftests.c: Update. * unittests/parse-connection-spec-selftests.c: Update. * valops.c: Update. * valprint.c: Update. * value.c: Update. * varobj.c: Update. * windows-nat.c: Update. * x86-linux-nat.c: Update. * xml-support.c: Update. gdb/gdbserver/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * gdbreplay.c: Update. * linux-low.c: Update. * server.c: Update.
2019-04-03 23:59:07 +02:00
catch (const gdb_exception_error &ex)
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
{
/* Handle failure to read a register without interrupting the entire
'info registers' flow. */
Make exceptions use std::string and be self-managing This changes the exception's "message" member to be a shared_ptr wrapping a std::string. This allows removing the stack of exception messages, because now exceptions will self-destruct when needed. This also adds a noexcept copy constructor and operator= to gdb_exception, plus a "what" method. gdb/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * xml-support.c (gdb_xml_parser::parse): Update. * x86-linux-nat.c (x86_linux_nat_target::enable_btrace): Update. * value.c (show_convenience): Update. * unittests/cli-utils-selftests.c (test_number_or_range_parser) (test_parse_flags_qcs): Update. * thread.c (thr_try_catch_cmd): Update. * target.c (target_translate_tls_address): Update. * stack.c (print_frame_arg, read_frame_local, read_frame_arg) (info_frame_command_core, frame_apply_command_count): Update. * rust-exp.y (rust_lex_exception_test): Update. * riscv-tdep.c (riscv_print_one_register_info): Update. * remote.c (remote_target::enable_btrace): Update. * record-btrace.c (record_btrace_enable_warn): Update. * python/py-utils.c (gdbpy_convert_exception): Update. * printcmd.c (do_one_display, print_variable_and_value): Update. * mi/mi-main.c (mi_print_exception): Update. * mi/mi-interp.c (mi_cmd_interpreter_exec): Use SCOPE_EXIT. * mi/mi-cmd-stack.c (list_arg_or_local): Update. * linux-nat.c (linux_nat_target::attach): Update. * linux-fork.c (class scoped_switch_fork_info): Update. * infrun.c (displaced_step_prepare): Update. * infcall.c (call_function_by_hand_dummy): Update. * guile/scm-exception.c (gdbscm_scm_from_gdb_exception): Update. * gnu-v3-abi.c (print_one_vtable): Update. * frame.c (get_prev_frame_always): Update. * f-valprint.c (info_common_command_for_block): Update. * exec.c (try_open_exec_file): Update. * exceptions.c (print_exception, exception_print) (exception_fprintf, exception_print_same): Update. * dwarf2-frame.c (dwarf2_build_frame_info): Update. * dwarf-index-cache.c (index_cache::store) (index_cache::lookup_gdb_index): Update. * darwin-nat.c (maybe_cache_shell): Update. * cp-valprint.c (cp_print_value_fields): Update. * compile/compile-cplus-symbols.c (gcc_cplus_convert_symbol) (gcc_cplus_symbol_address): Update. * compile/compile-c-symbols.c (gcc_convert_symbol) (gcc_symbol_address, generate_c_for_for_one_variable): Update. * common/selftest.c: Update. * common/common-exceptions.h (struct gdb_exception) <message>: Now a std::string. (exception_try_scope_entry, exception_try_scope_exit): Don't declare. (struct exception_try_scope): Remove. (TRY): Don't use exception_try_scope. (struct gdb_exception): Add constructor, operator=. <what>: New method. (struct gdb_exception_RETURN_MASK_ALL) (struct gdb_exception_RETURN_MASK_ERROR) (struct gdb_exception_RETURN_MASK_QUIT): Add constructor. (struct gdb_quit_bad_alloc): Update. * common/common-exceptions.c (exception_none): Change initializer. (struct catcher) <state, exception>: Initialize inline. <prev>: Remove member. (current_catcher): Remove. (catchers): New global. (exceptions_state_mc_init): Simplify. (catcher_pop): Remove. (exceptions_state_mc, exceptions_state_mc_catch): Update. (try_scope_depth, exception_try_scope_entry) (exception_try_scope_exit): Remove. (throw_exception_sjlj): Update. (exception_messages, exception_messages_size): Remove. (throw_it): Simplify. (gdb_exception_sliced_copy): Remove. (throw_exception_cxx): Update. * cli/cli-script.c (script_from_file): Update. * breakpoint.c (insert_bp_location, update_breakpoint_locations): Update. * ada-valprint.c (ada_val_print): Update. * ada-lang.c (ada_to_fixed_type_1, ada_exception_name_addr) (create_excep_cond_exprs): Update. gdb/gdbserver/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * server.c (handle_btrace_general_set, handle_qxfer_btrace) (handle_qxfer_btrace_conf, detach_or_kill_for_exit_cleanup) (captured_main, main): Update. * gdbreplay.c (main): Update.
2019-01-28 18:11:10 +01:00
fprintf_filtered (file, "%s\n", ex.what ());
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
return;
}
print_raw_format = (value_entirely_available (val)
&& !value_optimized_out (val));
if (TYPE_CODE (regtype) == TYPE_CODE_FLT
|| (TYPE_CODE (regtype) == TYPE_CODE_UNION
&& TYPE_NFIELDS (regtype) == 2
&& TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
&& TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
|| (TYPE_CODE (regtype) == TYPE_CODE_UNION
&& TYPE_NFIELDS (regtype) == 3
&& TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
&& TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
&& TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
{
struct value_print_options opts;
const gdb_byte *valaddr = value_contents_for_printing (val);
Adjust byte order variable display/change if DW_AT_endianity is present. - Rationale: It is possible for compilers to indicate the desired byte order interpretation of scalar variables using the DWARF attribute: DW_AT_endianity A type flagged with this variable would typically use one of: DW_END_big DW_END_little which instructs the debugger what the desired byte order interpretation of the variable should be. The GCC compiler (as of V6) has a mechanism for setting the desired byte ordering of the fields within a structure or union. For, example, on a little endian target, a structure declared as: struct big { int v; short a[4]; } __attribute__( ( scalar_storage_order( "big-endian" ) ) ); could be used to ensure all the structure members have a big-endian interpretation (the compiler would automatically insert byte swap instructions before and after respective store and load instructions). - To reproduce GCC V8 is required to correctly emit DW_AT_endianity DWARF attributes in all situations when the scalar_storage_order attribute is used. A fix for (dwarf endianity instrumentation) for GCC V6-V7 can be found in the URL field of the following PR: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82509 - Test-case: A new test case (testsuite/gdb.base/endianity.*) is included with this patch. Manual testing for mixed endianity code has also been done with GCC V8. See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=82509#c4 - Observed vs. expected: Without this change, using scalar_storage_order that doesn't match the target, such as struct otherendian { int v; } __attribute__( ( scalar_storage_order( "big-endian" ) ) ); would behave like the following on a little endian target: Breakpoint 1 at 0x401135: file endianity.c, line 41. (gdb) run Starting program: /home/pjoot/freeware/t/a.out Missing separate debuginfos, use: debuginfo-install glibc-2.17-292.el7.x86_64 Breakpoint 1, main () at endianity.c:41 41 struct otherendian o = {3}; (gdb) n 43 do_nothing (&o); /* START */ (gdb) p o $1 = {v = 50331648} (gdb) p /x $2 = {v = 0x3000000} whereas with this gdb enhancement we can access the variable with the user specified endianity: Breakpoint 1, main () at endianity.c:41 41 struct otherendian o = {3}; (gdb) p o $1 = {v = 0} (gdb) n 43 do_nothing (&o); /* START */ (gdb) p o $2 = {v = 3} (gdb) p o.v = 4 $3 = 4 (gdb) p o.v $4 = 4 (gdb) x/4xb &o.v 0x7fffffffd90c: 0x00 0x00 0x00 0x04 (observe that the 4 byte int variable has a big endian representation in the hex dump.) gdb/ChangeLog 2019-11-21 Peeter Joot <peeter.joot@lzlabs.com> Byte reverse display of variables with DW_END_big, DW_END_little (DW_AT_endianity) dwarf attributes if different than the native byte order. * ada-lang.c (ada_value_binop): Use type_byte_order instead of gdbarch_byte_order. * ada-valprint.c (printstr): (ada_val_print_string): * ada-lang.c (value_pointer): (ada_value_binop): Use type_byte_order instead of gdbarch_byte_order. * c-lang.c (c_get_string): Use type_byte_order instead of gdbarch_byte_order. * c-valprint.c (c_val_print_array): Use type_byte_order instead of gdbarch_byte_order. * cp-valprint.c (cp_print_class_member): Use type_byte_order instead of gdbarch_byte_order. * dwarf2loc.c (rw_pieced_value): Use type_byte_order instead of gdbarch_byte_order. * dwarf2read.c (read_base_type): Handle DW_END_big, DW_END_little * f-lang.c (f_get_encoding): Use type_byte_order instead of gdbarch_byte_order. * findvar.c (default_read_var_value): Use type_byte_order instead of gdbarch_byte_order. * gdbtypes.c (check_types_equal): Require matching TYPE_ENDIANITY_NOT_DEFAULT if set. (recursive_dump_type): Print TYPE_ENDIANITY_BIG, and TYPE_ENDIANITY_LITTLE if set. (type_byte_order): new function. * gdbtypes.h (TYPE_ENDIANITY_NOT_DEFAULT): New macro. (struct main_type) <flag_endianity_not_default>: New field. (type_byte_order): New function. * infcmd.c (default_print_one_register_info): Use type_byte_order instead of gdbarch_byte_order. * p-lang.c (pascal_printstr): Use type_byte_order instead of gdbarch_byte_order. * p-valprint.c (pascal_val_print): Use type_byte_order instead of gdbarch_byte_order. * printcmd.c (print_scalar_formatted): Use type_byte_order instead of gdbarch_byte_order. * solib-darwin.c (darwin_current_sos): Use type_byte_order instead of gdbarch_byte_order. * solib-svr4.c (solib_svr4_r_ldsomap): Use type_byte_order instead of gdbarch_byte_order. * stap-probe.c (stap_modify_semaphore): Use type_byte_order instead of gdbarch_byte_order. * target-float.c (target_float_same_format_p): Use type_byte_order instead of gdbarch_byte_order. * valarith.c (scalar_binop): (value_bit_index): Use type_byte_order instead of gdbarch_byte_order. * valops.c (value_cast): Use type_byte_order instead of gdbarch_byte_order. * valprint.c (generic_emit_char): (generic_printstr): (val_print_string): Use type_byte_order instead of gdbarch_byte_order. * value.c (unpack_long): (unpack_bits_as_long): (unpack_value_bitfield): (modify_field): (pack_long): (pack_unsigned_long): Use type_byte_order instead of gdbarch_byte_order. * findvar.c (unsigned_pointer_to_address): (signed_pointer_to_address): (unsigned_address_to_pointer): (address_to_signed_pointer): (default_read_var_value): (default_value_from_register): Use type_byte_order instead of gdbarch_byte_order. * gnu-v3-abi.c (gnuv3_make_method_ptr): Use type_byte_order instead of gdbarch_byte_order. * riscv-tdep.c (riscv_print_one_register_info): Use type_byte_order instead of gdbarch_byte_order. gdb/testsuite/ChangeLog 2019-11-21 Peeter Joot <peeter.joot@lzlabs.com> * gdb.base/endianity.c: New test. * gdb.base/endianity.exp: New file. Change-Id: I4bd98c1b4508c2d7c5a5dbb15d7b7b1cb4e667e2
2017-10-06 22:13:04 +02:00
enum bfd_endian byte_order = type_byte_order (regtype);
get_user_print_options (&opts);
opts.deref_ref = 1;
val_print (regtype,
value_embedded_offset (val), 0,
file, 0, val, &opts, current_language);
if (print_raw_format)
{
fprintf_filtered (file, "\t(raw ");
print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
true);
fprintf_filtered (file, ")");
}
}
else
{
struct value_print_options opts;
/* Print the register in hex. */
get_formatted_print_options (&opts, 'x');
opts.deref_ref = 1;
val_print (regtype,
value_embedded_offset (val), 0,
file, 0, val, &opts, current_language);
if (print_raw_format)
{
if (regnum == RISCV_CSR_MSTATUS_REGNUM)
{
LONGEST d;
int size = register_size (gdbarch, regnum);
unsigned xlen;
/* The SD field is always in the upper bit of MSTATUS, regardless
of the number of bits in MSTATUS. */
d = value_as_long (val);
xlen = size * 8;
fprintf_filtered (file,
"\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
"FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
"SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
(int) ((d >> (xlen - 1)) & 0x1),
(int) ((d >> 24) & 0x1f),
(int) ((d >> 19) & 0x1),
(int) ((d >> 18) & 0x1),
(int) ((d >> 17) & 0x1),
(int) ((d >> 15) & 0x3),
(int) ((d >> 13) & 0x3),
(int) ((d >> 11) & 0x3),
(int) ((d >> 9) & 0x3),
(int) ((d >> 8) & 0x1),
(int) ((d >> 7) & 0x1),
(int) ((d >> 6) & 0x1),
(int) ((d >> 5) & 0x1),
(int) ((d >> 4) & 0x1),
(int) ((d >> 3) & 0x1),
(int) ((d >> 2) & 0x1),
(int) ((d >> 1) & 0x1),
(int) ((d >> 0) & 0x1));
}
else if (regnum == RISCV_CSR_MISA_REGNUM)
{
int base;
unsigned xlen, i;
LONGEST d;
int size = register_size (gdbarch, regnum);
/* The MXL field is always in the upper two bits of MISA,
regardless of the number of bits in MISA. Mask out other
bits to ensure we have a positive value. */
d = value_as_long (val);
base = (d >> ((size * 8) - 2)) & 0x3;
xlen = 16;
for (; base > 0; base--)
xlen *= 2;
fprintf_filtered (file, "\tRV%d", xlen);
for (i = 0; i < 26; i++)
{
if (d & (1 << i))
fprintf_filtered (file, "%c", 'A' + i);
}
}
else if (regnum == RISCV_CSR_FCSR_REGNUM
|| regnum == RISCV_CSR_FFLAGS_REGNUM
|| regnum == RISCV_CSR_FRM_REGNUM)
{
LONGEST d;
d = value_as_long (val);
fprintf_filtered (file, "\t");
if (regnum != RISCV_CSR_FRM_REGNUM)
fprintf_filtered (file,
"RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
(int) ((d >> 5) & 0x7),
(int) ((d >> 4) & 0x1),
(int) ((d >> 3) & 0x1),
(int) ((d >> 2) & 0x1),
(int) ((d >> 1) & 0x1),
(int) ((d >> 0) & 0x1));
if (regnum != RISCV_CSR_FFLAGS_REGNUM)
{
static const char * const sfrm[] =
{
"RNE (round to nearest; ties to even)",
"RTZ (Round towards zero)",
"RDN (Round down towards -INF)",
"RUP (Round up towards +INF)",
"RMM (Round to nearest; ties to max magnitude)",
"INVALID[5]",
"INVALID[6]",
"dynamic rounding mode",
};
int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
? (d >> 5) : d) & 0x3;
fprintf_filtered (file, "%sFRM:%i [%s]",
(regnum == RISCV_CSR_FCSR_REGNUM
? " " : ""),
frm, sfrm[frm]);
}
}
else if (regnum == RISCV_PRIV_REGNUM)
{
LONGEST d;
uint8_t priv;
d = value_as_long (val);
priv = d & 0xff;
if (priv < 4)
{
static const char * const sprv[] =
{
"User/Application",
"Supervisor",
"Hypervisor",
"Machine"
};
fprintf_filtered (file, "\tprv:%d [%s]",
priv, sprv[priv]);
}
else
fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
}
else
{
/* If not a vector register, print it also according to its
natural format. */
if (TYPE_VECTOR (regtype) == 0)
{
get_user_print_options (&opts);
opts.deref_ref = 1;
fprintf_filtered (file, "\t");
val_print (regtype,
value_embedded_offset (val), 0,
file, 0, val, &opts, current_language);
}
}
}
}
fprintf_filtered (file, "\n");
}
/* Return true if REGNUM is a valid CSR register. The CSR register space
is sparsely populated, so not every number is a named CSR. */
static bool
riscv_is_regnum_a_named_csr (int regnum)
{
gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
&& regnum <= RISCV_LAST_CSR_REGNUM);
switch (regnum)
{
#define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
return true;
default:
return false;
}
}
/* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
of REGGROUP? */
static int
riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
struct reggroup *reggroup)
{
/* Used by 'info registers' and 'info registers <groupname>'. */
if (gdbarch_register_name (gdbarch, regnum) == NULL
|| gdbarch_register_name (gdbarch, regnum)[0] == '\0')
return 0;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
if (regnum > RISCV_LAST_REGNUM)
{
int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
if (ret != -1)
return ret;
return default_register_reggroup_p (gdbarch, regnum, reggroup);
}
if (reggroup == all_reggroup)
{
if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
return 1;
if (riscv_is_regnum_a_named_csr (regnum))
return 1;
return 0;
}
else if (reggroup == float_reggroup)
return (riscv_is_fp_regno_p (regnum)
|| regnum == RISCV_CSR_FCSR_REGNUM
|| regnum == RISCV_CSR_FFLAGS_REGNUM
|| regnum == RISCV_CSR_FRM_REGNUM);
else if (reggroup == general_reggroup)
return regnum < RISCV_FIRST_FP_REGNUM;
else if (reggroup == restore_reggroup || reggroup == save_reggroup)
{
if (riscv_has_fp_regs (gdbarch))
return (regnum <= RISCV_LAST_FP_REGNUM
|| regnum == RISCV_CSR_FCSR_REGNUM
|| regnum == RISCV_CSR_FFLAGS_REGNUM
|| regnum == RISCV_CSR_FRM_REGNUM);
else
return regnum < RISCV_FIRST_FP_REGNUM;
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
else if (reggroup == system_reggroup || reggroup == csr_reggroup)
{
if (regnum == RISCV_PRIV_REGNUM)
return 1;
if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
return 0;
if (riscv_is_regnum_a_named_csr (regnum))
return 1;
return 0;
}
else if (reggroup == vector_reggroup)
return 0;
else
return 0;
}
/* Implement the print_registers_info gdbarch method. This is used by
'info registers' and 'info all-registers'. */
static void
riscv_print_registers_info (struct gdbarch *gdbarch,
struct ui_file *file,
struct frame_info *frame,
int regnum, int print_all)
{
if (regnum != -1)
{
/* Print one specified register. */
if (gdbarch_register_name (gdbarch, regnum) == NULL
|| *(gdbarch_register_name (gdbarch, regnum)) == '\0')
error (_("Not a valid register for the current processor type"));
riscv_print_one_register_info (gdbarch, file, frame, regnum);
}
else
{
struct reggroup *reggroup;
if (print_all)
reggroup = all_reggroup;
else
reggroup = general_reggroup;
for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
{
/* Zero never changes, so might as well hide by default. */
if (regnum == RISCV_ZERO_REGNUM && !print_all)
continue;
/* Registers with no name are not valid on this ISA. */
if (gdbarch_register_name (gdbarch, regnum) == NULL
|| *(gdbarch_register_name (gdbarch, regnum)) == '\0')
continue;
/* Is the register in the group we're interested in? */
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup))
continue;
riscv_print_one_register_info (gdbarch, file, frame, regnum);
}
}
}
/* Class that handles one decoded RiscV instruction. */
class riscv_insn
{
public:
/* Enum of all the opcodes that GDB cares about during the prologue scan. */
enum opcode
{
/* Unknown value is used at initialisation time. */
UNKNOWN = 0,
/* These instructions are all the ones we are interested in during the
prologue scan. */
ADD,
ADDI,
ADDIW,
ADDW,
AUIPC,
LUI,
SD,
SW,
/* These are needed for software breakpoint support. */
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JAL,
JALR,
BEQ,
BNE,
BLT,
BGE,
BLTU,
BGEU,
/* These are needed for stepping over atomic sequences. */
LR,
SC,
/* Other instructions are not interesting during the prologue scan, and
are ignored. */
OTHER
};
riscv_insn ()
: m_length (0),
m_opcode (OTHER),
m_rd (0),
m_rs1 (0),
m_rs2 (0)
{
/* Nothing. */
}
void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
/* Get the length of the instruction in bytes. */
int length () const
{ return m_length; }
/* Get the opcode for this instruction. */
enum opcode opcode () const
{ return m_opcode; }
/* Get destination register field for this instruction. This is only
valid if the OPCODE implies there is such a field for this
instruction. */
int rd () const
{ return m_rd; }
/* Get the RS1 register field for this instruction. This is only valid
if the OPCODE implies there is such a field for this instruction. */
int rs1 () const
{ return m_rs1; }
/* Get the RS2 register field for this instruction. This is only valid
if the OPCODE implies there is such a field for this instruction. */
int rs2 () const
{ return m_rs2; }
/* Get the immediate for this instruction in signed form. This is only
valid if the OPCODE implies there is such a field for this
instruction. */
int imm_signed () const
{ return m_imm.s; }
private:
/* Extract 5 bit register field at OFFSET from instruction OPCODE. */
int decode_register_index (unsigned long opcode, int offset)
{
return (opcode >> offset) & 0x1F;
}
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/* Extract 5 bit register field at OFFSET from instruction OPCODE. */
int decode_register_index_short (unsigned long opcode, int offset)
{
return ((opcode >> offset) & 0x7) + 8;
}
/* Helper for DECODE, decode 32-bit R-type instruction. */
void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rd = decode_register_index (ival, OP_SH_RD);
m_rs1 = decode_register_index (ival, OP_SH_RS1);
m_rs2 = decode_register_index (ival, OP_SH_RS2);
}
/* Helper for DECODE, decode 16-bit compressed R-type instruction. */
void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
m_rs2 = decode_register_index (ival, OP_SH_CRS2);
}
/* Helper for DECODE, decode 32-bit I-type instruction. */
void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rd = decode_register_index (ival, OP_SH_RD);
m_rs1 = decode_register_index (ival, OP_SH_RS1);
m_imm.s = EXTRACT_ITYPE_IMM (ival);
}
/* Helper for DECODE, decode 16-bit compressed I-type instruction. */
void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
m_imm.s = EXTRACT_RVC_IMM (ival);
}
/* Helper for DECODE, decode 32-bit S-type instruction. */
void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rs1 = decode_register_index (ival, OP_SH_RS1);
m_rs2 = decode_register_index (ival, OP_SH_RS2);
m_imm.s = EXTRACT_STYPE_IMM (ival);
}
/* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
encoding is different for each CS format instruction, so extracting
the immediate is left up to the caller, who should pass the extracted
immediate value through in IMM. */
void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
{
m_opcode = opcode;
m_imm.s = imm;
m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
}
/* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
encoding is different for each CSS format instruction, so extracting
the immediate is left up to the caller, who should pass the extracted
immediate value through in IMM. */
void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
{
m_opcode = opcode;
m_imm.s = imm;
m_rs1 = RISCV_SP_REGNUM;
/* Not a compressed register number in this case. */
m_rs2 = decode_register_index (ival, OP_SH_CRS2);
}
/* Helper for DECODE, decode 32-bit U-type instruction. */
void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rd = decode_register_index (ival, OP_SH_RD);
m_imm.s = EXTRACT_UTYPE_IMM (ival);
}
2018-08-08 19:53:12 +02:00
/* Helper for DECODE, decode 32-bit J-type instruction. */
void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rd = decode_register_index (ival, OP_SH_RD);
m_imm.s = EXTRACT_UJTYPE_IMM (ival);
}
/* Helper for DECODE, decode 32-bit J-type instruction. */
void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_imm.s = EXTRACT_RVC_J_IMM (ival);
}
void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rs1 = decode_register_index (ival, OP_SH_RS1);
m_rs2 = decode_register_index (ival, OP_SH_RS2);
m_imm.s = EXTRACT_SBTYPE_IMM (ival);
}
void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
{
m_opcode = opcode;
m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
m_imm.s = EXTRACT_RVC_B_IMM (ival);
}
/* Fetch instruction from target memory at ADDR, return the content of
the instruction, and update LEN with the instruction length. */
static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
CORE_ADDR addr, int *len);
/* The length of the instruction in bytes. Should be 2 or 4. */
int m_length;
/* The instruction opcode. */
enum opcode m_opcode;
/* The three possible registers an instruction might reference. Not
every instruction fills in all of these registers. Which fields are
valid depends on the opcode. The naming of these fields matches the
naming in the riscv isa manual. */
int m_rd;
int m_rs1;
int m_rs2;
/* Possible instruction immediate. This is only valid if the instruction
format contains an immediate, not all instruction, whether this is
valid depends on the opcode. Despite only having one format for now
the immediate is packed into a union, later instructions might require
an unsigned formatted immediate, having the union in place now will
reduce the need for code churn later. */
union riscv_insn_immediate
{
riscv_insn_immediate ()
: s (0)
{
/* Nothing. */
}
int s;
} m_imm;
};
/* Fetch instruction from target memory at ADDR, return the content of the
instruction, and update LEN with the instruction length. */
ULONGEST
riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
CORE_ADDR addr, int *len)
{
enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
gdb_byte buf[8];
int instlen, status;
/* All insns are at least 16 bits. */
status = target_read_memory (addr, buf, 2);
if (status)
memory_error (TARGET_XFER_E_IO, addr);
/* If we need more, grab it now. */
instlen = riscv_insn_length (buf[0]);
gdb_assert (instlen <= sizeof (buf));
*len = instlen;
if (instlen > 2)
{
status = target_read_memory (addr + 2, buf + 2, instlen - 2);
if (status)
memory_error (TARGET_XFER_E_IO, addr + 2);
}
return extract_unsigned_integer (buf, instlen, byte_order);
}
gdb/riscv: Handle errors while setting the frame id When we connect to a remote target one of the first things GDB does is establish a frame id. If an error is thrown while building this frame id then GDB will disconnect from the target. This can mean that, if the user is attempting to connect to a target that doesn't yet have a program loaded, or the program the user is going to load onto the target doesn't match what is already loaded, or the target is just in some undefined state, then the very first request for a frame id can fail (for example, by trying to load from an invalid memory address), and GDB will disconnect. It is then impossible for the user to connect to the target and load a new program at all. An example of such a session might look like this: Reading symbols from ./gdb/testsuite/outputs/gdb.arch/riscv-reg-aliases/riscv-reg-aliases... (gdb) target remote :37191 Remote debugging using :37191 0x0000000000000100 in ?? () Cannot access memory at address 0x0 (gdb) load You can't do that when your target is `exec' (gdb) info frame /path/to/gdb/gdb/thread.c:93: internal-error: thread_info* inferior_thread(): Assertion `tp' failed. A problem internal to GDB has been detected, further debugging may prove unreliable. Quit this debugging session? (y or n) The solution is to handle errors in riscv_frame_this_id, and leave the this_id variable with its default value, which is the predefined 'outermost' frame. With this fix in place, connecting to the same target now looks like this: (gdb) target remote :37191 Remote debugging using :37191 0x0000000000000100 in ?? () (gdb) info frame Stack level 0, frame at 0x0: pc = 0x100; saved pc = <not saved> Outermost frame: outermost Arglist at unknown address. Locals at unknown address, Previous frame's sp in sp gdb/ChangeLog: * riscv-tdep.c (riscv_insn::decode): Update header comment. (riscv_frame_this_id): Catch errors thrown while building the frame cache, leave the frame id as the default, which is the outer frame id.
2018-10-29 16:14:03 +01:00
/* Fetch from target memory an instruction at PC and decode it. This can
throw an error if the memory access fails, callers are responsible for
handling this error if that is appropriate. */
void
riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
{
ULONGEST ival;
/* Fetch the instruction, and the instructions length. */
ival = fetch_instruction (gdbarch, pc, &m_length);
if (m_length == 4)
{
if (is_add_insn (ival))
decode_r_type_insn (ADD, ival);
else if (is_addw_insn (ival))
decode_r_type_insn (ADDW, ival);
else if (is_addi_insn (ival))
decode_i_type_insn (ADDI, ival);
else if (is_addiw_insn (ival))
decode_i_type_insn (ADDIW, ival);
else if (is_auipc_insn (ival))
decode_u_type_insn (AUIPC, ival);
else if (is_lui_insn (ival))
decode_u_type_insn (LUI, ival);
else if (is_sd_insn (ival))
decode_s_type_insn (SD, ival);
else if (is_sw_insn (ival))
decode_s_type_insn (SW, ival);
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else if (is_jal_insn (ival))
decode_j_type_insn (JAL, ival);
else if (is_jalr_insn (ival))
decode_i_type_insn (JALR, ival);
else if (is_beq_insn (ival))
decode_b_type_insn (BEQ, ival);
else if (is_bne_insn (ival))
decode_b_type_insn (BNE, ival);
else if (is_blt_insn (ival))
decode_b_type_insn (BLT, ival);
else if (is_bge_insn (ival))
decode_b_type_insn (BGE, ival);
else if (is_bltu_insn (ival))
decode_b_type_insn (BLTU, ival);
else if (is_bgeu_insn (ival))
decode_b_type_insn (BGEU, ival);
else if (is_lr_w_insn (ival))
decode_r_type_insn (LR, ival);
else if (is_lr_d_insn (ival))
decode_r_type_insn (LR, ival);
else if (is_sc_w_insn (ival))
decode_r_type_insn (SC, ival);
else if (is_sc_d_insn (ival))
decode_r_type_insn (SC, ival);
else
/* None of the other fields are valid in this case. */
m_opcode = OTHER;
}
else if (m_length == 2)
{
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int xlen = riscv_isa_xlen (gdbarch);
/* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
C_JALR. So must try to match C_JALR first as it has more bits in
mask. */
if (is_c_jalr_insn (ival))
decode_cr_type_insn (JALR, ival);
else if (is_c_add_insn (ival))
decode_cr_type_insn (ADD, ival);
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/* C_ADDW is RV64 and RV128 only. */
else if (xlen != 4 && is_c_addw_insn (ival))
decode_cr_type_insn (ADDW, ival);
else if (is_c_addi_insn (ival))
decode_ci_type_insn (ADDI, ival);
2018-08-08 19:53:12 +02:00
/* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
only and C_JAL is RV32 only. */
else if (xlen != 4 && is_c_addiw_insn (ival))
decode_ci_type_insn (ADDIW, ival);
2018-08-08 19:53:12 +02:00
else if (xlen == 4 && is_c_jal_insn (ival))
decode_cj_type_insn (JAL, ival);
/* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
in mask. */
else if (is_c_addi16sp_insn (ival))
{
m_opcode = ADDI;
m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
}
else if (is_c_addi4spn_insn (ival))
{
m_opcode = ADDI;
m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
m_rs1 = RISCV_SP_REGNUM;
m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
}
2018-08-08 19:53:12 +02:00
else if (is_c_lui_insn (ival))
{
m_opcode = LUI;
m_rd = decode_register_index (ival, OP_SH_CRS1S);
m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
}
2018-08-08 19:53:12 +02:00
/* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
and C_FSW is RV32 only. */
else if (xlen != 4 && is_c_sd_insn (ival))
decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
2018-08-08 19:53:12 +02:00
else if (is_c_sw_insn (ival))
decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
else if (is_c_swsp_insn (ival))
decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
else if (xlen != 4 && is_c_sdsp_insn (ival))
decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
2018-08-08 19:53:12 +02:00
/* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
So must try to match C_JR first as it ahs more bits in mask. */
else if (is_c_jr_insn (ival))
decode_cr_type_insn (JALR, ival);
else if (is_c_j_insn (ival))
decode_cj_type_insn (JAL, ival);
else if (is_c_beqz_insn (ival))
decode_cb_type_insn (BEQ, ival);
else if (is_c_bnez_insn (ival))
decode_cb_type_insn (BNE, ival);
else
/* None of the other fields of INSN are valid in this case. */
m_opcode = OTHER;
}
else
{
/* This must be a 6 or 8 byte instruction, we don't currently decode
any of these, so just ignore it. */
gdb_assert (m_length == 6 || m_length == 8);
m_opcode = OTHER;
}
}
/* The prologue scanner. This is currently only used for skipping the
prologue of a function when the DWARF information is not sufficient.
However, it is written with filling of the frame cache in mind, which
is why different groups of stack setup instructions are split apart
during the core of the inner loop. In the future, the intention is to
extend this function to fully support building up a frame cache that
can unwind register values when there is no DWARF information. */
static CORE_ADDR
riscv_scan_prologue (struct gdbarch *gdbarch,
CORE_ADDR start_pc, CORE_ADDR end_pc,
struct riscv_unwind_cache *cache)
{
CORE_ADDR cur_pc, next_pc, after_prologue_pc;
CORE_ADDR end_prologue_addr = 0;
/* Find an upper limit on the function prologue using the debug
information. If the debug information could not be used to provide
that bound, then use an arbitrary large number as the upper bound. */
after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
if (after_prologue_pc == 0)
after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
if (after_prologue_pc < end_pc)
end_pc = after_prologue_pc;
pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
regs[regno] = pv_register (regno, 0);
pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
if (riscv_debug_unwinder)
fprintf_unfiltered
(gdb_stdlog,
"Prologue scan for function starting at %s (limit %s)\n",
core_addr_to_string (start_pc),
core_addr_to_string (end_pc));
for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
{
struct riscv_insn insn;
/* Decode the current instruction, and decide where the next
instruction lives based on the size of this instruction. */
insn.decode (gdbarch, cur_pc);
gdb_assert (insn.length () > 0);
next_pc = cur_pc + insn.length ();
/* Look for common stack adjustment insns. */
if ((insn.opcode () == riscv_insn::ADDI
|| insn.opcode () == riscv_insn::ADDIW)
&& insn.rd () == RISCV_SP_REGNUM
&& insn.rs1 () == RISCV_SP_REGNUM)
{
/* Handle: addi sp, sp, -i
or: addiw sp, sp, -i */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()]
= pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
}
else if ((insn.opcode () == riscv_insn::SW
|| insn.opcode () == riscv_insn::SD)
&& (insn.rs1 () == RISCV_SP_REGNUM
|| insn.rs1 () == RISCV_FP_REGNUM))
{
/* Handle: sw reg, offset(sp)
or: sd reg, offset(sp)
or: sw reg, offset(s0)
or: sd reg, offset(s0) */
/* Instruction storing a register onto the stack. */
gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
(insn.opcode () == riscv_insn::SW ? 4 : 8),
regs[insn.rs2 ()]);
}
else if (insn.opcode () == riscv_insn::ADDI
&& insn.rd () == RISCV_FP_REGNUM
&& insn.rs1 () == RISCV_SP_REGNUM)
{
/* Handle: addi s0, sp, size */
/* Instructions setting up the frame pointer. */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()]
= pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
}
else if ((insn.opcode () == riscv_insn::ADD
|| insn.opcode () == riscv_insn::ADDW)
&& insn.rd () == RISCV_FP_REGNUM
&& insn.rs1 () == RISCV_SP_REGNUM
&& insn.rs2 () == RISCV_ZERO_REGNUM)
{
/* Handle: add s0, sp, 0
or: addw s0, sp, 0 */
/* Instructions setting up the frame pointer. */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
}
else if ((insn.opcode () == riscv_insn::ADDI
&& insn.rd () == RISCV_ZERO_REGNUM
&& insn.rs1 () == RISCV_ZERO_REGNUM
&& insn.imm_signed () == 0))
{
/* Handle: add x0, x0, 0 (NOP) */
}
else if (insn.opcode () == riscv_insn::AUIPC)
{
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
}
else if (insn.opcode () == riscv_insn::LUI)
{
/* Handle: lui REG, n
Where REG is not gp register. */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()] = pv_constant (insn.imm_signed ());
}
else if (insn.opcode () == riscv_insn::ADDI)
{
/* Handle: addi REG1, REG2, IMM */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()]
= pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
}
else if (insn.opcode () == riscv_insn::ADD)
{
/* Handle: addi REG1, REG2, IMM */
gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
}
else
{
end_prologue_addr = cur_pc;
break;
}
}
if (end_prologue_addr == 0)
end_prologue_addr = cur_pc;
if (riscv_debug_unwinder)
fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
core_addr_to_string (end_prologue_addr));
if (cache != NULL)
{
/* Figure out if it is a frame pointer or just a stack pointer. Also
the offset held in the pv_t is from the original register value to
the current value, which for a grows down stack means a negative
value. The FRAME_BASE_OFFSET is the negation of this, how to get
from the current value to the original value. */
if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
{
cache->frame_base_reg = RISCV_FP_REGNUM;
cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
}
else
{
cache->frame_base_reg = RISCV_SP_REGNUM;
cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
}
/* Assign offset from old SP to all saved registers. As we don't
have the previous value for the frame base register at this
point, we store the offset as the address in the trad_frame, and
then convert this to an actual address later. */
for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
{
CORE_ADDR offset;
if (stack.find_reg (gdbarch, i, &offset))
{
if (riscv_debug_unwinder)
{
/* Display OFFSET as a signed value, the offsets are from
the frame base address to the registers location on
the stack, with a descending stack this means the
offsets are always negative. */
fprintf_unfiltered (gdb_stdlog,
"Register $%s at stack offset %s\n",
gdbarch_register_name (gdbarch, i),
plongest ((LONGEST) offset));
}
trad_frame_set_addr (cache->regs, i, offset);
}
}
}
return end_prologue_addr;
}
/* Implement the riscv_skip_prologue gdbarch method. */
static CORE_ADDR
riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR func_addr;
/* See if we can determine the end of the prologue via the symbol
table. If so, then return either PC, or the PC after the
prologue, whichever is greater. */
if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
{
CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (gdbarch, func_addr);
if (post_prologue_pc != 0)
return std::max (pc, post_prologue_pc);
}
/* Can't determine prologue from the symbol table, need to examine
instructions. Pass -1 for the end address to indicate the prologue
scanner can scan as far as it needs to find the end of the prologue. */
return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
}
/* Implement the gdbarch push dummy code callback. */
static CORE_ADDR
riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
CORE_ADDR funaddr, struct value **args, int nargs,
struct type *value_type, CORE_ADDR *real_pc,
CORE_ADDR *bp_addr, struct regcache *regcache)
{
/* A nop instruction is 'add x0, x0, 0'. */
static const gdb_byte nop_insn[] = { 0x13, 0x00, 0x00, 0x00 };
/* Allocate space for a breakpoint, and keep the stack correctly
aligned. The space allocated here must be at least big enough to
accommodate the NOP_INSN defined above. */
sp -= 16;
*bp_addr = sp;
*real_pc = funaddr;
/* When we insert a breakpoint we select whether to use a compressed
breakpoint or not based on the existing contents of the memory.
If the breakpoint is being placed onto the stack as part of setting up
for an inferior call from GDB, then the existing stack contents may
randomly appear to be a compressed instruction, causing GDB to insert
a compressed breakpoint. If this happens on a target that does not
support compressed instructions then this could cause problems.
To prevent this issue we write an uncompressed nop onto the stack at
the location where the breakpoint will be inserted. In this way we
ensure that we always use an uncompressed breakpoint, which should
work on all targets.
We call TARGET_WRITE_MEMORY here so that if the write fails we don't
throw an exception. Instead we ignore the error and move on. The
assumption is that either GDB will error later when actually trying to
insert a software breakpoint, or GDB will use hardware breakpoints and
there will be no need to write to memory later. */
int status = target_write_memory (*bp_addr, nop_insn, sizeof (nop_insn));
if (riscv_debug_breakpoints || riscv_debug_infcall)
fprintf_unfiltered (gdb_stdlog,
"Writing %s-byte nop instruction to %s: %s\n",
plongest (sizeof (nop_insn)),
paddress (gdbarch, *bp_addr),
(status == 0 ? "success" : "failed"));
return sp;
}
/* Implement the gdbarch type alignment method, overrides the generic
alignment algorithm for anything that is RISC-V specific. */
static ULONGEST
riscv_type_align (gdbarch *gdbarch, type *type)
{
type = check_typedef (type);
if (TYPE_CODE (type) == TYPE_CODE_ARRAY && TYPE_VECTOR (type))
return std::min (TYPE_LENGTH (type), (ULONGEST) BIGGEST_ALIGNMENT);
/* Anything else will be aligned by the generic code. */
return 0;
}
/* Holds information about a single argument either being passed to an
inferior function, or returned from an inferior function. This includes
information about the size, type, etc of the argument, and also
information about how the argument will be passed (or returned). */
struct riscv_arg_info
{
/* Contents of the argument. */
const gdb_byte *contents;
/* Length of argument. */
int length;
/* Alignment required for an argument of this type. */
int align;
/* The type for this argument. */
struct type *type;
/* Each argument can have either 1 or 2 locations assigned to it. Each
location describes where part of the argument will be placed. The
second location is valid based on the LOC_TYPE and C_LENGTH fields
of the first location (which is always valid). */
struct location
{
/* What type of location this is. */
enum location_type
{
/* Argument passed in a register. */
in_reg,
/* Argument passed as an on stack argument. */
on_stack,
/* Argument passed by reference. The second location is always
valid for a BY_REF argument, and describes where the address
of the BY_REF argument should be placed. */
by_ref
} loc_type;
/* Information that depends on the location type. */
union
{
/* Which register number to use. */
int regno;
/* The offset into the stack region. */
int offset;
} loc_data;
/* The length of contents covered by this location. If this is less
than the total length of the argument, then the second location
will be valid, and will describe where the rest of the argument
will go. */
int c_length;
/* The offset within CONTENTS for this part of the argument. Will
always be 0 for the first part. For the second part of the
argument, this might be the C_LENGTH value of the first part,
however, if we are passing a structure in two registers, and there's
is padding between the first and second field, then this offset
might be greater than the length of the first argument part. When
the second argument location is not holding part of the argument
value, but is instead holding the address of a reference argument,
then this offset will be set to 0. */
int c_offset;
} argloc[2];
/* TRUE if this is an unnamed argument. */
bool is_unnamed;
};
/* Information about a set of registers being used for passing arguments as
part of a function call. The register set must be numerically
sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
struct riscv_arg_reg
{
riscv_arg_reg (int first, int last)
: next_regnum (first),
last_regnum (last)
{
/* Nothing. */
}
/* The GDB register number to use in this set. */
int next_regnum;
/* The last GDB register number to use in this set. */
int last_regnum;
};
/* Arguments can be passed as on stack arguments, or by reference. The
on stack arguments must be in a continuous region starting from $sp,
while the by reference arguments can be anywhere, but we'll put them
on the stack after (at higher address) the on stack arguments.
This might not be the right approach to take. The ABI is clear that
an argument passed by reference can be modified by the callee, which
us placing the argument (temporarily) onto the stack will not achieve
(changes will be lost). There's also the possibility that very large
arguments could overflow the stack.
This struct is used to track offset into these two areas for where
arguments are to be placed. */
struct riscv_memory_offsets
{
riscv_memory_offsets ()
: arg_offset (0),
ref_offset (0)
{
/* Nothing. */
}
/* Offset into on stack argument area. */
int arg_offset;
/* Offset into the pass by reference area. */
int ref_offset;
};
/* Holds information about where arguments to a call will be placed. This
is updated as arguments are added onto the call, and can be used to
figure out where the next argument should be placed. */
struct riscv_call_info
{
riscv_call_info (struct gdbarch *gdbarch)
: int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
{
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
xlen = riscv_abi_xlen (gdbarch);
flen = riscv_abi_flen (gdbarch);
/* Disable use of floating point registers if needed. */
if (!riscv_has_fp_abi (gdbarch))
float_regs.next_regnum = float_regs.last_regnum + 1;
}
/* Track the memory areas used for holding in-memory arguments to a
call. */
struct riscv_memory_offsets memory;
/* Holds information about the next integer register to use for passing
an argument. */
struct riscv_arg_reg int_regs;
/* Holds information about the next floating point register to use for
passing an argument. */
struct riscv_arg_reg float_regs;
/* The XLEN and FLEN are copied in to this structure for convenience, and
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
int xlen;
int flen;
};
/* Return the number of registers available for use as parameters in the
register set REG. Returned value can be 0 or more. */
static int
riscv_arg_regs_available (struct riscv_arg_reg *reg)
{
if (reg->next_regnum > reg->last_regnum)
return 0;
return (reg->last_regnum - reg->next_regnum + 1);
}
/* If there is at least one register available in the register set REG then
the next register from REG is assigned to LOC and the length field of
LOC is updated to LENGTH. The register set REG is updated to indicate
that the assigned register is no longer available and the function
returns true.
If there are no registers available in REG then the function returns
false, and LOC and REG are unchanged. */
static bool
riscv_assign_reg_location (struct riscv_arg_info::location *loc,
struct riscv_arg_reg *reg,
int length, int offset)
{
if (reg->next_regnum <= reg->last_regnum)
{
loc->loc_type = riscv_arg_info::location::in_reg;
loc->loc_data.regno = reg->next_regnum;
reg->next_regnum++;
loc->c_length = length;
loc->c_offset = offset;
return true;
}
return false;
}
/* Assign LOC a location as the next stack parameter, and update MEMORY to
record that an area of stack has been used to hold the parameter
described by LOC.
The length field of LOC is updated to LENGTH, the length of the
parameter being stored, and ALIGN is the alignment required by the
parameter, which will affect how memory is allocated out of MEMORY. */
static void
riscv_assign_stack_location (struct riscv_arg_info::location *loc,
struct riscv_memory_offsets *memory,
int length, int align)
{
loc->loc_type = riscv_arg_info::location::on_stack;
memory->arg_offset
= align_up (memory->arg_offset, align);
loc->loc_data.offset = memory->arg_offset;
memory->arg_offset += length;
loc->c_length = length;
/* Offset is always 0, either we're the first location part, in which
case we're reading content from the start of the argument, or we're
passing the address of a reference argument, so 0. */
loc->c_offset = 0;
}
/* Update AINFO, which describes an argument that should be passed or
returned using the integer ABI. The argloc fields within AINFO are
updated to describe the location in which the argument will be passed to
a function, or returned from a function.
The CINFO structure contains the ongoing call information, the holds
information such as which argument registers are remaining to be
assigned to parameter, and how much memory has been used by parameters
so far.
By examining the state of CINFO a suitable location can be selected,
and assigned to AINFO. */
static void
riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
struct riscv_call_info *cinfo)
{
if (ainfo->length > (2 * cinfo->xlen))
{
/* Argument is going to be passed by reference. */
ainfo->argloc[0].loc_type
= riscv_arg_info::location::by_ref;
cinfo->memory.ref_offset
= align_up (cinfo->memory.ref_offset, ainfo->align);
ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
cinfo->memory.ref_offset += ainfo->length;
ainfo->argloc[0].c_length = ainfo->length;
/* The second location for this argument is given over to holding the
address of the by-reference data. Pass 0 for the offset as this
is not part of the actual argument value. */
if (!riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->int_regs,
cinfo->xlen, 0))
riscv_assign_stack_location (&ainfo->argloc[1],
&cinfo->memory, cinfo->xlen,
cinfo->xlen);
}
else
{
int len = std::min (ainfo->length, cinfo->xlen);
int align = std::max (ainfo->align, cinfo->xlen);
/* Unnamed arguments in registers that require 2*XLEN alignment are
passed in an aligned register pair. */
if (ainfo->is_unnamed && (align == cinfo->xlen * 2)
&& cinfo->int_regs.next_regnum & 1)
cinfo->int_regs.next_regnum++;
if (!riscv_assign_reg_location (&ainfo->argloc[0],
&cinfo->int_regs, len, 0))
riscv_assign_stack_location (&ainfo->argloc[0],
&cinfo->memory, len, align);
if (len < ainfo->length)
{
len = ainfo->length - len;
if (!riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->int_regs, len,
cinfo->xlen))
riscv_assign_stack_location (&ainfo->argloc[1],
&cinfo->memory, len, cinfo->xlen);
}
}
}
/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
is being passed with the floating point ABI. */
static void
riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
struct riscv_call_info *cinfo)
{
if (ainfo->length > cinfo->flen || ainfo->is_unnamed)
return riscv_call_arg_scalar_int (ainfo, cinfo);
else
{
if (!riscv_assign_reg_location (&ainfo->argloc[0],
&cinfo->float_regs,
ainfo->length, 0))
return riscv_call_arg_scalar_int (ainfo, cinfo);
}
}
/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
is a complex floating point argument, and is therefore handled
differently to other argument types. */
static void
riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
struct riscv_call_info *cinfo)
{
if (ainfo->length <= (2 * cinfo->flen)
&& riscv_arg_regs_available (&cinfo->float_regs) >= 2
&& !ainfo->is_unnamed)
{
bool result;
int len = ainfo->length / 2;
result = riscv_assign_reg_location (&ainfo->argloc[0],
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
&cinfo->float_regs, len, 0);
gdb_assert (result);
result = riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->float_regs, len, len);
gdb_assert (result);
}
else
return riscv_call_arg_scalar_int (ainfo, cinfo);
}
/* A structure used for holding information about a structure type within
the inferior program. The RiscV ABI has special rules for handling some
structures with a single field or with two fields. The counting of
fields here is done after flattening out all nested structures. */
class riscv_struct_info
{
public:
riscv_struct_info ()
: m_number_of_fields (0),
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
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m_types { nullptr, nullptr },
m_offsets { 0, 0 }
{
/* Nothing. */
}
/* Analyse TYPE descending into nested structures, count the number of
scalar fields and record the types of the first two fields found. */
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
void analyse (struct type *type)
{
analyse_inner (type, 0);
}
/* The number of scalar fields found in the analysed type. This is
currently only accurate if the value returned is 0, 1, or 2 as the
analysis stops counting when the number of fields is 3. This is
because the RiscV ABI only has special cases for 1 or 2 fields,
anything else we just don't care about. */
int number_of_fields () const
{ return m_number_of_fields; }
/* Return the type for scalar field INDEX within the analysed type. Will
return nullptr if there is no field at that index. Only INDEX values
0 and 1 can be requested as the RiscV ABI only has special cases for
structures with 1 or 2 fields. */
struct type *field_type (int index) const
{
gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
return m_types[index];
}
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
/* Return the offset of scalar field INDEX within the analysed type. Will
return 0 if there is no field at that index. Only INDEX values 0 and
1 can be requested as the RiscV ABI only has special cases for
structures with 1 or 2 fields. */
int field_offset (int index) const
{
gdb_assert (index < (sizeof (m_offsets) / sizeof (m_offsets[0])));
return m_offsets[index];
}
private:
/* The number of scalar fields found within the structure after recursing
into nested structures. */
int m_number_of_fields;
/* The types of the first two scalar fields found within the structure
after recursing into nested structures. */
struct type *m_types[2];
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
/* The offsets of the first two scalar fields found within the structure
after recursing into nested structures. */
int m_offsets[2];
/* Recursive core for ANALYSE, the OFFSET parameter tracks the byte
offset from the start of the top level structure being analysed. */
void analyse_inner (struct type *type, int offset);
};
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
/* See description in class declaration. */
void
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
riscv_struct_info::analyse_inner (struct type *type, int offset)
{
unsigned int count = TYPE_NFIELDS (type);
unsigned int i;
for (i = 0; i < count; ++i)
{
if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
continue;
struct type *field_type = TYPE_FIELD_TYPE (type, i);
field_type = check_typedef (field_type);
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
int field_offset
= offset + TYPE_FIELD_BITPOS (type, i) / TARGET_CHAR_BIT;
switch (TYPE_CODE (field_type))
{
case TYPE_CODE_STRUCT:
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
analyse_inner (field_type, field_offset);
break;
default:
/* RiscV only flattens out structures. Anything else does not
need to be flattened, we just record the type, and when we
look at the analysis results we'll realise this is not a
structure we can special case, and pass the structure in
memory. */
if (m_number_of_fields < 2)
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
{
m_types[m_number_of_fields] = field_type;
m_offsets[m_number_of_fields] = field_offset;
}
m_number_of_fields++;
break;
}
/* RiscV only has special handling for structures with 1 or 2 scalar
fields, any more than that and the structure is just passed in
memory. We can safely drop out early when we find 3 or more
fields then. */
if (m_number_of_fields > 2)
return;
}
}
/* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
is a structure. Small structures on RiscV have some special case
handling in order that the structure might be passed in register.
Larger structures are passed in memory. After assigning location
information to AINFO, CINFO will have been updated. */
static void
riscv_call_arg_struct (struct riscv_arg_info *ainfo,
struct riscv_call_info *cinfo)
{
if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
{
struct riscv_struct_info sinfo;
sinfo.analyse (ainfo->type);
if (sinfo.number_of_fields () == 1
&& TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
{
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
/* The following is similar to RISCV_CALL_ARG_COMPLEX_FLOAT,
except we use the type of the complex field instead of the
type from AINFO, and the first location might be at a non-zero
offset. */
if (TYPE_LENGTH (sinfo.field_type (0)) <= (2 * cinfo->flen)
&& riscv_arg_regs_available (&cinfo->float_regs) >= 2
&& !ainfo->is_unnamed)
{
bool result;
int len = TYPE_LENGTH (sinfo.field_type (0)) / 2;
int offset = sinfo.field_offset (0);
result = riscv_assign_reg_location (&ainfo->argloc[0],
&cinfo->float_regs, len,
offset);
gdb_assert (result);
result = riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->float_regs, len,
(offset + len));
gdb_assert (result);
}
else
riscv_call_arg_scalar_int (ainfo, cinfo);
return;
}
if (sinfo.number_of_fields () == 1
&& TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
{
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
/* The following is similar to RISCV_CALL_ARG_SCALAR_FLOAT,
except we use the type of the first scalar field instead of
the type from AINFO. Also the location might be at a non-zero
offset. */
if (TYPE_LENGTH (sinfo.field_type (0)) > cinfo->flen
|| ainfo->is_unnamed)
riscv_call_arg_scalar_int (ainfo, cinfo);
else
{
int offset = sinfo.field_offset (0);
int len = TYPE_LENGTH (sinfo.field_type (0));
if (!riscv_assign_reg_location (&ainfo->argloc[0],
&cinfo->float_regs,
len, offset))
riscv_call_arg_scalar_int (ainfo, cinfo);
}
return;
}
if (sinfo.number_of_fields () == 2
&& TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
&& TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
&& TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
&& TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
&& riscv_arg_regs_available (&cinfo->float_regs) >= 2)
{
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
int len0 = TYPE_LENGTH (sinfo.field_type (0));
int offset = sinfo.field_offset (0);
if (!riscv_assign_reg_location (&ainfo->argloc[0],
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
&cinfo->float_regs, len0, offset))
error (_("failed during argument setup"));
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
int len1 = TYPE_LENGTH (sinfo.field_type (1));
offset = sinfo.field_offset (1);
gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
- TYPE_LENGTH (sinfo.field_type (0))));
if (!riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->float_regs,
len1, offset))
error (_("failed during argument setup"));
return;
}
if (sinfo.number_of_fields () == 2
&& riscv_arg_regs_available (&cinfo->int_regs) >= 1
&& (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
&& TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
&& is_integral_type (sinfo.field_type (1))
&& TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
{
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
int len0 = TYPE_LENGTH (sinfo.field_type (0));
int offset = sinfo.field_offset (0);
if (!riscv_assign_reg_location (&ainfo->argloc[0],
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
&cinfo->float_regs, len0, offset))
error (_("failed during argument setup"));
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
int len1 = TYPE_LENGTH (sinfo.field_type (1));
offset = sinfo.field_offset (1);
gdb_assert (len1 <= cinfo->xlen);
if (!riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->int_regs, len1, offset))
error (_("failed during argument setup"));
return;
}
if (sinfo.number_of_fields () == 2
&& riscv_arg_regs_available (&cinfo->int_regs) >= 1
&& (is_integral_type (sinfo.field_type (0))
&& TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
&& TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
&& TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
{
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
int len0 = TYPE_LENGTH (sinfo.field_type (0));
int len1 = TYPE_LENGTH (sinfo.field_type (1));
gdb_assert (len0 <= cinfo->xlen);
gdb_assert (len1 <= cinfo->flen);
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
int offset = sinfo.field_offset (0);
if (!riscv_assign_reg_location (&ainfo->argloc[0],
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
&cinfo->int_regs, len0, offset))
error (_("failed during argument setup"));
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
offset = sinfo.field_offset (1);
if (!riscv_assign_reg_location (&ainfo->argloc[1],
&cinfo->float_regs,
len1, offset))
error (_("failed during argument setup"));
return;
}
}
/* Non of the structure flattening cases apply, so we just pass using
the integer ABI. */
riscv_call_arg_scalar_int (ainfo, cinfo);
}
/* Assign a location to call (or return) argument AINFO, the location is
selected from CINFO which holds information about what call argument
locations are available for use next. The TYPE is the type of the
argument being passed, this information is recorded into AINFO (along
with some additional information derived from the type). IS_UNNAMED
is true if this is an unnamed (stdarg) argument, this info is also
recorded into AINFO.
After assigning a location to AINFO, CINFO will have been updated. */
static void
riscv_arg_location (struct gdbarch *gdbarch,
struct riscv_arg_info *ainfo,
struct riscv_call_info *cinfo,
struct type *type, bool is_unnamed)
{
ainfo->type = type;
ainfo->length = TYPE_LENGTH (ainfo->type);
ainfo->align = type_align (ainfo->type);
ainfo->is_unnamed = is_unnamed;
ainfo->contents = nullptr;
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
ainfo->argloc[0].c_length = 0;
ainfo->argloc[1].c_length = 0;
switch (TYPE_CODE (ainfo->type))
{
case TYPE_CODE_INT:
case TYPE_CODE_BOOL:
case TYPE_CODE_CHAR:
case TYPE_CODE_RANGE:
case TYPE_CODE_ENUM:
case TYPE_CODE_PTR:
if (ainfo->length <= cinfo->xlen)
{
ainfo->type = builtin_type (gdbarch)->builtin_long;
ainfo->length = cinfo->xlen;
}
else if (ainfo->length <= (2 * cinfo->xlen))
{
ainfo->type = builtin_type (gdbarch)->builtin_long_long;
ainfo->length = 2 * cinfo->xlen;
}
/* Recalculate the alignment requirement. */
ainfo->align = type_align (ainfo->type);
riscv_call_arg_scalar_int (ainfo, cinfo);
break;
case TYPE_CODE_FLT:
riscv_call_arg_scalar_float (ainfo, cinfo);
break;
case TYPE_CODE_COMPLEX:
riscv_call_arg_complex_float (ainfo, cinfo);
break;
case TYPE_CODE_STRUCT:
riscv_call_arg_struct (ainfo, cinfo);
break;
default:
riscv_call_arg_scalar_int (ainfo, cinfo);
break;
}
}
/* Used for printing debug information about the call argument location in
INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
addresses for the location of pass-by-reference and
arguments-on-the-stack memory areas. */
static void
riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
struct riscv_arg_info *info,
CORE_ADDR sp_refs, CORE_ADDR sp_args)
{
fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
TYPE_SAFE_NAME (info->type), info->length, info->align);
switch (info->argloc[0].loc_type)
{
case riscv_arg_info::location::in_reg:
fprintf_unfiltered
(stream, ", register %s",
gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
if (info->argloc[0].c_length < info->length)
{
switch (info->argloc[1].loc_type)
{
case riscv_arg_info::location::in_reg:
fprintf_unfiltered
(stream, ", register %s",
gdbarch_register_name (gdbarch,
info->argloc[1].loc_data.regno));
break;
case riscv_arg_info::location::on_stack:
fprintf_unfiltered (stream, ", on stack at offset 0x%x",
info->argloc[1].loc_data.offset);
break;
case riscv_arg_info::location::by_ref:
default:
/* The second location should never be a reference, any
argument being passed by reference just places its address
in the first location and is done. */
error (_("invalid argument location"));
break;
}
if (info->argloc[1].c_offset > info->argloc[0].c_length)
fprintf_unfiltered (stream, " (offset 0x%x)",
info->argloc[1].c_offset);
}
break;
case riscv_arg_info::location::on_stack:
fprintf_unfiltered (stream, ", on stack at offset 0x%x",
info->argloc[0].loc_data.offset);
break;
case riscv_arg_info::location::by_ref:
fprintf_unfiltered
(stream, ", by reference, data at offset 0x%x (%s)",
info->argloc[0].loc_data.offset,
core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
if (info->argloc[1].loc_type
== riscv_arg_info::location::in_reg)
fprintf_unfiltered
(stream, ", address in register %s",
gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
else
{
gdb_assert (info->argloc[1].loc_type
== riscv_arg_info::location::on_stack);
fprintf_unfiltered
(stream, ", address on stack at offset 0x%x (%s)",
info->argloc[1].loc_data.offset,
core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
}
break;
default:
gdb_assert_not_reached (_("unknown argument location type"));
}
}
/* Implement the push dummy call gdbarch callback. */
static CORE_ADDR
riscv_push_dummy_call (struct gdbarch *gdbarch,
struct value *function,
struct regcache *regcache,
CORE_ADDR bp_addr,
int nargs,
struct value **args,
CORE_ADDR sp,
Pass return_method to _push_dummy_call gdb/ChangeLog: * aarch64-tdep.c (aarch64_push_dummy_call): Replace arg with return_method. * alpha-tdep.c (alpha_push_dummy_call): Likewise. * amd64-tdep.c (amd64_push_arguments): Likewise. (amd64_push_dummy_call): Likewise. * amd64-windows-tdep.c (amd64_windows_push_arguments): Likewise. * arc-tdep.c (arc_push_dummy_call): Likewise. * arm-tdep.c (arm_push_dummy_call): Likewise. * avr-tdep.c (avr_push_dummy_call): Likewise. * bfin-tdep.c (bfin_push_dummy_call): Likewise. * cris-tdep.c (cris_push_dummy_call): Likewise. * csky-tdep.c (csky_push_dummy_call): Likewise. * frv-tdep.c (frv_push_dummy_call): Likewise. * gdbarch.c: Regenerate. * gdbarch.h: Regenerate. * gdbarch.sh (gdbarch_push_dummy_call): Replace arg with return_method. * h8300-tdep.c (h8300_push_dummy_call): Likewise. * hppa-tdep.c (hppa32_push_dummy_call): Likewise. (hppa64_push_dummy_call): Likewise. * i386-darwin-tdep.c (i386_darwin_push_dummy_call): Likewise. * i386-tdep.c (i386_push_dummy_call): Likewise. * ia64-tdep.c (ia64_push_dummy_call): Likewise. * infcall.c (call_function_by_hand_dummy): Likewise. * iq2000-tdep.c (iq2000_push_dummy_call): Likewise. * lm32-tdep.c (lm32_push_dummy_call): Likewise. * m32c-tdep.c (m32c_push_dummy_call): Likewise. * m32r-tdep.c (m32r_push_dummy_call): Likewise. * m68hc11-tdep.c (m68hc11_push_dummy_call): Likewise. * m68k-tdep.c (m68k_push_dummy_call): Likewise. * mep-tdep.c (mep_push_dummy_call): Likewise. * mips-tdep.c (mips_eabi_push_dummy_call): Likewise. (mips_n32n64_push_dummy_call): Likewise. (mips_o32_push_dummy_call): Likewise. (mips_o64_push_dummy_call): Likewise. * mn10300-tdep.c (mn10300_push_dummy_call): Likewise. * msp430-tdep.c (msp430_push_dummy_call): Likewise. * nds32-tdep.c (nds32_push_dummy_call): Likewise. * nios2-tdep.c (nios2_push_dummy_call): Likewise. * or1k-tdep.c (or1k_push_dummy_call): Likewise. * ppc-sysv-tdep.c (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * ppc-tdep.h (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * riscv-tdep.c (riscv_push_dummy_call): Likewise. * rl78-tdep.c (rl78_push_dummy_call): Likewise. * rs6000-aix-tdep.c (rs6000_push_dummy_call): Likewise. * rs6000-lynx178-tdep.c (rs6000_lynx178_push_dummy_call): Likewise. * rx-tdep.c (rx_push_dummy_call): Likewise. * s390-tdep.c (s390_push_dummy_call): Likewise. * score-tdep.c (score_push_dummy_call): Likewise. * sh-tdep.c (sh_push_dummy_call_fpu): Likewise. (sh_push_dummy_call_nofpu): Likewise. * sparc-tdep.c (sparc32_store_arguments): Likewise. (sparc32_push_dummy_call): Likewise. * sparc64-tdep.c (sparc64_store_arguments): Likewise. (sparc64_push_dummy_call): Likewise. * spu-tdep.c (spu_push_dummy_call): Likewise. * tic6x-tdep.c (tic6x_push_dummy_call): Likewise. * tilegx-tdep.c (tilegx_push_dummy_call): Likewise. * v850-tdep.c (v850_push_dummy_call): Likewise. * vax-tdep.c (vax_push_dummy_call): Likewise. * xstormy16-tdep.c (xstormy16_push_dummy_call): Likewise. * xtensa-tdep.c (xtensa_push_dummy_call): Likewise.
2018-11-16 12:21:04 +01:00
function_call_return_method return_method,
CORE_ADDR struct_addr)
{
int i;
CORE_ADDR sp_args, sp_refs;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct riscv_arg_info *arg_info =
(struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
struct riscv_call_info call_info (gdbarch);
CORE_ADDR osp = sp;
struct type *ftype = check_typedef (value_type (function));
if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
/* We'll use register $a0 if we're returning a struct. */
Pass return_method to _push_dummy_call gdb/ChangeLog: * aarch64-tdep.c (aarch64_push_dummy_call): Replace arg with return_method. * alpha-tdep.c (alpha_push_dummy_call): Likewise. * amd64-tdep.c (amd64_push_arguments): Likewise. (amd64_push_dummy_call): Likewise. * amd64-windows-tdep.c (amd64_windows_push_arguments): Likewise. * arc-tdep.c (arc_push_dummy_call): Likewise. * arm-tdep.c (arm_push_dummy_call): Likewise. * avr-tdep.c (avr_push_dummy_call): Likewise. * bfin-tdep.c (bfin_push_dummy_call): Likewise. * cris-tdep.c (cris_push_dummy_call): Likewise. * csky-tdep.c (csky_push_dummy_call): Likewise. * frv-tdep.c (frv_push_dummy_call): Likewise. * gdbarch.c: Regenerate. * gdbarch.h: Regenerate. * gdbarch.sh (gdbarch_push_dummy_call): Replace arg with return_method. * h8300-tdep.c (h8300_push_dummy_call): Likewise. * hppa-tdep.c (hppa32_push_dummy_call): Likewise. (hppa64_push_dummy_call): Likewise. * i386-darwin-tdep.c (i386_darwin_push_dummy_call): Likewise. * i386-tdep.c (i386_push_dummy_call): Likewise. * ia64-tdep.c (ia64_push_dummy_call): Likewise. * infcall.c (call_function_by_hand_dummy): Likewise. * iq2000-tdep.c (iq2000_push_dummy_call): Likewise. * lm32-tdep.c (lm32_push_dummy_call): Likewise. * m32c-tdep.c (m32c_push_dummy_call): Likewise. * m32r-tdep.c (m32r_push_dummy_call): Likewise. * m68hc11-tdep.c (m68hc11_push_dummy_call): Likewise. * m68k-tdep.c (m68k_push_dummy_call): Likewise. * mep-tdep.c (mep_push_dummy_call): Likewise. * mips-tdep.c (mips_eabi_push_dummy_call): Likewise. (mips_n32n64_push_dummy_call): Likewise. (mips_o32_push_dummy_call): Likewise. (mips_o64_push_dummy_call): Likewise. * mn10300-tdep.c (mn10300_push_dummy_call): Likewise. * msp430-tdep.c (msp430_push_dummy_call): Likewise. * nds32-tdep.c (nds32_push_dummy_call): Likewise. * nios2-tdep.c (nios2_push_dummy_call): Likewise. * or1k-tdep.c (or1k_push_dummy_call): Likewise. * ppc-sysv-tdep.c (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * ppc-tdep.h (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * riscv-tdep.c (riscv_push_dummy_call): Likewise. * rl78-tdep.c (rl78_push_dummy_call): Likewise. * rs6000-aix-tdep.c (rs6000_push_dummy_call): Likewise. * rs6000-lynx178-tdep.c (rs6000_lynx178_push_dummy_call): Likewise. * rx-tdep.c (rx_push_dummy_call): Likewise. * s390-tdep.c (s390_push_dummy_call): Likewise. * score-tdep.c (score_push_dummy_call): Likewise. * sh-tdep.c (sh_push_dummy_call_fpu): Likewise. (sh_push_dummy_call_nofpu): Likewise. * sparc-tdep.c (sparc32_store_arguments): Likewise. (sparc32_push_dummy_call): Likewise. * sparc64-tdep.c (sparc64_store_arguments): Likewise. (sparc64_push_dummy_call): Likewise. * spu-tdep.c (spu_push_dummy_call): Likewise. * tic6x-tdep.c (tic6x_push_dummy_call): Likewise. * tilegx-tdep.c (tilegx_push_dummy_call): Likewise. * v850-tdep.c (v850_push_dummy_call): Likewise. * vax-tdep.c (vax_push_dummy_call): Likewise. * xstormy16-tdep.c (xstormy16_push_dummy_call): Likewise. * xtensa-tdep.c (xtensa_push_dummy_call): Likewise.
2018-11-16 12:21:04 +01:00
if (return_method == return_method_struct)
++call_info.int_regs.next_regnum;
Simple -Wshadow=local fixes This fixes all the straightforward -Wshadow=local warnings in gdb. A few standard approaches are used here: * Renaming an inner (or outer, but more commonly inner) variable; * Lowering a declaration to avoid a clash; * Moving a declaration into a more inner scope to avoid a clash, including the special case of moving a declaration into a loop header. I did not consider any of the changes in this patch to be particularly noteworthy, though of course they should all still be examined. gdb/ChangeLog 2018-10-04 Tom Tromey <tom@tromey.com> * ctf.c (SET_ARRAY_FIELD): Rename "u32". * p-valprint.c (pascal_val_print): Split inner "i" variable. * xtensa-tdep.c (xtensa_push_dummy_call): Declare "i" in loop header. * xstormy16-tdep.c (xstormy16_push_dummy_call): Declare "val" in more inner scope. * xcoffread.c (read_xcoff_symtab): Rename inner "symbol". * varobj.c (varobj_update): Rename inner "newobj", "type_changed". * valprint.c (generic_emit_char): Rename inner "buf". * valops.c (find_overload_match): Rename inner "temp". (value_struct_elt_for_reference): Declare "v" in more inner scope. * v850-tdep.c (v850_push_dummy_call): Rename "len". * unittests/array-view-selftests.c (run_tests): Rename inner "vec". * tui/tui-stack.c (tui_show_frame_info): Declare "i" in loop header. * tracepoint.c (merge_uploaded_trace_state_variables): Declare "tsv" in more inner scope. (print_one_static_tracepoint_marker): Rename inner "tuple_emitter". * tic6x-tdep.c (tic6x_analyze_prologue): Declare "inst" lower. (tic6x_push_dummy_call): Don't redeclare "addr". * target-float.c: Declare "dto" lower. * symtab.c (lookup_local_symbol): Rename inner "sym". (find_pc_sect_line): Rename inner "pc". * stack.c (print_frame): Don't redeclare "gdbarch". (return_command): Rename inner "gdbarch". * s390-tdep.c (s390_prologue_frame_unwind_cache): Renam inner "sp". * rust-lang.c (rust_internal_print_type): Declare "i" in loop header. * rs6000-tdep.c (ppc_process_record): Rename inner "addr". * riscv-tdep.c (riscv_push_dummy_call): Declare "info" in inner scope. * remote.c (remote_target::update_thread_list): Don't redeclare "tp". (remote_target::process_initial_stop_replies): Rename inner "thread". (remote_target::remote_parse_stop_reply): Don't redeclare "p". (remote_target::wait_as): Don't redeclare "stop_reply". (remote_target::get_thread_local_address): Rename inner "result". (remote_target::get_tib_address): Likewise.
2018-04-22 00:16:27 +02:00
for (i = 0; i < nargs; ++i)
{
struct value *arg_value;
struct type *arg_type;
Simple -Wshadow=local fixes This fixes all the straightforward -Wshadow=local warnings in gdb. A few standard approaches are used here: * Renaming an inner (or outer, but more commonly inner) variable; * Lowering a declaration to avoid a clash; * Moving a declaration into a more inner scope to avoid a clash, including the special case of moving a declaration into a loop header. I did not consider any of the changes in this patch to be particularly noteworthy, though of course they should all still be examined. gdb/ChangeLog 2018-10-04 Tom Tromey <tom@tromey.com> * ctf.c (SET_ARRAY_FIELD): Rename "u32". * p-valprint.c (pascal_val_print): Split inner "i" variable. * xtensa-tdep.c (xtensa_push_dummy_call): Declare "i" in loop header. * xstormy16-tdep.c (xstormy16_push_dummy_call): Declare "val" in more inner scope. * xcoffread.c (read_xcoff_symtab): Rename inner "symbol". * varobj.c (varobj_update): Rename inner "newobj", "type_changed". * valprint.c (generic_emit_char): Rename inner "buf". * valops.c (find_overload_match): Rename inner "temp". (value_struct_elt_for_reference): Declare "v" in more inner scope. * v850-tdep.c (v850_push_dummy_call): Rename "len". * unittests/array-view-selftests.c (run_tests): Rename inner "vec". * tui/tui-stack.c (tui_show_frame_info): Declare "i" in loop header. * tracepoint.c (merge_uploaded_trace_state_variables): Declare "tsv" in more inner scope. (print_one_static_tracepoint_marker): Rename inner "tuple_emitter". * tic6x-tdep.c (tic6x_analyze_prologue): Declare "inst" lower. (tic6x_push_dummy_call): Don't redeclare "addr". * target-float.c: Declare "dto" lower. * symtab.c (lookup_local_symbol): Rename inner "sym". (find_pc_sect_line): Rename inner "pc". * stack.c (print_frame): Don't redeclare "gdbarch". (return_command): Rename inner "gdbarch". * s390-tdep.c (s390_prologue_frame_unwind_cache): Renam inner "sp". * rust-lang.c (rust_internal_print_type): Declare "i" in loop header. * rs6000-tdep.c (ppc_process_record): Rename inner "addr". * riscv-tdep.c (riscv_push_dummy_call): Declare "info" in inner scope. * remote.c (remote_target::update_thread_list): Don't redeclare "tp". (remote_target::process_initial_stop_replies): Rename inner "thread". (remote_target::remote_parse_stop_reply): Don't redeclare "p". (remote_target::wait_as): Don't redeclare "stop_reply". (remote_target::get_thread_local_address): Rename inner "result". (remote_target::get_tib_address): Likewise.
2018-04-22 00:16:27 +02:00
struct riscv_arg_info *info = &arg_info[i];
arg_value = args[i];
arg_type = check_typedef (value_type (arg_value));
riscv_arg_location (gdbarch, info, &call_info, arg_type,
TYPE_VARARGS (ftype) && i >= TYPE_NFIELDS (ftype));
if (info->type != arg_type)
arg_value = value_cast (info->type, arg_value);
info->contents = value_contents (arg_value);
}
/* Adjust the stack pointer and align it. */
sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
if (riscv_debug_infcall > 0)
{
fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
(riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
call_info.xlen, call_info.flen);
Pass return_method to _push_dummy_call gdb/ChangeLog: * aarch64-tdep.c (aarch64_push_dummy_call): Replace arg with return_method. * alpha-tdep.c (alpha_push_dummy_call): Likewise. * amd64-tdep.c (amd64_push_arguments): Likewise. (amd64_push_dummy_call): Likewise. * amd64-windows-tdep.c (amd64_windows_push_arguments): Likewise. * arc-tdep.c (arc_push_dummy_call): Likewise. * arm-tdep.c (arm_push_dummy_call): Likewise. * avr-tdep.c (avr_push_dummy_call): Likewise. * bfin-tdep.c (bfin_push_dummy_call): Likewise. * cris-tdep.c (cris_push_dummy_call): Likewise. * csky-tdep.c (csky_push_dummy_call): Likewise. * frv-tdep.c (frv_push_dummy_call): Likewise. * gdbarch.c: Regenerate. * gdbarch.h: Regenerate. * gdbarch.sh (gdbarch_push_dummy_call): Replace arg with return_method. * h8300-tdep.c (h8300_push_dummy_call): Likewise. * hppa-tdep.c (hppa32_push_dummy_call): Likewise. (hppa64_push_dummy_call): Likewise. * i386-darwin-tdep.c (i386_darwin_push_dummy_call): Likewise. * i386-tdep.c (i386_push_dummy_call): Likewise. * ia64-tdep.c (ia64_push_dummy_call): Likewise. * infcall.c (call_function_by_hand_dummy): Likewise. * iq2000-tdep.c (iq2000_push_dummy_call): Likewise. * lm32-tdep.c (lm32_push_dummy_call): Likewise. * m32c-tdep.c (m32c_push_dummy_call): Likewise. * m32r-tdep.c (m32r_push_dummy_call): Likewise. * m68hc11-tdep.c (m68hc11_push_dummy_call): Likewise. * m68k-tdep.c (m68k_push_dummy_call): Likewise. * mep-tdep.c (mep_push_dummy_call): Likewise. * mips-tdep.c (mips_eabi_push_dummy_call): Likewise. (mips_n32n64_push_dummy_call): Likewise. (mips_o32_push_dummy_call): Likewise. (mips_o64_push_dummy_call): Likewise. * mn10300-tdep.c (mn10300_push_dummy_call): Likewise. * msp430-tdep.c (msp430_push_dummy_call): Likewise. * nds32-tdep.c (nds32_push_dummy_call): Likewise. * nios2-tdep.c (nios2_push_dummy_call): Likewise. * or1k-tdep.c (or1k_push_dummy_call): Likewise. * ppc-sysv-tdep.c (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * ppc-tdep.h (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * riscv-tdep.c (riscv_push_dummy_call): Likewise. * rl78-tdep.c (rl78_push_dummy_call): Likewise. * rs6000-aix-tdep.c (rs6000_push_dummy_call): Likewise. * rs6000-lynx178-tdep.c (rs6000_lynx178_push_dummy_call): Likewise. * rx-tdep.c (rx_push_dummy_call): Likewise. * s390-tdep.c (s390_push_dummy_call): Likewise. * score-tdep.c (score_push_dummy_call): Likewise. * sh-tdep.c (sh_push_dummy_call_fpu): Likewise. (sh_push_dummy_call_nofpu): Likewise. * sparc-tdep.c (sparc32_store_arguments): Likewise. (sparc32_push_dummy_call): Likewise. * sparc64-tdep.c (sparc64_store_arguments): Likewise. (sparc64_push_dummy_call): Likewise. * spu-tdep.c (spu_push_dummy_call): Likewise. * tic6x-tdep.c (tic6x_push_dummy_call): Likewise. * tilegx-tdep.c (tilegx_push_dummy_call): Likewise. * v850-tdep.c (v850_push_dummy_call): Likewise. * vax-tdep.c (vax_push_dummy_call): Likewise. * xstormy16-tdep.c (xstormy16_push_dummy_call): Likewise. * xtensa-tdep.c (xtensa_push_dummy_call): Likewise.
2018-11-16 12:21:04 +01:00
if (return_method == return_method_struct)
fprintf_unfiltered (gdb_stdlog,
"[*] struct return pointer in register $A0\n");
for (i = 0; i < nargs; ++i)
{
struct riscv_arg_info *info = &arg_info [i];
fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
fprintf_unfiltered (gdb_stdlog, "\n");
}
if (call_info.memory.arg_offset > 0
|| call_info.memory.ref_offset > 0)
{
fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
core_addr_to_string (osp));
fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
call_info.memory.arg_offset);
fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
call_info.memory.ref_offset);
fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
core_addr_to_string_nz (osp - sp));
}
}
/* Now load the argument into registers, or onto the stack. */
Pass return_method to _push_dummy_call gdb/ChangeLog: * aarch64-tdep.c (aarch64_push_dummy_call): Replace arg with return_method. * alpha-tdep.c (alpha_push_dummy_call): Likewise. * amd64-tdep.c (amd64_push_arguments): Likewise. (amd64_push_dummy_call): Likewise. * amd64-windows-tdep.c (amd64_windows_push_arguments): Likewise. * arc-tdep.c (arc_push_dummy_call): Likewise. * arm-tdep.c (arm_push_dummy_call): Likewise. * avr-tdep.c (avr_push_dummy_call): Likewise. * bfin-tdep.c (bfin_push_dummy_call): Likewise. * cris-tdep.c (cris_push_dummy_call): Likewise. * csky-tdep.c (csky_push_dummy_call): Likewise. * frv-tdep.c (frv_push_dummy_call): Likewise. * gdbarch.c: Regenerate. * gdbarch.h: Regenerate. * gdbarch.sh (gdbarch_push_dummy_call): Replace arg with return_method. * h8300-tdep.c (h8300_push_dummy_call): Likewise. * hppa-tdep.c (hppa32_push_dummy_call): Likewise. (hppa64_push_dummy_call): Likewise. * i386-darwin-tdep.c (i386_darwin_push_dummy_call): Likewise. * i386-tdep.c (i386_push_dummy_call): Likewise. * ia64-tdep.c (ia64_push_dummy_call): Likewise. * infcall.c (call_function_by_hand_dummy): Likewise. * iq2000-tdep.c (iq2000_push_dummy_call): Likewise. * lm32-tdep.c (lm32_push_dummy_call): Likewise. * m32c-tdep.c (m32c_push_dummy_call): Likewise. * m32r-tdep.c (m32r_push_dummy_call): Likewise. * m68hc11-tdep.c (m68hc11_push_dummy_call): Likewise. * m68k-tdep.c (m68k_push_dummy_call): Likewise. * mep-tdep.c (mep_push_dummy_call): Likewise. * mips-tdep.c (mips_eabi_push_dummy_call): Likewise. (mips_n32n64_push_dummy_call): Likewise. (mips_o32_push_dummy_call): Likewise. (mips_o64_push_dummy_call): Likewise. * mn10300-tdep.c (mn10300_push_dummy_call): Likewise. * msp430-tdep.c (msp430_push_dummy_call): Likewise. * nds32-tdep.c (nds32_push_dummy_call): Likewise. * nios2-tdep.c (nios2_push_dummy_call): Likewise. * or1k-tdep.c (or1k_push_dummy_call): Likewise. * ppc-sysv-tdep.c (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * ppc-tdep.h (ppc_sysv_abi_push_dummy_call): Likewise. (ppc64_sysv_abi_push_dummy_call): Likewise. * riscv-tdep.c (riscv_push_dummy_call): Likewise. * rl78-tdep.c (rl78_push_dummy_call): Likewise. * rs6000-aix-tdep.c (rs6000_push_dummy_call): Likewise. * rs6000-lynx178-tdep.c (rs6000_lynx178_push_dummy_call): Likewise. * rx-tdep.c (rx_push_dummy_call): Likewise. * s390-tdep.c (s390_push_dummy_call): Likewise. * score-tdep.c (score_push_dummy_call): Likewise. * sh-tdep.c (sh_push_dummy_call_fpu): Likewise. (sh_push_dummy_call_nofpu): Likewise. * sparc-tdep.c (sparc32_store_arguments): Likewise. (sparc32_push_dummy_call): Likewise. * sparc64-tdep.c (sparc64_store_arguments): Likewise. (sparc64_push_dummy_call): Likewise. * spu-tdep.c (spu_push_dummy_call): Likewise. * tic6x-tdep.c (tic6x_push_dummy_call): Likewise. * tilegx-tdep.c (tilegx_push_dummy_call): Likewise. * v850-tdep.c (v850_push_dummy_call): Likewise. * vax-tdep.c (vax_push_dummy_call): Likewise. * xstormy16-tdep.c (xstormy16_push_dummy_call): Likewise. * xtensa-tdep.c (xtensa_push_dummy_call): Likewise.
2018-11-16 12:21:04 +01:00
if (return_method == return_method_struct)
{
gdb_byte buf[sizeof (LONGEST)];
store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
regcache->cooked_write (RISCV_A0_REGNUM, buf);
}
for (i = 0; i < nargs; ++i)
{
CORE_ADDR dst;
int second_arg_length = 0;
const gdb_byte *second_arg_data;
struct riscv_arg_info *info = &arg_info [i];
gdb_assert (info->length > 0);
switch (info->argloc[0].loc_type)
{
case riscv_arg_info::location::in_reg:
{
gdb_byte tmp [sizeof (ULONGEST)];
gdb_assert (info->argloc[0].c_length <= info->length);
/* FP values in FP registers must be NaN-boxed. */
if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
&& info->argloc[0].c_length < call_info.flen)
memset (tmp, -1, sizeof (tmp));
else
memset (tmp, 0, sizeof (tmp));
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
memcpy (tmp, (info->contents + info->argloc[0].c_offset),
info->argloc[0].c_length);
regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
second_arg_length =
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
(((info->argloc[0].c_length + info->argloc[0].c_offset) < info->length)
? info->argloc[1].c_length : 0);
second_arg_data = info->contents + info->argloc[1].c_offset;
}
break;
case riscv_arg_info::location::on_stack:
dst = sp_args + info->argloc[0].loc_data.offset;
write_memory (dst, info->contents, info->length);
second_arg_length = 0;
break;
case riscv_arg_info::location::by_ref:
dst = sp_refs + info->argloc[0].loc_data.offset;
write_memory (dst, info->contents, info->length);
second_arg_length = call_info.xlen;
second_arg_data = (gdb_byte *) &dst;
break;
default:
gdb_assert_not_reached (_("unknown argument location type"));
}
if (second_arg_length > 0)
{
switch (info->argloc[1].loc_type)
{
case riscv_arg_info::location::in_reg:
{
gdb_byte tmp [sizeof (ULONGEST)];
gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
&& second_arg_length <= call_info.flen)
|| second_arg_length <= call_info.xlen);
/* FP values in FP registers must be NaN-boxed. */
if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
&& second_arg_length < call_info.flen)
memset (tmp, -1, sizeof (tmp));
else
memset (tmp, 0, sizeof (tmp));
memcpy (tmp, second_arg_data, second_arg_length);
regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
}
break;
case riscv_arg_info::location::on_stack:
{
CORE_ADDR arg_addr;
arg_addr = sp_args + info->argloc[1].loc_data.offset;
write_memory (arg_addr, second_arg_data, second_arg_length);
break;
}
case riscv_arg_info::location::by_ref:
default:
/* The second location should never be a reference, any
argument being passed by reference just places its address
in the first location and is done. */
error (_("invalid argument location"));
break;
}
}
}
/* Set the dummy return value to bp_addr.
A dummy breakpoint will be setup to execute the call. */
if (riscv_debug_infcall > 0)
fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
core_addr_to_string (bp_addr));
regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
/* Finally, update the stack pointer. */
if (riscv_debug_infcall > 0)
fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
core_addr_to_string (sp));
regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
return sp;
}
/* Implement the return_value gdbarch method. */
static enum return_value_convention
riscv_return_value (struct gdbarch *gdbarch,
struct value *function,
struct type *type,
struct regcache *regcache,
gdb_byte *readbuf,
const gdb_byte *writebuf)
{
struct riscv_call_info call_info (gdbarch);
struct riscv_arg_info info;
struct type *arg_type;
arg_type = check_typedef (type);
riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
if (riscv_debug_infcall > 0)
{
fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
fprintf_unfiltered (gdb_stdlog, "[R] ");
riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
fprintf_unfiltered (gdb_stdlog, "\n");
}
if (readbuf != nullptr || writebuf != nullptr)
{
gdb/riscv: Prevent buffer overflow in riscv_return_value The existing code for reading and writing the return value can overflow the passed in buffers in a couple of situations. This commit aims to resolve these issues. The problems were detected using valgrind, here are two examples, first from gdb.base/structs.exp: (gdb) p/x fun9() ==31353== Invalid write of size 8 ==31353== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==31353== by 0x632EBB: memcpy (string_fortified.h:34) ==31353== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==31353== by 0x659D3F: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2593) ==31353== by 0x583641: get_call_return_value (infcall.c:448) ==31353== by 0x583641: call_thread_fsm_should_stop(thread_fsm*, thread_info*) (infcall.c:546) ==31353== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==31353== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==31353== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==31353== by 0x6CA34B: wait_sync_command_done() (top.c:503) ==31353== by 0x584653: run_inferior_call (infcall.c:621) ... And from gdb.base/call-sc.exp: (gdb) advance fun fun () at /gdb/gdb/testsuite/gdb.base/call-sc.c:41 41 return foo; (gdb) finish ==1968== Invalid write of size 8 ==1968== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==1968== by 0x632EBB: memcpy (string_fortified.h:34) ==1968== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==1968== by 0x659D01: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2576) ==1968== by 0x5891E4: get_return_value(value*, type*) (infcmd.c:1640) ==1968== by 0x5892C4: finish_command_fsm_should_stop(thread_fsm*, thread_info*) (infcmd.c:1808) ==1968== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==1968== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==1968== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==1968== by 0x6CA34B: wait_sync_command_done() (top.c:503) ... There are a couple of problems with the existing code, that are all related. In riscv_call_arg_struct we incorrectly rounded up the size of a structure argument. This is unnecessary, and caused GDB to read too much data into the output buffer when extracting a struct return value. In fixing this it became clear that we were incorrectly assuming that any value being placed in a register (or read from a register) would always access the entire register. This is not true, for example a 9-byte struct on a 64-bit target places 8-bytes in one registers and 1-byte in a second register (assuming available registers). To handle this I switch from using cooked_read to cooked_read_part. Finally, when processing basic integer return value types these are extended to xlen sized types and then passed in registers. We currently don't handle this type expansion in riscv_return_value, but we do in riscv_push_dummy_call. The result is that small integer types (like char) result in a full xlen sized register being written into the output buffer, which results in buffer overflow. To address this issue we now create a value of the expanded type and use this values contents buffer to hold the return value before casting the value down to the smaller expected type. This patch resolves all of the valgrind issues I have found so far, and causes no regressions. Tested against RV32/64 with and without floating point support. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_struct): Don't adjust size before assigning locations. (riscv_return_value): Take more care not to read/write outside of argument buffer. Cast return value between the declared type and the abi type.
2018-11-27 14:41:44 +01:00
unsigned int arg_len;
struct value *abi_val;
gdb_byte *old_readbuf = nullptr;
int regnum;
/* We only do one thing at a time. */
gdb_assert (readbuf == nullptr || writebuf == nullptr);
/* In some cases the argument is not returned as the declared type,
and we need to cast to or from the ABI type in order to
correctly access the argument. When writing to the machine we
do the cast here, when reading from the machine the cast occurs
later, after extracting the value. As the ABI type can be
larger than the declared type, then the read or write buffers
passed in might be too small. Here we ensure that we are using
buffers of sufficient size. */
if (writebuf != nullptr)
{
struct value *arg_val = value_from_contents (arg_type, writebuf);
abi_val = value_cast (info.type, arg_val);
writebuf = value_contents_raw (abi_val);
}
else
{
abi_val = allocate_value (info.type);
old_readbuf = readbuf;
readbuf = value_contents_raw (abi_val);
}
arg_len = TYPE_LENGTH (info.type);
switch (info.argloc[0].loc_type)
{
/* Return value in register(s). */
case riscv_arg_info::location::in_reg:
{
regnum = info.argloc[0].loc_data.regno;
gdb/riscv: Prevent buffer overflow in riscv_return_value The existing code for reading and writing the return value can overflow the passed in buffers in a couple of situations. This commit aims to resolve these issues. The problems were detected using valgrind, here are two examples, first from gdb.base/structs.exp: (gdb) p/x fun9() ==31353== Invalid write of size 8 ==31353== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==31353== by 0x632EBB: memcpy (string_fortified.h:34) ==31353== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==31353== by 0x659D3F: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2593) ==31353== by 0x583641: get_call_return_value (infcall.c:448) ==31353== by 0x583641: call_thread_fsm_should_stop(thread_fsm*, thread_info*) (infcall.c:546) ==31353== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==31353== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==31353== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==31353== by 0x6CA34B: wait_sync_command_done() (top.c:503) ==31353== by 0x584653: run_inferior_call (infcall.c:621) ... And from gdb.base/call-sc.exp: (gdb) advance fun fun () at /gdb/gdb/testsuite/gdb.base/call-sc.c:41 41 return foo; (gdb) finish ==1968== Invalid write of size 8 ==1968== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==1968== by 0x632EBB: memcpy (string_fortified.h:34) ==1968== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==1968== by 0x659D01: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2576) ==1968== by 0x5891E4: get_return_value(value*, type*) (infcmd.c:1640) ==1968== by 0x5892C4: finish_command_fsm_should_stop(thread_fsm*, thread_info*) (infcmd.c:1808) ==1968== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==1968== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==1968== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==1968== by 0x6CA34B: wait_sync_command_done() (top.c:503) ... There are a couple of problems with the existing code, that are all related. In riscv_call_arg_struct we incorrectly rounded up the size of a structure argument. This is unnecessary, and caused GDB to read too much data into the output buffer when extracting a struct return value. In fixing this it became clear that we were incorrectly assuming that any value being placed in a register (or read from a register) would always access the entire register. This is not true, for example a 9-byte struct on a 64-bit target places 8-bytes in one registers and 1-byte in a second register (assuming available registers). To handle this I switch from using cooked_read to cooked_read_part. Finally, when processing basic integer return value types these are extended to xlen sized types and then passed in registers. We currently don't handle this type expansion in riscv_return_value, but we do in riscv_push_dummy_call. The result is that small integer types (like char) result in a full xlen sized register being written into the output buffer, which results in buffer overflow. To address this issue we now create a value of the expanded type and use this values contents buffer to hold the return value before casting the value down to the smaller expected type. This patch resolves all of the valgrind issues I have found so far, and causes no regressions. Tested against RV32/64 with and without floating point support. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_struct): Don't adjust size before assigning locations. (riscv_return_value): Take more care not to read/write outside of argument buffer. Cast return value between the declared type and the abi type.
2018-11-27 14:41:44 +01:00
gdb_assert (info.argloc[0].c_length <= arg_len);
gdb_assert (info.argloc[0].c_length
<= register_size (gdbarch, regnum));
if (readbuf)
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
{
gdb_byte *ptr = readbuf + info.argloc[0].c_offset;
regcache->cooked_read_part (regnum, 0,
info.argloc[0].c_length,
ptr);
}
if (writebuf)
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
{
const gdb_byte *ptr = writebuf + info.argloc[0].c_offset;
regcache->cooked_write_part (regnum, 0,
info.argloc[0].c_length,
ptr);
}
/* A return value in register can have a second part in a
second register. */
gdb/riscv: Handle empty C++ structs during argument passing This commit resolves a large number of failures in the test script gdb.base/infcall-nested-structs.exp which were caused by GDB (for RISC-V) incorrectly handling empty C++ structures when preparing arguments for a dummy call, or collecting a return value. The issue is further complicated in that there was a bug in GCC, such that in some cases GCC would generate incorrect code when passing a small structure that contained empty sub-structures. This was fixed in GCC trunk on 5-March-2019, so in order to see the best results with this patch you'll need a recent version of GCC. Anything that used to work should continue to work after this patch, regardless of GCC version being used. The fix in this commit is that GDB now pays more attention to the offset of fields within a structure when preparing arguments as in C++ an empty structure has a non-zero size, this is an example: struct s1 { struct s2 { } empty; int f; }; We previously assumed that 'f' was at offset 0 inside type 's1', however this is not the case in C++ as 's2' has size 1, and with alignment 'f' is likely at some even bigger offset inside 's1'. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_complex_float): Fix offset of first component to 0. (riscv_struct_info::riscv_struct_info): Initialise m_offsets member. (riscv_struct_info::analyse): New implementation using new analyse_inner member function. (riscv_struct_info::field_offset): New member function. (riscv_struct_info::m_offsets): New member variable. (riscv_struct_info::analyse_inner): New private member function, takes the old implementation of riscv_struct_info::analyse but extended to track field offsets. (riscv_call_arg_struct): Update the struct folding special cases to handle cases where empty C++ structs, which are non-zero length, are found. (riscv_arg_location): Initialise the length of each location, a non-zero length now indicates the location is in use. (riscv_push_dummy_call): Allow for the first location having a non-zero offset when setting up arguments. (riscv_return_value): Likewise, but for return values.
2019-04-05 14:50:19 +02:00
if (info.argloc[1].c_length > 0)
{
switch (info.argloc[1].loc_type)
{
case riscv_arg_info::location::in_reg:
regnum = info.argloc[1].loc_data.regno;
gdb/riscv: Prevent buffer overflow in riscv_return_value The existing code for reading and writing the return value can overflow the passed in buffers in a couple of situations. This commit aims to resolve these issues. The problems were detected using valgrind, here are two examples, first from gdb.base/structs.exp: (gdb) p/x fun9() ==31353== Invalid write of size 8 ==31353== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==31353== by 0x632EBB: memcpy (string_fortified.h:34) ==31353== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==31353== by 0x659D3F: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2593) ==31353== by 0x583641: get_call_return_value (infcall.c:448) ==31353== by 0x583641: call_thread_fsm_should_stop(thread_fsm*, thread_info*) (infcall.c:546) ==31353== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==31353== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==31353== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==31353== by 0x6CA34B: wait_sync_command_done() (top.c:503) ==31353== by 0x584653: run_inferior_call (infcall.c:621) ... And from gdb.base/call-sc.exp: (gdb) advance fun fun () at /gdb/gdb/testsuite/gdb.base/call-sc.c:41 41 return foo; (gdb) finish ==1968== Invalid write of size 8 ==1968== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==1968== by 0x632EBB: memcpy (string_fortified.h:34) ==1968== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==1968== by 0x659D01: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2576) ==1968== by 0x5891E4: get_return_value(value*, type*) (infcmd.c:1640) ==1968== by 0x5892C4: finish_command_fsm_should_stop(thread_fsm*, thread_info*) (infcmd.c:1808) ==1968== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==1968== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==1968== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==1968== by 0x6CA34B: wait_sync_command_done() (top.c:503) ... There are a couple of problems with the existing code, that are all related. In riscv_call_arg_struct we incorrectly rounded up the size of a structure argument. This is unnecessary, and caused GDB to read too much data into the output buffer when extracting a struct return value. In fixing this it became clear that we were incorrectly assuming that any value being placed in a register (or read from a register) would always access the entire register. This is not true, for example a 9-byte struct on a 64-bit target places 8-bytes in one registers and 1-byte in a second register (assuming available registers). To handle this I switch from using cooked_read to cooked_read_part. Finally, when processing basic integer return value types these are extended to xlen sized types and then passed in registers. We currently don't handle this type expansion in riscv_return_value, but we do in riscv_push_dummy_call. The result is that small integer types (like char) result in a full xlen sized register being written into the output buffer, which results in buffer overflow. To address this issue we now create a value of the expanded type and use this values contents buffer to hold the return value before casting the value down to the smaller expected type. This patch resolves all of the valgrind issues I have found so far, and causes no regressions. Tested against RV32/64 with and without floating point support. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_struct): Don't adjust size before assigning locations. (riscv_return_value): Take more care not to read/write outside of argument buffer. Cast return value between the declared type and the abi type.
2018-11-27 14:41:44 +01:00
gdb_assert ((info.argloc[0].c_length
+ info.argloc[1].c_length) <= arg_len);
gdb_assert (info.argloc[1].c_length
<= register_size (gdbarch, regnum));
if (readbuf)
{
readbuf += info.argloc[1].c_offset;
gdb/riscv: Prevent buffer overflow in riscv_return_value The existing code for reading and writing the return value can overflow the passed in buffers in a couple of situations. This commit aims to resolve these issues. The problems were detected using valgrind, here are two examples, first from gdb.base/structs.exp: (gdb) p/x fun9() ==31353== Invalid write of size 8 ==31353== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==31353== by 0x632EBB: memcpy (string_fortified.h:34) ==31353== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==31353== by 0x659D3F: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2593) ==31353== by 0x583641: get_call_return_value (infcall.c:448) ==31353== by 0x583641: call_thread_fsm_should_stop(thread_fsm*, thread_info*) (infcall.c:546) ==31353== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==31353== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==31353== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==31353== by 0x6CA34B: wait_sync_command_done() (top.c:503) ==31353== by 0x584653: run_inferior_call (infcall.c:621) ... And from gdb.base/call-sc.exp: (gdb) advance fun fun () at /gdb/gdb/testsuite/gdb.base/call-sc.c:41 41 return foo; (gdb) finish ==1968== Invalid write of size 8 ==1968== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==1968== by 0x632EBB: memcpy (string_fortified.h:34) ==1968== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==1968== by 0x659D01: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2576) ==1968== by 0x5891E4: get_return_value(value*, type*) (infcmd.c:1640) ==1968== by 0x5892C4: finish_command_fsm_should_stop(thread_fsm*, thread_info*) (infcmd.c:1808) ==1968== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==1968== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==1968== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==1968== by 0x6CA34B: wait_sync_command_done() (top.c:503) ... There are a couple of problems with the existing code, that are all related. In riscv_call_arg_struct we incorrectly rounded up the size of a structure argument. This is unnecessary, and caused GDB to read too much data into the output buffer when extracting a struct return value. In fixing this it became clear that we were incorrectly assuming that any value being placed in a register (or read from a register) would always access the entire register. This is not true, for example a 9-byte struct on a 64-bit target places 8-bytes in one registers and 1-byte in a second register (assuming available registers). To handle this I switch from using cooked_read to cooked_read_part. Finally, when processing basic integer return value types these are extended to xlen sized types and then passed in registers. We currently don't handle this type expansion in riscv_return_value, but we do in riscv_push_dummy_call. The result is that small integer types (like char) result in a full xlen sized register being written into the output buffer, which results in buffer overflow. To address this issue we now create a value of the expanded type and use this values contents buffer to hold the return value before casting the value down to the smaller expected type. This patch resolves all of the valgrind issues I have found so far, and causes no regressions. Tested against RV32/64 with and without floating point support. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_struct): Don't adjust size before assigning locations. (riscv_return_value): Take more care not to read/write outside of argument buffer. Cast return value between the declared type and the abi type.
2018-11-27 14:41:44 +01:00
regcache->cooked_read_part (regnum, 0,
info.argloc[1].c_length,
readbuf);
}
if (writebuf)
{
writebuf += info.argloc[1].c_offset;
gdb/riscv: Prevent buffer overflow in riscv_return_value The existing code for reading and writing the return value can overflow the passed in buffers in a couple of situations. This commit aims to resolve these issues. The problems were detected using valgrind, here are two examples, first from gdb.base/structs.exp: (gdb) p/x fun9() ==31353== Invalid write of size 8 ==31353== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==31353== by 0x632EBB: memcpy (string_fortified.h:34) ==31353== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==31353== by 0x659D3F: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2593) ==31353== by 0x583641: get_call_return_value (infcall.c:448) ==31353== by 0x583641: call_thread_fsm_should_stop(thread_fsm*, thread_info*) (infcall.c:546) ==31353== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==31353== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==31353== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==31353== by 0x6CA34B: wait_sync_command_done() (top.c:503) ==31353== by 0x584653: run_inferior_call (infcall.c:621) ... And from gdb.base/call-sc.exp: (gdb) advance fun fun () at /gdb/gdb/testsuite/gdb.base/call-sc.c:41 41 return foo; (gdb) finish ==1968== Invalid write of size 8 ==1968== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==1968== by 0x632EBB: memcpy (string_fortified.h:34) ==1968== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==1968== by 0x659D01: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2576) ==1968== by 0x5891E4: get_return_value(value*, type*) (infcmd.c:1640) ==1968== by 0x5892C4: finish_command_fsm_should_stop(thread_fsm*, thread_info*) (infcmd.c:1808) ==1968== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==1968== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==1968== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==1968== by 0x6CA34B: wait_sync_command_done() (top.c:503) ... There are a couple of problems with the existing code, that are all related. In riscv_call_arg_struct we incorrectly rounded up the size of a structure argument. This is unnecessary, and caused GDB to read too much data into the output buffer when extracting a struct return value. In fixing this it became clear that we were incorrectly assuming that any value being placed in a register (or read from a register) would always access the entire register. This is not true, for example a 9-byte struct on a 64-bit target places 8-bytes in one registers and 1-byte in a second register (assuming available registers). To handle this I switch from using cooked_read to cooked_read_part. Finally, when processing basic integer return value types these are extended to xlen sized types and then passed in registers. We currently don't handle this type expansion in riscv_return_value, but we do in riscv_push_dummy_call. The result is that small integer types (like char) result in a full xlen sized register being written into the output buffer, which results in buffer overflow. To address this issue we now create a value of the expanded type and use this values contents buffer to hold the return value before casting the value down to the smaller expected type. This patch resolves all of the valgrind issues I have found so far, and causes no regressions. Tested against RV32/64 with and without floating point support. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_struct): Don't adjust size before assigning locations. (riscv_return_value): Take more care not to read/write outside of argument buffer. Cast return value between the declared type and the abi type.
2018-11-27 14:41:44 +01:00
regcache->cooked_write_part (regnum, 0,
info.argloc[1].c_length,
writebuf);
}
break;
case riscv_arg_info::location::by_ref:
case riscv_arg_info::location::on_stack:
default:
error (_("invalid argument location"));
break;
}
}
}
break;
/* Return value by reference will have its address in A0. */
case riscv_arg_info::location::by_ref:
{
ULONGEST addr;
regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
&addr);
if (readbuf != nullptr)
read_memory (addr, readbuf, info.length);
if (writebuf != nullptr)
write_memory (addr, writebuf, info.length);
}
break;
case riscv_arg_info::location::on_stack:
default:
error (_("invalid argument location"));
break;
}
gdb/riscv: Prevent buffer overflow in riscv_return_value The existing code for reading and writing the return value can overflow the passed in buffers in a couple of situations. This commit aims to resolve these issues. The problems were detected using valgrind, here are two examples, first from gdb.base/structs.exp: (gdb) p/x fun9() ==31353== Invalid write of size 8 ==31353== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==31353== by 0x632EBB: memcpy (string_fortified.h:34) ==31353== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==31353== by 0x659D3F: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2593) ==31353== by 0x583641: get_call_return_value (infcall.c:448) ==31353== by 0x583641: call_thread_fsm_should_stop(thread_fsm*, thread_info*) (infcall.c:546) ==31353== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==31353== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==31353== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==31353== by 0x6CA34B: wait_sync_command_done() (top.c:503) ==31353== by 0x584653: run_inferior_call (infcall.c:621) ... And from gdb.base/call-sc.exp: (gdb) advance fun fun () at /gdb/gdb/testsuite/gdb.base/call-sc.c:41 41 return foo; (gdb) finish ==1968== Invalid write of size 8 ==1968== at 0x4C34153: memmove (vg_replace_strmem.c:1270) ==1968== by 0x632EBB: memcpy (string_fortified.h:34) ==1968== by 0x632EBB: readable_regcache::raw_read(int, unsigned char*) (regcache.c:538) ==1968== by 0x659D01: riscv_return_value(gdbarch*, value*, type*, regcache*, unsigned char*, unsigned char const*) (riscv-tdep.c:2576) ==1968== by 0x5891E4: get_return_value(value*, type*) (infcmd.c:1640) ==1968== by 0x5892C4: finish_command_fsm_should_stop(thread_fsm*, thread_info*) (infcmd.c:1808) ==1968== by 0x59BBEC: fetch_inferior_event(void*) (infrun.c:3883) ==1968== by 0x53890B: check_async_event_handlers (event-loop.c:1064) ==1968== by 0x53890B: gdb_do_one_event() [clone .part.4] (event-loop.c:326) ==1968== by 0x6CA34B: wait_sync_command_done() (top.c:503) ... There are a couple of problems with the existing code, that are all related. In riscv_call_arg_struct we incorrectly rounded up the size of a structure argument. This is unnecessary, and caused GDB to read too much data into the output buffer when extracting a struct return value. In fixing this it became clear that we were incorrectly assuming that any value being placed in a register (or read from a register) would always access the entire register. This is not true, for example a 9-byte struct on a 64-bit target places 8-bytes in one registers and 1-byte in a second register (assuming available registers). To handle this I switch from using cooked_read to cooked_read_part. Finally, when processing basic integer return value types these are extended to xlen sized types and then passed in registers. We currently don't handle this type expansion in riscv_return_value, but we do in riscv_push_dummy_call. The result is that small integer types (like char) result in a full xlen sized register being written into the output buffer, which results in buffer overflow. To address this issue we now create a value of the expanded type and use this values contents buffer to hold the return value before casting the value down to the smaller expected type. This patch resolves all of the valgrind issues I have found so far, and causes no regressions. Tested against RV32/64 with and without floating point support. gdb/ChangeLog: * riscv-tdep.c (riscv_call_arg_struct): Don't adjust size before assigning locations. (riscv_return_value): Take more care not to read/write outside of argument buffer. Cast return value between the declared type and the abi type.
2018-11-27 14:41:44 +01:00
/* This completes the cast from abi type back to the declared type
in the case that we are reading from the machine. See the
comment at the head of this block for more details. */
if (readbuf != nullptr)
{
struct value *arg_val = value_cast (arg_type, abi_val);
memcpy (old_readbuf, value_contents_raw (arg_val),
TYPE_LENGTH (arg_type));
}
}
switch (info.argloc[0].loc_type)
{
case riscv_arg_info::location::in_reg:
return RETURN_VALUE_REGISTER_CONVENTION;
case riscv_arg_info::location::by_ref:
return RETURN_VALUE_ABI_RETURNS_ADDRESS;
case riscv_arg_info::location::on_stack:
default:
error (_("invalid argument location"));
}
}
/* Implement the frame_align gdbarch method. */
static CORE_ADDR
riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
{
return align_down (addr, 16);
}
/* Generate, or return the cached frame cache for the RiscV frame
unwinder. */
static struct riscv_unwind_cache *
riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
{
CORE_ADDR pc, start_addr;
struct riscv_unwind_cache *cache;
struct gdbarch *gdbarch = get_frame_arch (this_frame);
int numregs, regno;
if ((*this_cache) != NULL)
return (struct riscv_unwind_cache *) *this_cache;
cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
cache->regs = trad_frame_alloc_saved_regs (this_frame);
(*this_cache) = cache;
/* Scan the prologue, filling in the cache. */
start_addr = get_frame_func (this_frame);
pc = get_frame_pc (this_frame);
riscv_scan_prologue (gdbarch, start_addr, pc, cache);
/* We can now calculate the frame base address. */
cache->frame_base
= (get_frame_register_signed (this_frame, cache->frame_base_reg)
+ cache->frame_base_offset);
if (riscv_debug_unwinder)
fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
core_addr_to_string (cache->frame_base),
gdbarch_register_name (gdbarch,
cache->frame_base_reg),
cache->frame_base_offset);
/* The prologue scanner sets the address of registers stored to the stack
as the offset of that register from the frame base. The prologue
scanner doesn't know the actual frame base value, and so is unable to
compute the exact address. We do now know the frame base value, so
update the address of registers stored to the stack. */
numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
for (regno = 0; regno < numregs; ++regno)
{
if (trad_frame_addr_p (cache->regs, regno))
cache->regs[regno].addr += cache->frame_base;
}
/* The previous $pc can be found wherever the $ra value can be found.
The previous $ra value is gone, this would have been stored be the
previous frame if required. */
cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
/* Build the frame id. */
cache->this_id = frame_id_build (cache->frame_base, start_addr);
/* The previous $sp value is the frame base value. */
trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
cache->frame_base);
return cache;
}
/* Implement the this_id callback for RiscV frame unwinder. */
static void
riscv_frame_this_id (struct frame_info *this_frame,
void **prologue_cache,
struct frame_id *this_id)
{
struct riscv_unwind_cache *cache;
Rewrite TRY/CATCH This rewrites gdb's TRY/CATCH to plain C++ try/catch. The patch was largely written by script, though one change (to a comment in common-exceptions.h) was reverted by hand. gdb/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * xml-support.c: Use C++ exception handling. * x86-linux-nat.c: Use C++ exception handling. * windows-nat.c: Use C++ exception handling. * varobj.c: Use C++ exception handling. * value.c: Use C++ exception handling. * valprint.c: Use C++ exception handling. * valops.c: Use C++ exception handling. * unittests/parse-connection-spec-selftests.c: Use C++ exception handling. * unittests/cli-utils-selftests.c: Use C++ exception handling. * typeprint.c: Use C++ exception handling. * tui/tui.c: Use C++ exception handling. * tracefile-tfile.c: Use C++ exception handling. * top.c: Use C++ exception handling. * thread.c: Use C++ exception handling. * target.c: Use C++ exception handling. * symmisc.c: Use C++ exception handling. * symfile-mem.c: Use C++ exception handling. * stack.c: Use C++ exception handling. * sparc64-linux-tdep.c: Use C++ exception handling. * solib.c: Use C++ exception handling. * solib-svr4.c: Use C++ exception handling. * solib-spu.c: Use C++ exception handling. * solib-frv.c: Use C++ exception handling. * solib-dsbt.c: Use C++ exception handling. * selftest-arch.c: Use C++ exception handling. * s390-tdep.c: Use C++ exception handling. * rust-lang.c: Use C++ exception handling. * rust-exp.y: Use C++ exception handling. * rs6000-tdep.c: Use C++ exception handling. * rs6000-aix-tdep.c: Use C++ exception handling. * riscv-tdep.c: Use C++ exception handling. * remote.c: Use C++ exception handling. * remote-fileio.c: Use C++ exception handling. * record-full.c: Use C++ exception handling. * record-btrace.c: Use C++ exception handling. * python/python.c: Use C++ exception handling. * python/py-value.c: Use C++ exception handling. * python/py-utils.c: Use C++ exception handling. * python/py-unwind.c: Use C++ exception handling. * python/py-type.c: Use C++ exception handling. * python/py-symbol.c: Use C++ exception handling. * python/py-record.c: Use C++ exception handling. * python/py-record-btrace.c: Use C++ exception handling. * python/py-progspace.c: Use C++ exception handling. * python/py-prettyprint.c: Use C++ exception handling. * python/py-param.c: Use C++ exception handling. * python/py-objfile.c: Use C++ exception handling. * python/py-linetable.c: Use C++ exception handling. * python/py-lazy-string.c: Use C++ exception handling. * python/py-infthread.c: Use C++ exception handling. * python/py-inferior.c: Use C++ exception handling. * python/py-gdb-readline.c: Use C++ exception handling. * python/py-framefilter.c: Use C++ exception handling. * python/py-frame.c: Use C++ exception handling. * python/py-finishbreakpoint.c: Use C++ exception handling. * python/py-cmd.c: Use C++ exception handling. * python/py-breakpoint.c: Use C++ exception handling. * python/py-arch.c: Use C++ exception handling. * printcmd.c: Use C++ exception handling. * ppc-linux-tdep.c: Use C++ exception handling. * parse.c: Use C++ exception handling. * p-valprint.c: Use C++ exception handling. * objc-lang.c: Use C++ exception handling. * mi/mi-main.c: Use C++ exception handling. * mi/mi-interp.c: Use C++ exception handling. * mi/mi-cmd-stack.c: Use C++ exception handling. * mi/mi-cmd-break.c: Use C++ exception handling. * main.c: Use C++ exception handling. * linux-thread-db.c: Use C++ exception handling. * linux-tdep.c: Use C++ exception handling. * linux-nat.c: Use C++ exception handling. * linux-fork.c: Use C++ exception handling. * linespec.c: Use C++ exception handling. * language.c: Use C++ exception handling. * jit.c: Use C++ exception handling. * infrun.c: Use C++ exception handling. * infcmd.c: Use C++ exception handling. * infcall.c: Use C++ exception handling. * inf-loop.c: Use C++ exception handling. * i386-tdep.c: Use C++ exception handling. * i386-linux-tdep.c: Use C++ exception handling. * guile/scm-value.c: Use C++ exception handling. * guile/scm-type.c: Use C++ exception handling. * guile/scm-symtab.c: Use C++ exception handling. * guile/scm-symbol.c: Use C++ exception handling. * guile/scm-pretty-print.c: Use C++ exception handling. * guile/scm-ports.c: Use C++ exception handling. * guile/scm-param.c: Use C++ exception handling. * guile/scm-math.c: Use C++ exception handling. * guile/scm-lazy-string.c: Use C++ exception handling. * guile/scm-frame.c: Use C++ exception handling. * guile/scm-disasm.c: Use C++ exception handling. * guile/scm-cmd.c: Use C++ exception handling. * guile/scm-breakpoint.c: Use C++ exception handling. * guile/scm-block.c: Use C++ exception handling. * guile/guile-internal.h: Use C++ exception handling. * gnu-v3-abi.c: Use C++ exception handling. * gdbtypes.c: Use C++ exception handling. * frame.c: Use C++ exception handling. * frame-unwind.c: Use C++ exception handling. * fbsd-tdep.c: Use C++ exception handling. * f-valprint.c: Use C++ exception handling. * exec.c: Use C++ exception handling. * event-top.c: Use C++ exception handling. * event-loop.c: Use C++ exception handling. * eval.c: Use C++ exception handling. * dwarf2read.c: Use C++ exception handling. * dwarf2loc.c: Use C++ exception handling. * dwarf2-frame.c: Use C++ exception handling. * dwarf2-frame-tailcall.c: Use C++ exception handling. * dwarf-index-write.c: Use C++ exception handling. * dwarf-index-cache.c: Use C++ exception handling. * dtrace-probe.c: Use C++ exception handling. * disasm-selftests.c: Use C++ exception handling. * darwin-nat.c: Use C++ exception handling. * cp-valprint.c: Use C++ exception handling. * cp-support.c: Use C++ exception handling. * cp-abi.c: Use C++ exception handling. * corelow.c: Use C++ exception handling. * completer.c: Use C++ exception handling. * compile/compile-object-run.c: Use C++ exception handling. * compile/compile-object-load.c: Use C++ exception handling. * compile/compile-cplus-symbols.c: Use C++ exception handling. * compile/compile-c-symbols.c: Use C++ exception handling. * common/selftest.c: Use C++ exception handling. * common/new-op.c: Use C++ exception handling. * cli/cli-script.c: Use C++ exception handling. * cli/cli-interp.c: Use C++ exception handling. * cli/cli-cmds.c: Use C++ exception handling. * c-varobj.c: Use C++ exception handling. * btrace.c: Use C++ exception handling. * breakpoint.c: Use C++ exception handling. * break-catch-throw.c: Use C++ exception handling. * arch-utils.c: Use C++ exception handling. * amd64-tdep.c: Use C++ exception handling. * ada-valprint.c: Use C++ exception handling. * ada-typeprint.c: Use C++ exception handling. * ada-lang.c: Use C++ exception handling. * aarch64-tdep.c: Use C++ exception handling. gdb/gdbserver/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * server.c: Use C++ exception handling. * linux-low.c: Use C++ exception handling. * gdbreplay.c: Use C++ exception handling.
2019-04-04 00:02:42 +02:00
try
gdb/riscv: Handle errors while setting the frame id When we connect to a remote target one of the first things GDB does is establish a frame id. If an error is thrown while building this frame id then GDB will disconnect from the target. This can mean that, if the user is attempting to connect to a target that doesn't yet have a program loaded, or the program the user is going to load onto the target doesn't match what is already loaded, or the target is just in some undefined state, then the very first request for a frame id can fail (for example, by trying to load from an invalid memory address), and GDB will disconnect. It is then impossible for the user to connect to the target and load a new program at all. An example of such a session might look like this: Reading symbols from ./gdb/testsuite/outputs/gdb.arch/riscv-reg-aliases/riscv-reg-aliases... (gdb) target remote :37191 Remote debugging using :37191 0x0000000000000100 in ?? () Cannot access memory at address 0x0 (gdb) load You can't do that when your target is `exec' (gdb) info frame /path/to/gdb/gdb/thread.c:93: internal-error: thread_info* inferior_thread(): Assertion `tp' failed. A problem internal to GDB has been detected, further debugging may prove unreliable. Quit this debugging session? (y or n) The solution is to handle errors in riscv_frame_this_id, and leave the this_id variable with its default value, which is the predefined 'outermost' frame. With this fix in place, connecting to the same target now looks like this: (gdb) target remote :37191 Remote debugging using :37191 0x0000000000000100 in ?? () (gdb) info frame Stack level 0, frame at 0x0: pc = 0x100; saved pc = <not saved> Outermost frame: outermost Arglist at unknown address. Locals at unknown address, Previous frame's sp in sp gdb/ChangeLog: * riscv-tdep.c (riscv_insn::decode): Update header comment. (riscv_frame_this_id): Catch errors thrown while building the frame cache, leave the frame id as the default, which is the outer frame id.
2018-10-29 16:14:03 +01:00
{
cache = riscv_frame_cache (this_frame, prologue_cache);
*this_id = cache->this_id;
}
Rename gdb exception types This renames the gdb exception types. The old types were only needed due to the macros in common-exception.h that are now gone. The intermediate layer of gdb_exception_RETURN_MASK_ALL did not seem needed, so this patch removes it entirely. gdb/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * common/common-exceptions.h (gdb_exception_RETURN_MASK_ALL): Remove. (gdb_exception_error): Rename from gdb_exception_RETURN_MASK_ERROR. (gdb_exception_quit): Rename from gdb_exception_RETURN_MASK_QUIT. (gdb_quit_bad_alloc): Update. * aarch64-tdep.c: Update. * ada-lang.c: Update. * ada-typeprint.c: Update. * ada-valprint.c: Update. * amd64-tdep.c: Update. * arch-utils.c: Update. * break-catch-throw.c: Update. * breakpoint.c: Update. * btrace.c: Update. * c-varobj.c: Update. * cli/cli-cmds.c: Update. * cli/cli-interp.c: Update. * cli/cli-script.c: Update. * common/common-exceptions.c: Update. * common/new-op.c: Update. * common/selftest.c: Update. * compile/compile-c-symbols.c: Update. * compile/compile-cplus-symbols.c: Update. * compile/compile-object-load.c: Update. * compile/compile-object-run.c: Update. * completer.c: Update. * corelow.c: Update. * cp-abi.c: Update. * cp-support.c: Update. * cp-valprint.c: Update. * darwin-nat.c: Update. * disasm-selftests.c: Update. * dtrace-probe.c: Update. * dwarf-index-cache.c: Update. * dwarf-index-write.c: Update. * dwarf2-frame-tailcall.c: Update. * dwarf2-frame.c: Update. * dwarf2loc.c: Update. * dwarf2read.c: Update. * eval.c: Update. * event-loop.c: Update. * event-top.c: Update. * exec.c: Update. * f-valprint.c: Update. * fbsd-tdep.c: Update. * frame-unwind.c: Update. * frame.c: Update. * gdbtypes.c: Update. * gnu-v3-abi.c: Update. * guile/guile-internal.h: Update. * guile/scm-block.c: Update. * guile/scm-breakpoint.c: Update. * guile/scm-cmd.c: Update. * guile/scm-disasm.c: Update. * guile/scm-frame.c: Update. * guile/scm-lazy-string.c: Update. * guile/scm-math.c: Update. * guile/scm-param.c: Update. * guile/scm-ports.c: Update. * guile/scm-pretty-print.c: Update. * guile/scm-symbol.c: Update. * guile/scm-symtab.c: Update. * guile/scm-type.c: Update. * guile/scm-value.c: Update. * i386-linux-tdep.c: Update. * i386-tdep.c: Update. * inf-loop.c: Update. * infcall.c: Update. * infcmd.c: Update. * infrun.c: Update. * jit.c: Update. * language.c: Update. * linespec.c: Update. * linux-fork.c: Update. * linux-nat.c: Update. * linux-tdep.c: Update. * linux-thread-db.c: Update. * main.c: Update. * mi/mi-cmd-break.c: Update. * mi/mi-cmd-stack.c: Update. * mi/mi-interp.c: Update. * mi/mi-main.c: Update. * objc-lang.c: Update. * p-valprint.c: Update. * parse.c: Update. * ppc-linux-tdep.c: Update. * printcmd.c: Update. * python/py-arch.c: Update. * python/py-breakpoint.c: Update. * python/py-cmd.c: Update. * python/py-finishbreakpoint.c: Update. * python/py-frame.c: Update. * python/py-framefilter.c: Update. * python/py-gdb-readline.c: Update. * python/py-inferior.c: Update. * python/py-infthread.c: Update. * python/py-lazy-string.c: Update. * python/py-linetable.c: Update. * python/py-objfile.c: Update. * python/py-param.c: Update. * python/py-prettyprint.c: Update. * python/py-progspace.c: Update. * python/py-record-btrace.c: Update. * python/py-record.c: Update. * python/py-symbol.c: Update. * python/py-type.c: Update. * python/py-unwind.c: Update. * python/py-utils.c: Update. * python/py-value.c: Update. * python/python.c: Update. * record-btrace.c: Update. * record-full.c: Update. * remote-fileio.c: Update. * remote.c: Update. * riscv-tdep.c: Update. * rs6000-aix-tdep.c: Update. * rs6000-tdep.c: Update. * rust-exp.y: Update. * rust-lang.c: Update. * s390-tdep.c: Update. * selftest-arch.c: Update. * solib-dsbt.c: Update. * solib-frv.c: Update. * solib-spu.c: Update. * solib-svr4.c: Update. * solib.c: Update. * sparc64-linux-tdep.c: Update. * stack.c: Update. * symfile-mem.c: Update. * symmisc.c: Update. * target.c: Update. * thread.c: Update. * top.c: Update. * tracefile-tfile.c: Update. * tui/tui.c: Update. * typeprint.c: Update. * unittests/cli-utils-selftests.c: Update. * unittests/parse-connection-spec-selftests.c: Update. * valops.c: Update. * valprint.c: Update. * value.c: Update. * varobj.c: Update. * windows-nat.c: Update. * x86-linux-nat.c: Update. * xml-support.c: Update. gdb/gdbserver/ChangeLog 2019-04-08 Tom Tromey <tom@tromey.com> * gdbreplay.c: Update. * linux-low.c: Update. * server.c: Update.
2019-04-03 23:59:07 +02:00
catch (const gdb_exception_error &ex)
gdb/riscv: Handle errors while setting the frame id When we connect to a remote target one of the first things GDB does is establish a frame id. If an error is thrown while building this frame id then GDB will disconnect from the target. This can mean that, if the user is attempting to connect to a target that doesn't yet have a program loaded, or the program the user is going to load onto the target doesn't match what is already loaded, or the target is just in some undefined state, then the very first request for a frame id can fail (for example, by trying to load from an invalid memory address), and GDB will disconnect. It is then impossible for the user to connect to the target and load a new program at all. An example of such a session might look like this: Reading symbols from ./gdb/testsuite/outputs/gdb.arch/riscv-reg-aliases/riscv-reg-aliases... (gdb) target remote :37191 Remote debugging using :37191 0x0000000000000100 in ?? () Cannot access memory at address 0x0 (gdb) load You can't do that when your target is `exec' (gdb) info frame /path/to/gdb/gdb/thread.c:93: internal-error: thread_info* inferior_thread(): Assertion `tp' failed. A problem internal to GDB has been detected, further debugging may prove unreliable. Quit this debugging session? (y or n) The solution is to handle errors in riscv_frame_this_id, and leave the this_id variable with its default value, which is the predefined 'outermost' frame. With this fix in place, connecting to the same target now looks like this: (gdb) target remote :37191 Remote debugging using :37191 0x0000000000000100 in ?? () (gdb) info frame Stack level 0, frame at 0x0: pc = 0x100; saved pc = <not saved> Outermost frame: outermost Arglist at unknown address. Locals at unknown address, Previous frame's sp in sp gdb/ChangeLog: * riscv-tdep.c (riscv_insn::decode): Update header comment. (riscv_frame_this_id): Catch errors thrown while building the frame cache, leave the frame id as the default, which is the outer frame id.
2018-10-29 16:14:03 +01:00
{
/* Ignore errors, this leaves the frame id as the predefined outer
frame id which terminates the backtrace at this point. */
}
}
/* Implement the prev_register callback for RiscV frame unwinder. */
static struct value *
riscv_frame_prev_register (struct frame_info *this_frame,
void **prologue_cache,
int regnum)
{
struct riscv_unwind_cache *cache;
cache = riscv_frame_cache (this_frame, prologue_cache);
return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
}
/* Structure defining the RiscV normal frame unwind functions. Since we
are the fallback unwinder (DWARF unwinder is used first), we use the
default frame sniffer, which always accepts the frame. */
static const struct frame_unwind riscv_frame_unwind =
{
/*.type =*/ NORMAL_FRAME,
/*.stop_reason =*/ default_frame_unwind_stop_reason,
/*.this_id =*/ riscv_frame_this_id,
/*.prev_register =*/ riscv_frame_prev_register,
/*.unwind_data =*/ NULL,
/*.sniffer =*/ default_frame_sniffer,
/*.dealloc_cache =*/ NULL,
/*.prev_arch =*/ NULL,
};
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
/* Extract a set of required target features out of INFO, specifically the
bfd being executed is examined to see what target features it requires.
IF there is no current bfd, or the bfd doesn't indicate any useful
features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
static struct riscv_gdbarch_features
riscv_features_from_gdbarch_info (const struct gdbarch_info info)
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
struct riscv_gdbarch_features features;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Now try to improve on the defaults by looking at the binary we are
going to execute. We assume the user knows what they are doing and
that the target will match the binary. Remember, this code path is
only used at all if the target hasn't given us a description, so this
is really a last ditched effort to do something sane before giving
up. */
if (info.abfd != NULL
&& bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
{
unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
int e_flags = elf_elfheader (info.abfd)->e_flags;
if (eclass == ELFCLASS32)
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
features.xlen = 4;
else if (eclass == ELFCLASS64)
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
features.xlen = 8;
else
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
internal_error (__FILE__, __LINE__,
_("unknown ELF header class %d"), eclass);
if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
features.flen = 8;
else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
features.flen = 4;
}
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
return features;
}
/* Find a suitable default target description. Use the contents of INFO,
specifically the bfd object being executed, to guide the selection of a
suitable default target description. */
static const struct target_desc *
riscv_find_default_target_description (const struct gdbarch_info info)
{
/* Extract desired feature set from INFO. */
struct riscv_gdbarch_features features
= riscv_features_from_gdbarch_info (info);
/* If the XLEN field is still 0 then we got nothing useful from INFO. In
this case we fall back to a minimal useful target, 8-byte x-registers,
with no floating point. */
if (features.xlen == 0)
features.xlen = 8;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Now build a target description based on the feature set. */
return riscv_create_target_description (features);
}
/* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
is updated with the register numbers for each register as listed in
REG_SET. If any register marked as required in REG_SET is not found in
FEATURE then this function returns false, otherwise, it returns true. */
static bool
riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
const struct tdesc_feature *feature,
const struct riscv_register_feature *reg_set)
{
for (const auto &reg : reg_set->registers)
{
bool found = false;
for (const char *name : reg.names)
{
found =
tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
if (found)
break;
}
if (!found && reg.required_p)
return false;
}
return true;
}
/* Add all the expected register sets into GDBARCH. */
static void
riscv_add_reggroups (struct gdbarch *gdbarch)
{
/* Add predefined register groups. */
reggroup_add (gdbarch, all_reggroup);
reggroup_add (gdbarch, save_reggroup);
reggroup_add (gdbarch, restore_reggroup);
reggroup_add (gdbarch, system_reggroup);
reggroup_add (gdbarch, vector_reggroup);
reggroup_add (gdbarch, general_reggroup);
reggroup_add (gdbarch, float_reggroup);
/* Add RISC-V specific register groups. */
reggroup_add (gdbarch, csr_reggroup);
}
/* Create register aliases for all the alternative names that exist for
registers in REG_SET. */
static void
riscv_setup_register_aliases (struct gdbarch *gdbarch,
const struct riscv_register_feature *reg_set)
{
for (auto &reg : reg_set->registers)
{
/* The first item in the names list is the preferred name for the
register, this is what RISCV_REGISTER_NAME returns, and so we
don't need to create an alias with that name here. */
for (int i = 1; i < reg.names.size (); ++i)
user_reg_add (gdbarch, reg.names[i], value_of_riscv_user_reg,
&reg.regnum);
}
}
/* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
static int
riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
if (reg < RISCV_DWARF_REGNUM_X31)
return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
else if (reg < RISCV_DWARF_REGNUM_F31)
return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
return -1;
}
/* Implement the gcc_target_options method. We have to select the arch and abi
from the feature info. We have enough feature info to select the abi, but
not enough info for the arch given all of the possible architecture
extensions. So choose reasonable defaults for now. */
static std::string
riscv_gcc_target_options (struct gdbarch *gdbarch)
{
int isa_xlen = riscv_isa_xlen (gdbarch);
int isa_flen = riscv_isa_flen (gdbarch);
int abi_xlen = riscv_abi_xlen (gdbarch);
int abi_flen = riscv_abi_flen (gdbarch);
std::string target_options;
target_options = "-march=rv";
if (isa_xlen == 8)
target_options += "64";
else
target_options += "32";
if (isa_flen == 8)
target_options += "gc";
else if (isa_flen == 4)
target_options += "imafc";
else
target_options += "imac";
target_options += " -mabi=";
if (abi_xlen == 8)
target_options += "lp64";
else
target_options += "ilp32";
if (abi_flen == 8)
target_options += "d";
else if (abi_flen == 4)
target_options += "f";
/* The gdb loader doesn't handle link-time relaxation relocations. */
target_options += " -mno-relax";
return target_options;
}
/* Implement the gnu_triplet_regexp method. A single compiler supports both
32-bit and 64-bit code, and may be named riscv32 or riscv64 or (not
recommended) riscv. */
static const char *
riscv_gnu_triplet_regexp (struct gdbarch *gdbarch)
{
return "riscv(32|64)?";
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Initialize the current architecture based on INFO. If possible,
re-use an architecture from ARCHES, which is a list of
architectures already created during this debugging session.
Called e.g. at program startup, when reading a core file, and when
reading a binary file. */
static struct gdbarch *
riscv_gdbarch_init (struct gdbarch_info info,
struct gdbarch_list *arches)
{
struct gdbarch *gdbarch;
struct gdbarch_tdep *tdep;
struct riscv_gdbarch_features features;
const struct target_desc *tdesc = info.target_desc;
/* Ensure we always have a target description. */
if (!tdesc_has_registers (tdesc))
tdesc = riscv_find_default_target_description (info);
gdb_assert (tdesc);
if (riscv_debug_gdbarch)
fprintf_unfiltered (gdb_stdlog, "Have got a target description\n");
const struct tdesc_feature *feature_cpu
= tdesc_find_feature (tdesc, riscv_xreg_feature.name);
const struct tdesc_feature *feature_fpu
= tdesc_find_feature (tdesc, riscv_freg_feature.name);
const struct tdesc_feature *feature_virtual
= tdesc_find_feature (tdesc, riscv_virtual_feature.name);
const struct tdesc_feature *feature_csr
= tdesc_find_feature (tdesc, riscv_csr_feature.name);
if (feature_cpu == NULL)
return NULL;
struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
bool valid_p = riscv_check_tdesc_feature (tdesc_data,
feature_cpu,
&riscv_xreg_feature);
if (valid_p)
{
/* Check that all of the core cpu registers have the same bitsize. */
int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
for (auto &tdesc_reg : feature_cpu->registers)
valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
if (riscv_debug_gdbarch)
fprintf_filtered
(gdb_stdlog,
"From target-description, xlen = %d\n", xlen_bitsize);
features.xlen = (xlen_bitsize / 8);
}
if (feature_fpu != NULL)
{
valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
&riscv_freg_feature);
/* Search for the first floating point register (by any alias), to
determine the bitsize. */
int bitsize = -1;
const auto &fp0 = riscv_freg_feature.registers[0];
for (const char *name : fp0.names)
{
if (tdesc_unnumbered_register (feature_fpu, name))
{
bitsize = tdesc_register_bitsize (feature_fpu, name);
break;
}
}
gdb_assert (bitsize != -1);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
features.flen = (bitsize / 8);
if (riscv_debug_gdbarch)
fprintf_filtered
(gdb_stdlog,
"From target-description, flen = %d\n", bitsize);
}
else
{
features.flen = 0;
if (riscv_debug_gdbarch)
fprintf_filtered
(gdb_stdlog,
"No FPU in target-description, assume soft-float ABI\n");
}
if (feature_virtual)
riscv_check_tdesc_feature (tdesc_data, feature_virtual,
&riscv_virtual_feature);
if (feature_csr)
riscv_check_tdesc_feature (tdesc_data, feature_csr,
&riscv_csr_feature);
if (!valid_p)
{
if (riscv_debug_gdbarch)
fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n");
tdesc_data_cleanup (tdesc_data);
return NULL;
}
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
/* Have a look at what the supplied (if any) bfd object requires of the
target, then check that this matches with what the target is
providing. */
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
struct riscv_gdbarch_features abi_features
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
= riscv_features_from_gdbarch_info (info);
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
/* In theory a binary compiled for RV32 could run on an RV64 target,
however, this has not been tested in GDB yet, so for now we require
that the requested xlen match the targets xlen. */
if (abi_features.xlen != 0 && abi_features.xlen != features.xlen)
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
error (_("bfd requires xlen %d, but target has xlen %d"),
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
abi_features.xlen, features.xlen);
/* We do support running binaries compiled for 32-bit float on targets
with 64-bit float, so we only complain if the binary requires more
than the target has available. */
if (abi_features.flen > features.flen)
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
error (_("bfd requires flen %d, but target has flen %d"),
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
abi_features.flen, features.flen);
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
/* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
features from the INFO object. In this case we assume that the xlen
abi matches the hardware. */
if (abi_features.xlen == 0)
abi_features.xlen = features.xlen;
gdb/riscv: Improve logic for when h/w float abi should be used Currently, if the target announces that it has floating point registers in its target description then GDB assumes that the hardware float ABI should be used. However, there's nothing stopping a user compiling a program for the soft-float abi, and then trying to run this on a target with hardware floating point registers. This commit adjusts the logic that decides if GDB should use the hardware float abi. The primary decision now is based on what the ELF currently being executed says in its headers. If the file was compiled for h/w float abi, then GDB uses h/w float abi, otherwise s/w float is used. If the current BFD is not an ELF then we don't currently have a mechanism for figuring out if the file was compiled for float or not. In this case we disable the h/w float abi. This shouldn't be a problem as, right now, the RISC-V linker can only produce ELFs. If there is NO current BFD (can this happen?) then we will enable h/w float abi if the target has floating point hardware, otherwise, s/w float abi is used. This commit also adds some sanity checking that the features requested in the BFD (xlen and flen) match the target description. For testing I ran the testsuite on a target that returns a target description containing both integer and floating point registers, but used a compiler that didn't have floating point support. Before this commit I would see failures on may tests that made inferior calls using floating point arguments, after this commit, all of these issues are resolved. One example from the testsuite is gdb.base/infcall-nested-structs.exp. gdb/ChangeLog: * riscv-tdep.c (riscv_features_from_gdbarch_info): New function. (riscv_find_default_target_description): Use new function to extract feature from gdbarch_info. (riscv_gdbarch_init): Add error checks for xlen and flen between target description and bfd headers. Be smarter about when we think the hardware floating point abi should be used.
2018-12-03 18:48:49 +01:00
/* Find a candidate among the list of pre-declared architectures. */
for (arches = gdbarch_list_lookup_by_info (arches, &info);
arches != NULL;
arches = gdbarch_list_lookup_by_info (arches->next, &info))
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
{
/* Check that the feature set of the ARCHES matches the feature set
we are looking for. If it doesn't then we can't reuse this
gdbarch. */
struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch);
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
if (other_tdep->isa_features != features
|| other_tdep->abi_features != abi_features)
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
continue;
break;
}
if (arches != NULL)
{
tdesc_data_cleanup (tdesc_data);
return arches->gdbarch;
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
}
/* None found, so create a new architecture from the information provided. */
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
tdep = new (struct gdbarch_tdep);
gdbarch = gdbarch_alloc (&info, tdep);
gdb/riscv: Split ISA and ABI features The goal of this commit is to allow RV64 binaries compiled for the 'F' extension to run on a target that supports both the 'F' and 'D' extensions. The 'D' extension depends on the 'F' extension and chapter 9 of the RISC-V ISA manual implies that running a program compiled for 'F' on a 'D' target should be fine. To support this the gdbarch now holds two feature sets, one represents the features that are present on the target, and one represents the features requested in the ELF flags. The existing error checks are relaxed slightly to allow binaries compiled for 32-bit 'F' extension to run on targets with the 64-bit 'D' extension. A new set of functions called riscv_abi_{xlen,flen} are added to compliment the existing riscv_isa_{xlen,flen}, and some callers to the isa functions now call the abi functions when that is appropriate. In riscv_call_arg_struct two asserts are removed, these asserts no longer make sense. The asserts were both like this: gdb_assert (TYPE_LENGTH (ainfo->type) <= (cinfo->flen + cinfo->xlen)); And were made in two cases, when passing structures like these: struct { integer field1; float field2; }; or, struct { float field1; integer field2; }; When running on an RV64 target which only has 32-bit float then the integer field could be 64-bits, while if the float field is 32-bits the overall size of the structure can be 128-bits (with 32-bits of padding). In this case the assertion would fail, however, the code isn't incorrect, so its safe to just remove the assertion. This was tested by running on an RV64IMFDC target using a compiler configured for RV64IMFC, and comparing the results with those obtained when using a compiler configured for RV64IMFDC. The only regressions I see (now) are in gdb.base/store.exp and are related too different code generation choices GCC makes between the two targets. Finally, this commit does not make any attempt to support running binaries compiled for RV32 on an RV64 target, though nothing in here should prevent that being supported in the future. gdb/ChangeLog: * arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>: Delete. <operator==>: Update with for removed field. <hash>: Likewise. * riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to... <isa_features>: ...this. <abi_features>: New field. (riscv_isa_flen): Update comment. (riscv_abi_xlen): New declaration. (riscv_abi_flen): New declaration. * riscv-tdep.c (riscv_isa_xlen): Update to get answer from isa_features. (riscv_abi_xlen): New function. (riscv_isa_flen): Update to get answer from isa_features. (riscv_abi_flen): New function. (riscv_has_fp_abi): Update to get answer from abi_features. (riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa xlen and flen. (riscv_call_info) <xlen, flen>: Update comment. (riscv_call_arg_struct): Remove invalid assertions (riscv_features_from_gdbarch_info): Update now hw_float_abi field is removed. (riscv_gdbarch_init): Gather isa features and abi features separately, ensure both match on the gdbarch when reusing an old gdbarch. Relax an error check to allow 32-bit abi float to run on a target with 64-bit float hardware.
2018-12-13 18:59:12 +01:00
tdep->isa_features = features;
tdep->abi_features = abi_features;
/* Target data types. */
set_gdbarch_short_bit (gdbarch, 16);
set_gdbarch_int_bit (gdbarch, 32);
set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
set_gdbarch_long_long_bit (gdbarch, 64);
set_gdbarch_float_bit (gdbarch, 32);
set_gdbarch_double_bit (gdbarch, 64);
set_gdbarch_long_double_bit (gdbarch, 128);
set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
set_gdbarch_char_signed (gdbarch, 0);
set_gdbarch_type_align (gdbarch, riscv_type_align);
/* Information about the target architecture. */
set_gdbarch_return_value (gdbarch, riscv_return_value);
set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
/* Functions to analyze frames. */
set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
set_gdbarch_frame_align (gdbarch, riscv_frame_align);
/* Functions handling dummy frames. */
set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
/* Frame unwinders. Use DWARF debug info if available, otherwise use our own
unwinder. */
dwarf2_append_unwinders (gdbarch);
frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Register architecture. */
riscv_add_reggroups (gdbarch);
/* Internal <-> external register number maps. */
set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* We reserve all possible register numbers for the known registers.
This means the target description mechanism will add any target
specific registers after this number. This helps make debugging GDB
just a little easier. */
set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
/* We don't have to provide the count of 0 here (its the default) but
include this line to make it explicit that, right now, we don't have
any pseudo registers on RISC-V. */
set_gdbarch_num_pseudo_regs (gdbarch, 0);
/* Some specific register numbers GDB likes to know about. */
set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
/* Finalise the target description registers. */
tdesc_use_registers (gdbarch, tdesc, tdesc_data);
/* Override the register type callback setup by the target description
mechanism. This allows us to provide special type for floating point
registers. */
set_gdbarch_register_type (gdbarch, riscv_register_type);
/* Override the register name callback setup by the target description
mechanism. This allows us to force our preferred names for the
registers, no matter what the target description called them. */
set_gdbarch_register_name (gdbarch, riscv_register_name);
/* Override the register group callback setup by the target description
mechanism. This allows us to force registers into the groups we
want, ignoring what the target tells us. */
set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
/* Create register aliases for alternative register names. */
riscv_setup_register_aliases (gdbarch, &riscv_xreg_feature);
if (riscv_has_fp_regs (gdbarch))
riscv_setup_register_aliases (gdbarch, &riscv_freg_feature);
riscv_setup_register_aliases (gdbarch, &riscv_csr_feature);
/* Compile command hooks. */
set_gdbarch_gcc_target_options (gdbarch, riscv_gcc_target_options);
set_gdbarch_gnu_triplet_regexp (gdbarch, riscv_gnu_triplet_regexp);
/* Hook in OS ABI-specific overrides, if they have been registered. */
gdbarch_init_osabi (info, gdbarch);
register_riscv_ravenscar_ops (gdbarch);
return gdbarch;
}
2018-08-08 19:53:12 +02:00
/* This decodes the current instruction and determines the address of the
next instruction. */
static CORE_ADDR
riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
{
struct gdbarch *gdbarch = regcache->arch ();
struct riscv_insn insn;
CORE_ADDR next_pc;
insn.decode (gdbarch, pc);
next_pc = pc + insn.length ();
if (insn.opcode () == riscv_insn::JAL)
next_pc = pc + insn.imm_signed ();
else if (insn.opcode () == riscv_insn::JALR)
{
LONGEST source;
regcache->cooked_read (insn.rs1 (), &source);
next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
}
else if (insn.opcode () == riscv_insn::BEQ)
{
LONGEST src1, src2;
regcache->cooked_read (insn.rs1 (), &src1);
regcache->cooked_read (insn.rs2 (), &src2);
if (src1 == src2)
next_pc = pc + insn.imm_signed ();
}
else if (insn.opcode () == riscv_insn::BNE)
{
LONGEST src1, src2;
regcache->cooked_read (insn.rs1 (), &src1);
regcache->cooked_read (insn.rs2 (), &src2);
if (src1 != src2)
next_pc = pc + insn.imm_signed ();
}
else if (insn.opcode () == riscv_insn::BLT)
{
LONGEST src1, src2;
regcache->cooked_read (insn.rs1 (), &src1);
regcache->cooked_read (insn.rs2 (), &src2);
if (src1 < src2)
next_pc = pc + insn.imm_signed ();
}
else if (insn.opcode () == riscv_insn::BGE)
{
LONGEST src1, src2;
regcache->cooked_read (insn.rs1 (), &src1);
regcache->cooked_read (insn.rs2 (), &src2);
if (src1 >= src2)
next_pc = pc + insn.imm_signed ();
}
else if (insn.opcode () == riscv_insn::BLTU)
{
ULONGEST src1, src2;
regcache->cooked_read (insn.rs1 (), &src1);
regcache->cooked_read (insn.rs2 (), &src2);
if (src1 < src2)
next_pc = pc + insn.imm_signed ();
}
else if (insn.opcode () == riscv_insn::BGEU)
{
ULONGEST src1, src2;
regcache->cooked_read (insn.rs1 (), &src1);
regcache->cooked_read (insn.rs2 (), &src2);
if (src1 >= src2)
next_pc = pc + insn.imm_signed ();
}
return next_pc;
}
/* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
for the end of the sequence and put the breakpoint there. */
static bool
riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
CORE_ADDR *next_pc)
{
struct gdbarch *gdbarch = regcache->arch ();
struct riscv_insn insn;
CORE_ADDR cur_step_pc = pc;
CORE_ADDR last_addr = 0;
/* First instruction has to be a load reserved. */
insn.decode (gdbarch, cur_step_pc);
if (insn.opcode () != riscv_insn::LR)
return false;
cur_step_pc = cur_step_pc + insn.length ();
/* Next instruction should be branch to exit. */
insn.decode (gdbarch, cur_step_pc);
if (insn.opcode () != riscv_insn::BNE)
return false;
last_addr = cur_step_pc + insn.imm_signed ();
cur_step_pc = cur_step_pc + insn.length ();
/* Next instruction should be store conditional. */
insn.decode (gdbarch, cur_step_pc);
if (insn.opcode () != riscv_insn::SC)
return false;
cur_step_pc = cur_step_pc + insn.length ();
/* Next instruction should be branch to start. */
insn.decode (gdbarch, cur_step_pc);
if (insn.opcode () != riscv_insn::BNE)
return false;
if (pc != (cur_step_pc + insn.imm_signed ()))
return false;
cur_step_pc = cur_step_pc + insn.length ();
/* We should now be at the end of the sequence. */
if (cur_step_pc != last_addr)
return false;
*next_pc = cur_step_pc;
return true;
}
/* This is called just before we want to resume the inferior, if we want to
single-step it but there is no hardware or kernel single-step support. We
find the target of the coming instruction and breakpoint it. */
std::vector<CORE_ADDR>
riscv_software_single_step (struct regcache *regcache)
{
CORE_ADDR pc, next_pc;
pc = regcache_read_pc (regcache);
if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
return {next_pc};
next_pc = riscv_next_pc (regcache, pc);
return {next_pc};
}
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
/* Create RISC-V specific reggroups. */
static void
riscv_init_reggroups ()
{
csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
}
gdb: add back declarations for _initialize functions I'd like to enable the -Wmissing-declarations warning. However, it warns for every _initialize function, for example: CXX dcache.o /home/smarchi/src/binutils-gdb/gdb/dcache.c: In function ‘void _initialize_dcache()’: /home/smarchi/src/binutils-gdb/gdb/dcache.c:688:1: error: no previous declaration for ‘void _initialize_dcache()’ [-Werror=missing-declarations] _initialize_dcache (void) ^~~~~~~~~~~~~~~~~~ The only practical way forward I found is to add back the declarations, which were removed by this commit: commit 481695ed5f6e0a8a9c9c50bfac1cdd2b3151e6c9 Author: John Baldwin <jhb@FreeBSD.org> Date: Sat Sep 9 11:02:37 2017 -0700 Remove unnecessary function prototypes. I don't think it's a big problem to have the declarations for these functions, but if anybody has a better solution for this, I'll be happy to use it. gdb/ChangeLog: * aarch64-fbsd-nat.c (_initialize_aarch64_fbsd_nat): Add declaration. * aarch64-fbsd-tdep.c (_initialize_aarch64_fbsd_tdep): Add declaration. * aarch64-linux-nat.c (_initialize_aarch64_linux_nat): Add declaration. * aarch64-linux-tdep.c (_initialize_aarch64_linux_tdep): Add declaration. * aarch64-newlib-tdep.c (_initialize_aarch64_newlib_tdep): Add declaration. * aarch64-tdep.c (_initialize_aarch64_tdep): Add declaration. * ada-exp.y (_initialize_ada_exp): Add declaration. * ada-lang.c (_initialize_ada_language): Add declaration. * ada-tasks.c (_initialize_tasks): Add declaration. * agent.c (_initialize_agent): Add declaration. * aix-thread.c (_initialize_aix_thread): Add declaration. * alpha-bsd-nat.c (_initialize_alphabsd_nat): Add declaration. * alpha-linux-nat.c (_initialize_alpha_linux_nat): Add declaration. * alpha-linux-tdep.c (_initialize_alpha_linux_tdep): Add declaration. * alpha-nbsd-tdep.c (_initialize_alphanbsd_tdep): Add declaration. * alpha-obsd-tdep.c (_initialize_alphaobsd_tdep): Add declaration. * alpha-tdep.c (_initialize_alpha_tdep): Add declaration. * amd64-darwin-tdep.c (_initialize_amd64_darwin_tdep): Add declaration. * amd64-dicos-tdep.c (_initialize_amd64_dicos_tdep): Add declaration. * amd64-fbsd-nat.c (_initialize_amd64fbsd_nat): Add declaration. * amd64-fbsd-tdep.c (_initialize_amd64fbsd_tdep): Add declaration. * amd64-linux-nat.c (_initialize_amd64_linux_nat): Add declaration. * amd64-linux-tdep.c (_initialize_amd64_linux_tdep): Add declaration. * amd64-nbsd-nat.c (_initialize_amd64nbsd_nat): Add declaration. * amd64-nbsd-tdep.c (_initialize_amd64nbsd_tdep): Add declaration. * amd64-obsd-nat.c (_initialize_amd64obsd_nat): Add declaration. * amd64-obsd-tdep.c (_initialize_amd64obsd_tdep): Add declaration. * amd64-sol2-tdep.c (_initialize_amd64_sol2_tdep): Add declaration. * amd64-tdep.c (_initialize_amd64_tdep): Add declaration. * amd64-windows-nat.c (_initialize_amd64_windows_nat): Add declaration. * amd64-windows-tdep.c (_initialize_amd64_windows_tdep): Add declaration. * annotate.c (_initialize_annotate): Add declaration. * arc-newlib-tdep.c (_initialize_arc_newlib_tdep): Add declaration. * arc-tdep.c (_initialize_arc_tdep): Add declaration. * arch-utils.c (_initialize_gdbarch_utils): Add declaration. * arm-fbsd-nat.c (_initialize_arm_fbsd_nat): Add declaration. * arm-fbsd-tdep.c (_initialize_arm_fbsd_tdep): Add declaration. * arm-linux-nat.c (_initialize_arm_linux_nat): Add declaration. * arm-linux-tdep.c (_initialize_arm_linux_tdep): Add declaration. * arm-nbsd-nat.c (_initialize_arm_netbsd_nat): Add declaration. * arm-nbsd-tdep.c (_initialize_arm_netbsd_tdep): Add declaration. * arm-obsd-tdep.c (_initialize_armobsd_tdep): Add declaration. * arm-pikeos-tdep.c (_initialize_arm_pikeos_tdep): Add declaration. * arm-symbian-tdep.c (_initialize_arm_symbian_tdep): Add declaration. * arm-tdep.c (_initialize_arm_tdep): Add declaration. * arm-wince-tdep.c (_initialize_arm_wince_tdep): Add declaration. * auto-load.c (_initialize_auto_load): Add declaration. * auxv.c (_initialize_auxv): Add declaration. * avr-tdep.c (_initialize_avr_tdep): Add declaration. * ax-gdb.c (_initialize_ax_gdb): Add declaration. * bfin-linux-tdep.c (_initialize_bfin_linux_tdep): Add declaration. * bfin-tdep.c (_initialize_bfin_tdep): Add declaration. * break-catch-sig.c (_initialize_break_catch_sig): Add declaration. * break-catch-syscall.c (_initialize_break_catch_syscall): Add declaration. * break-catch-throw.c (_initialize_break_catch_throw): Add declaration. * breakpoint.c (_initialize_breakpoint): Add declaration. * bsd-uthread.c (_initialize_bsd_uthread): Add declaration. * btrace.c (_initialize_btrace): Add declaration. * charset.c (_initialize_charset): Add declaration. * cli/cli-cmds.c (_initialize_cli_cmds): Add declaration. * cli/cli-dump.c (_initialize_cli_dump): Add declaration. * cli/cli-interp.c (_initialize_cli_interp): Add declaration. * cli/cli-logging.c (_initialize_cli_logging): Add declaration. * cli/cli-script.c (_initialize_cli_script): Add declaration. * cli/cli-style.c (_initialize_cli_style): Add declaration. * coff-pe-read.c (_initialize_coff_pe_read): Add declaration. * coffread.c (_initialize_coffread): Add declaration. * compile/compile-cplus-types.c (_initialize_compile_cplus_types): Add declaration. * compile/compile.c (_initialize_compile): Add declaration. * complaints.c (_initialize_complaints): Add declaration. * completer.c (_initialize_completer): Add declaration. * copying.c (_initialize_copying): Add declaration. * corefile.c (_initialize_core): Add declaration. * corelow.c (_initialize_corelow): Add declaration. * cp-abi.c (_initialize_cp_abi): Add declaration. * cp-namespace.c (_initialize_cp_namespace): Add declaration. * cp-support.c (_initialize_cp_support): Add declaration. * cp-valprint.c (_initialize_cp_valprint): Add declaration. * cris-linux-tdep.c (_initialize_cris_linux_tdep): Add declaration. * cris-tdep.c (_initialize_cris_tdep): Add declaration. * csky-linux-tdep.c (_initialize_csky_linux_tdep): Add declaration. * csky-tdep.c (_initialize_csky_tdep): Add declaration. * ctfread.c (_initialize_ctfread): Add declaration. * d-lang.c (_initialize_d_language): Add declaration. * darwin-nat-info.c (_initialize_darwin_info_commands): Add declaration. * darwin-nat.c (_initialize_darwin_nat): Add declaration. * dbxread.c (_initialize_dbxread): Add declaration. * dcache.c (_initialize_dcache): Add declaration. * disasm-selftests.c (_initialize_disasm_selftests): Add declaration. * disasm.c (_initialize_disasm): Add declaration. * dtrace-probe.c (_initialize_dtrace_probe): Add declaration. * dummy-frame.c (_initialize_dummy_frame): Add declaration. * dwarf-index-cache.c (_initialize_index_cache): Add declaration. * dwarf-index-write.c (_initialize_dwarf_index_write): Add declaration. * dwarf2-frame-tailcall.c (_initialize_tailcall_frame): Add declaration. * dwarf2-frame.c (_initialize_dwarf2_frame): Add declaration. * dwarf2expr.c (_initialize_dwarf2expr): Add declaration. * dwarf2loc.c (_initialize_dwarf2loc): Add declaration. * dwarf2read.c (_initialize_dwarf2_read): Add declaration. * elfread.c (_initialize_elfread): Add declaration. * exec.c (_initialize_exec): Add declaration. * extension.c (_initialize_extension): Add declaration. * f-lang.c (_initialize_f_language): Add declaration. * f-valprint.c (_initialize_f_valprint): Add declaration. * fbsd-nat.c (_initialize_fbsd_nat): Add declaration. * fbsd-tdep.c (_initialize_fbsd_tdep): Add declaration. * filesystem.c (_initialize_filesystem): Add declaration. * findcmd.c (_initialize_mem_search): Add declaration. * findvar.c (_initialize_findvar): Add declaration. * fork-child.c (_initialize_fork_child): Add declaration. * frame-base.c (_initialize_frame_base): Add declaration. * frame-unwind.c (_initialize_frame_unwind): Add declaration. * frame.c (_initialize_frame): Add declaration. * frv-linux-tdep.c (_initialize_frv_linux_tdep): Add declaration. * frv-tdep.c (_initialize_frv_tdep): Add declaration. * ft32-tdep.c (_initialize_ft32_tdep): Add declaration. * gcore.c (_initialize_gcore): Add declaration. * gdb-demangle.c (_initialize_gdb_demangle): Add declaration. * gdb_bfd.c (_initialize_gdb_bfd): Add declaration. * gdbarch-selftests.c (_initialize_gdbarch_selftests): Add declaration. * gdbarch.c (_initialize_gdbarch): Add declaration. * gdbtypes.c (_initialize_gdbtypes): Add declaration. * gnu-nat.c (_initialize_gnu_nat): Add declaration. * gnu-v2-abi.c (_initialize_gnu_v2_abi): Add declaration. * gnu-v3-abi.c (_initialize_gnu_v3_abi): Add declaration. * go-lang.c (_initialize_go_language): Add declaration. * go32-nat.c (_initialize_go32_nat): Add declaration. * guile/guile.c (_initialize_guile): Add declaration. * h8300-tdep.c (_initialize_h8300_tdep): Add declaration. * hppa-linux-nat.c (_initialize_hppa_linux_nat): Add declaration. * hppa-linux-tdep.c (_initialize_hppa_linux_tdep): Add declaration. * hppa-nbsd-nat.c (_initialize_hppanbsd_nat): Add declaration. * hppa-nbsd-tdep.c (_initialize_hppanbsd_tdep): Add declaration. * hppa-obsd-nat.c (_initialize_hppaobsd_nat): Add declaration. * hppa-obsd-tdep.c (_initialize_hppabsd_tdep): Add declaration. * hppa-tdep.c (_initialize_hppa_tdep): Add declaration. * i386-bsd-nat.c (_initialize_i386bsd_nat): Add declaration. * i386-cygwin-tdep.c (_initialize_i386_cygwin_tdep): Add declaration. * i386-darwin-nat.c (_initialize_i386_darwin_nat): Add declaration. * i386-darwin-tdep.c (_initialize_i386_darwin_tdep): Add declaration. * i386-dicos-tdep.c (_initialize_i386_dicos_tdep): Add declaration. * i386-fbsd-nat.c (_initialize_i386fbsd_nat): Add declaration. * i386-fbsd-tdep.c (_initialize_i386fbsd_tdep): Add declaration. * i386-gnu-nat.c (_initialize_i386gnu_nat): Add declaration. * i386-gnu-tdep.c (_initialize_i386gnu_tdep): Add declaration. * i386-go32-tdep.c (_initialize_i386_go32_tdep): Add declaration. * i386-linux-nat.c (_initialize_i386_linux_nat): Add declaration. * i386-linux-tdep.c (_initialize_i386_linux_tdep): Add declaration. * i386-nbsd-nat.c (_initialize_i386nbsd_nat): Add declaration. * i386-nbsd-tdep.c (_initialize_i386nbsd_tdep): Add declaration. * i386-nto-tdep.c (_initialize_i386nto_tdep): Add declaration. * i386-obsd-nat.c (_initialize_i386obsd_nat): Add declaration. * i386-obsd-tdep.c (_initialize_i386obsd_tdep): Add declaration. * i386-sol2-nat.c (_initialize_amd64_sol2_nat): Add declaration. * i386-sol2-tdep.c (_initialize_i386_sol2_tdep): Add declaration. * i386-tdep.c (_initialize_i386_tdep): Add declaration. * i386-windows-nat.c (_initialize_i386_windows_nat): Add declaration. * ia64-libunwind-tdep.c (_initialize_libunwind_frame): Add declaration. * ia64-linux-nat.c (_initialize_ia64_linux_nat): Add declaration. * ia64-linux-tdep.c (_initialize_ia64_linux_tdep): Add declaration. * ia64-tdep.c (_initialize_ia64_tdep): Add declaration. * ia64-vms-tdep.c (_initialize_ia64_vms_tdep): Add declaration. * infcall.c (_initialize_infcall): Add declaration. * infcmd.c (_initialize_infcmd): Add declaration. * inflow.c (_initialize_inflow): Add declaration. * infrun.c (_initialize_infrun): Add declaration. * interps.c (_initialize_interpreter): Add declaration. * iq2000-tdep.c (_initialize_iq2000_tdep): Add declaration. * jit.c (_initialize_jit): Add declaration. * language.c (_initialize_language): Add declaration. * linux-fork.c (_initialize_linux_fork): Add declaration. * linux-nat.c (_initialize_linux_nat): Add declaration. * linux-tdep.c (_initialize_linux_tdep): Add declaration. * linux-thread-db.c (_initialize_thread_db): Add declaration. * lm32-tdep.c (_initialize_lm32_tdep): Add declaration. * m2-lang.c (_initialize_m2_language): Add declaration. * m32c-tdep.c (_initialize_m32c_tdep): Add declaration. * m32r-linux-nat.c (_initialize_m32r_linux_nat): Add declaration. * m32r-linux-tdep.c (_initialize_m32r_linux_tdep): Add declaration. * m32r-tdep.c (_initialize_m32r_tdep): Add declaration. * m68hc11-tdep.c (_initialize_m68hc11_tdep): Add declaration. * m68k-bsd-nat.c (_initialize_m68kbsd_nat): Add declaration. * m68k-bsd-tdep.c (_initialize_m68kbsd_tdep): Add declaration. * m68k-linux-nat.c (_initialize_m68k_linux_nat): Add declaration. * m68k-linux-tdep.c (_initialize_m68k_linux_tdep): Add declaration. * m68k-tdep.c (_initialize_m68k_tdep): Add declaration. * machoread.c (_initialize_machoread): Add declaration. * macrocmd.c (_initialize_macrocmd): Add declaration. * macroscope.c (_initialize_macroscope): Add declaration. * maint-test-options.c (_initialize_maint_test_options): Add declaration. * maint-test-settings.c (_initialize_maint_test_settings): Add declaration. * maint.c (_initialize_maint_cmds): Add declaration. * mdebugread.c (_initialize_mdebugread): Add declaration. * memattr.c (_initialize_mem): Add declaration. * mep-tdep.c (_initialize_mep_tdep): Add declaration. * mi/mi-cmd-env.c (_initialize_mi_cmd_env): Add declaration. * mi/mi-cmds.c (_initialize_mi_cmds): Add declaration. * mi/mi-interp.c (_initialize_mi_interp): Add declaration. * mi/mi-main.c (_initialize_mi_main): Add declaration. * microblaze-linux-tdep.c (_initialize_microblaze_linux_tdep): Add declaration. * microblaze-tdep.c (_initialize_microblaze_tdep): Add declaration. * mips-fbsd-nat.c (_initialize_mips_fbsd_nat): Add declaration. * mips-fbsd-tdep.c (_initialize_mips_fbsd_tdep): Add declaration. * mips-linux-nat.c (_initialize_mips_linux_nat): Add declaration. * mips-linux-tdep.c (_initialize_mips_linux_tdep): Add declaration. * mips-nbsd-nat.c (_initialize_mipsnbsd_nat): Add declaration. * mips-nbsd-tdep.c (_initialize_mipsnbsd_tdep): Add declaration. * mips-sde-tdep.c (_initialize_mips_sde_tdep): Add declaration. * mips-tdep.c (_initialize_mips_tdep): Add declaration. * mips64-obsd-nat.c (_initialize_mips64obsd_nat): Add declaration. * mips64-obsd-tdep.c (_initialize_mips64obsd_tdep): Add declaration. * mipsread.c (_initialize_mipsread): Add declaration. * mn10300-linux-tdep.c (_initialize_mn10300_linux_tdep): Add declaration. * mn10300-tdep.c (_initialize_mn10300_tdep): Add declaration. * moxie-tdep.c (_initialize_moxie_tdep): Add declaration. * msp430-tdep.c (_initialize_msp430_tdep): Add declaration. * nds32-tdep.c (_initialize_nds32_tdep): Add declaration. * nios2-linux-tdep.c (_initialize_nios2_linux_tdep): Add declaration. * nios2-tdep.c (_initialize_nios2_tdep): Add declaration. * nto-procfs.c (_initialize_procfs): Add declaration. * objc-lang.c (_initialize_objc_language): Add declaration. * observable.c (_initialize_observer): Add declaration. * opencl-lang.c (_initialize_opencl_language): Add declaration. * or1k-linux-tdep.c (_initialize_or1k_linux_tdep): Add declaration. * or1k-tdep.c (_initialize_or1k_tdep): Add declaration. * osabi.c (_initialize_gdb_osabi): Add declaration. * osdata.c (_initialize_osdata): Add declaration. * p-valprint.c (_initialize_pascal_valprint): Add declaration. * parse.c (_initialize_parse): Add declaration. * ppc-fbsd-nat.c (_initialize_ppcfbsd_nat): Add declaration. * ppc-fbsd-tdep.c (_initialize_ppcfbsd_tdep): Add declaration. * ppc-linux-nat.c (_initialize_ppc_linux_nat): Add declaration. * ppc-linux-tdep.c (_initialize_ppc_linux_tdep): Add declaration. * ppc-nbsd-nat.c (_initialize_ppcnbsd_nat): Add declaration. * ppc-nbsd-tdep.c (_initialize_ppcnbsd_tdep): Add declaration. * ppc-obsd-nat.c (_initialize_ppcobsd_nat): Add declaration. * ppc-obsd-tdep.c (_initialize_ppcobsd_tdep): Add declaration. * printcmd.c (_initialize_printcmd): Add declaration. * probe.c (_initialize_probe): Add declaration. * proc-api.c (_initialize_proc_api): Add declaration. * proc-events.c (_initialize_proc_events): Add declaration. * proc-service.c (_initialize_proc_service): Add declaration. * procfs.c (_initialize_procfs): Add declaration. * producer.c (_initialize_producer): Add declaration. * psymtab.c (_initialize_psymtab): Add declaration. * python/python.c (_initialize_python): Add declaration. * ravenscar-thread.c (_initialize_ravenscar): Add declaration. * record-btrace.c (_initialize_record_btrace): Add declaration. * record-full.c (_initialize_record_full): Add declaration. * record.c (_initialize_record): Add declaration. * regcache-dump.c (_initialize_regcache_dump): Add declaration. * regcache.c (_initialize_regcache): Add declaration. * reggroups.c (_initialize_reggroup): Add declaration. * remote-notif.c (_initialize_notif): Add declaration. * remote-sim.c (_initialize_remote_sim): Add declaration. * remote.c (_initialize_remote): Add declaration. * reverse.c (_initialize_reverse): Add declaration. * riscv-fbsd-nat.c (_initialize_riscv_fbsd_nat): Add declaration. * riscv-fbsd-tdep.c (_initialize_riscv_fbsd_tdep): Add declaration. * riscv-linux-nat.c (_initialize_riscv_linux_nat): Add declaration. * riscv-linux-tdep.c (_initialize_riscv_linux_tdep): Add declaration. * riscv-tdep.c (_initialize_riscv_tdep): Add declaration. * rl78-tdep.c (_initialize_rl78_tdep): Add declaration. * rs6000-aix-tdep.c (_initialize_rs6000_aix_tdep): Add declaration. * rs6000-lynx178-tdep.c (_initialize_rs6000_lynx178_tdep): Add declaration. * rs6000-nat.c (_initialize_rs6000_nat): Add declaration. * rs6000-tdep.c (_initialize_rs6000_tdep): Add declaration. * run-on-main-thread.c (_initialize_run_on_main_thread): Add declaration. * rust-exp.y (_initialize_rust_exp): Add declaration. * rx-tdep.c (_initialize_rx_tdep): Add declaration. * s12z-tdep.c (_initialize_s12z_tdep): Add declaration. * s390-linux-nat.c (_initialize_s390_nat): Add declaration. * s390-linux-tdep.c (_initialize_s390_linux_tdep): Add declaration. * s390-tdep.c (_initialize_s390_tdep): Add declaration. * score-tdep.c (_initialize_score_tdep): Add declaration. * ser-go32.c (_initialize_ser_dos): Add declaration. * ser-mingw.c (_initialize_ser_windows): Add declaration. * ser-pipe.c (_initialize_ser_pipe): Add declaration. * ser-tcp.c (_initialize_ser_tcp): Add declaration. * ser-uds.c (_initialize_ser_socket): Add declaration. * ser-unix.c (_initialize_ser_hardwire): Add declaration. * serial.c (_initialize_serial): Add declaration. * sh-linux-tdep.c (_initialize_sh_linux_tdep): Add declaration. * sh-nbsd-nat.c (_initialize_shnbsd_nat): Add declaration. * sh-nbsd-tdep.c (_initialize_shnbsd_tdep): Add declaration. * sh-tdep.c (_initialize_sh_tdep): Add declaration. * skip.c (_initialize_step_skip): Add declaration. * sol-thread.c (_initialize_sol_thread): Add declaration. * solib-aix.c (_initialize_solib_aix): Add declaration. * solib-darwin.c (_initialize_darwin_solib): Add declaration. * solib-dsbt.c (_initialize_dsbt_solib): Add declaration. * solib-frv.c (_initialize_frv_solib): Add declaration. * solib-svr4.c (_initialize_svr4_solib): Add declaration. * solib-target.c (_initialize_solib_target): Add declaration. * solib.c (_initialize_solib): Add declaration. * source-cache.c (_initialize_source_cache): Add declaration. * source.c (_initialize_source): Add declaration. * sparc-linux-nat.c (_initialize_sparc_linux_nat): Add declaration. * sparc-linux-tdep.c (_initialize_sparc_linux_tdep): Add declaration. * sparc-nat.c (_initialize_sparc_nat): Add declaration. * sparc-nbsd-nat.c (_initialize_sparcnbsd_nat): Add declaration. * sparc-nbsd-tdep.c (_initialize_sparcnbsd_tdep): Add declaration. * sparc-obsd-tdep.c (_initialize_sparc32obsd_tdep): Add declaration. * sparc-sol2-tdep.c (_initialize_sparc_sol2_tdep): Add declaration. * sparc-tdep.c (_initialize_sparc_tdep): Add declaration. * sparc64-fbsd-nat.c (_initialize_sparc64fbsd_nat): Add declaration. * sparc64-fbsd-tdep.c (_initialize_sparc64fbsd_tdep): Add declaration. * sparc64-linux-nat.c (_initialize_sparc64_linux_nat): Add declaration. * sparc64-linux-tdep.c (_initialize_sparc64_linux_tdep): Add declaration. * sparc64-nat.c (_initialize_sparc64_nat): Add declaration. * sparc64-nbsd-nat.c (_initialize_sparc64nbsd_nat): Add declaration. * sparc64-nbsd-tdep.c (_initialize_sparc64nbsd_tdep): Add declaration. * sparc64-obsd-nat.c (_initialize_sparc64obsd_nat): Add declaration. * sparc64-obsd-tdep.c (_initialize_sparc64obsd_tdep): Add declaration. * sparc64-sol2-tdep.c (_initialize_sparc64_sol2_tdep): Add declaration. * sparc64-tdep.c (_initialize_sparc64_adi_tdep): Add declaration. * stabsread.c (_initialize_stabsread): Add declaration. * stack.c (_initialize_stack): Add declaration. * stap-probe.c (_initialize_stap_probe): Add declaration. * std-regs.c (_initialize_frame_reg): Add declaration. * symfile-debug.c (_initialize_symfile_debug): Add declaration. * symfile-mem.c (_initialize_symfile_mem): Add declaration. * symfile.c (_initialize_symfile): Add declaration. * symmisc.c (_initialize_symmisc): Add declaration. * symtab.c (_initialize_symtab): Add declaration. * target.c (_initialize_target): Add declaration. * target-connection.c (_initialize_target_connection): Add declaration. * target-dcache.c (_initialize_target_dcache): Add declaration. * target-descriptions.c (_initialize_target_descriptions): Add declaration. * thread.c (_initialize_thread): Add declaration. * tic6x-linux-tdep.c (_initialize_tic6x_linux_tdep): Add declaration. * tic6x-tdep.c (_initialize_tic6x_tdep): Add declaration. * tilegx-linux-nat.c (_initialize_tile_linux_nat): Add declaration. * tilegx-linux-tdep.c (_initialize_tilegx_linux_tdep): Add declaration. * tilegx-tdep.c (_initialize_tilegx_tdep): Add declaration. * tracectf.c (_initialize_ctf): Add declaration. * tracefile-tfile.c (_initialize_tracefile_tfile): Add declaration. * tracefile.c (_initialize_tracefile): Add declaration. * tracepoint.c (_initialize_tracepoint): Add declaration. * tui/tui-hooks.c (_initialize_tui_hooks): Add declaration. * tui/tui-interp.c (_initialize_tui_interp): Add declaration. * tui/tui-layout.c (_initialize_tui_layout): Add declaration. * tui/tui-regs.c (_initialize_tui_regs): Add declaration. * tui/tui-stack.c (_initialize_tui_stack): Add declaration. * tui/tui-win.c (_initialize_tui_win): Add declaration. * tui/tui.c (_initialize_tui): Add declaration. * typeprint.c (_initialize_typeprint): Add declaration. * ui-style.c (_initialize_ui_style): Add declaration. * unittests/array-view-selftests.c (_initialize_array_view_selftests): Add declaration. * unittests/child-path-selftests.c (_initialize_child_path_selftests): Add declaration. * unittests/cli-utils-selftests.c (_initialize_cli_utils_selftests): Add declaration. * unittests/common-utils-selftests.c (_initialize_common_utils_selftests): Add declaration. * unittests/copy_bitwise-selftests.c (_initialize_copy_bitwise_utils_selftests): Add declaration. * unittests/environ-selftests.c (_initialize_environ_selftests): Add declaration. * unittests/filtered_iterator-selftests.c (_initialize_filtered_iterator_selftests): Add declaration. * unittests/format_pieces-selftests.c (_initialize_format_pieces_selftests): Add declaration. * unittests/function-view-selftests.c (_initialize_function_view_selftests): Add declaration. * unittests/help-doc-selftests.c (_initialize_help_doc_selftests): Add declaration. * unittests/lookup_name_info-selftests.c (_initialize_lookup_name_info_selftests): Add declaration. * unittests/main-thread-selftests.c (_initialize_main_thread_selftests): Add declaration. * unittests/memory-map-selftests.c (_initialize_memory_map_selftests): Add declaration. * unittests/memrange-selftests.c (_initialize_memrange_selftests): Add declaration. * unittests/mkdir-recursive-selftests.c (_initialize_mkdir_recursive_selftests): Add declaration. * unittests/observable-selftests.c (_initialize_observer_selftest): Add declaration. * unittests/offset-type-selftests.c (_initialize_offset_type_selftests): Add declaration. * unittests/optional-selftests.c (_initialize_optional_selftests): Add declaration. * unittests/parse-connection-spec-selftests.c (_initialize_parse_connection_spec_selftests): Add declaration. * unittests/rsp-low-selftests.c (_initialize_rsp_low_selftests): Add declaration. * unittests/scoped_fd-selftests.c (_initialize_scoped_fd_selftests): Add declaration. * unittests/scoped_mmap-selftests.c (_initialize_scoped_mmap_selftests): Add declaration. * unittests/scoped_restore-selftests.c (_initialize_scoped_restore_selftests): Add declaration. * unittests/string_view-selftests.c (_initialize_string_view_selftests): Add declaration. * unittests/style-selftests.c (_initialize_style_selftest): Add declaration. * unittests/tracepoint-selftests.c (_initialize_tracepoint_selftests): Add declaration. * unittests/tui-selftests.c (_initialize_tui_selftest): Add declaration. * unittests/unpack-selftests.c (_initialize_unpack_selftests): Add declaration. * unittests/utils-selftests.c (_initialize_utils_selftests): Add declaration. * unittests/vec-utils-selftests.c (_initialize_vec_utils_selftests): Add declaration. * unittests/xml-utils-selftests.c (_initialize_xml_utils): Add declaration. * user-regs.c (_initialize_user_regs): Add declaration. * utils.c (_initialize_utils): Add declaration. * v850-tdep.c (_initialize_v850_tdep): Add declaration. * valops.c (_initialize_valops): Add declaration. * valprint.c (_initialize_valprint): Add declaration. * value.c (_initialize_values): Add declaration. * varobj.c (_initialize_varobj): Add declaration. * vax-bsd-nat.c (_initialize_vaxbsd_nat): Add declaration. * vax-nbsd-tdep.c (_initialize_vaxnbsd_tdep): Add declaration. * vax-tdep.c (_initialize_vax_tdep): Add declaration. * windows-nat.c (_initialize_windows_nat): Add declaration. (_initialize_check_for_gdb_ini): Add declaration. (_initialize_loadable): Add declaration. * windows-tdep.c (_initialize_windows_tdep): Add declaration. * x86-bsd-nat.c (_initialize_x86_bsd_nat): Add declaration. * x86-linux-nat.c (_initialize_x86_linux_nat): Add declaration. * xcoffread.c (_initialize_xcoffread): Add declaration. * xml-support.c (_initialize_xml_support): Add declaration. * xstormy16-tdep.c (_initialize_xstormy16_tdep): Add declaration. * xtensa-linux-nat.c (_initialize_xtensa_linux_nat): Add declaration. * xtensa-linux-tdep.c (_initialize_xtensa_linux_tdep): Add declaration. * xtensa-tdep.c (_initialize_xtensa_tdep): Add declaration. Change-Id: I13eec7e0ed2b3c427377a7bdb055cf46da64def9
2020-01-13 20:01:38 +01:00
void _initialize_riscv_tdep ();
void
gdb: add back declarations for _initialize functions I'd like to enable the -Wmissing-declarations warning. However, it warns for every _initialize function, for example: CXX dcache.o /home/smarchi/src/binutils-gdb/gdb/dcache.c: In function ‘void _initialize_dcache()’: /home/smarchi/src/binutils-gdb/gdb/dcache.c:688:1: error: no previous declaration for ‘void _initialize_dcache()’ [-Werror=missing-declarations] _initialize_dcache (void) ^~~~~~~~~~~~~~~~~~ The only practical way forward I found is to add back the declarations, which were removed by this commit: commit 481695ed5f6e0a8a9c9c50bfac1cdd2b3151e6c9 Author: John Baldwin <jhb@FreeBSD.org> Date: Sat Sep 9 11:02:37 2017 -0700 Remove unnecessary function prototypes. I don't think it's a big problem to have the declarations for these functions, but if anybody has a better solution for this, I'll be happy to use it. gdb/ChangeLog: * aarch64-fbsd-nat.c (_initialize_aarch64_fbsd_nat): Add declaration. * aarch64-fbsd-tdep.c (_initialize_aarch64_fbsd_tdep): Add declaration. * aarch64-linux-nat.c (_initialize_aarch64_linux_nat): Add declaration. * aarch64-linux-tdep.c (_initialize_aarch64_linux_tdep): Add declaration. * aarch64-newlib-tdep.c (_initialize_aarch64_newlib_tdep): Add declaration. * aarch64-tdep.c (_initialize_aarch64_tdep): Add declaration. * ada-exp.y (_initialize_ada_exp): Add declaration. * ada-lang.c (_initialize_ada_language): Add declaration. * ada-tasks.c (_initialize_tasks): Add declaration. * agent.c (_initialize_agent): Add declaration. * aix-thread.c (_initialize_aix_thread): Add declaration. * alpha-bsd-nat.c (_initialize_alphabsd_nat): Add declaration. * alpha-linux-nat.c (_initialize_alpha_linux_nat): Add declaration. * alpha-linux-tdep.c (_initialize_alpha_linux_tdep): Add declaration. * alpha-nbsd-tdep.c (_initialize_alphanbsd_tdep): Add declaration. * alpha-obsd-tdep.c (_initialize_alphaobsd_tdep): Add declaration. * alpha-tdep.c (_initialize_alpha_tdep): Add declaration. * amd64-darwin-tdep.c (_initialize_amd64_darwin_tdep): Add declaration. * amd64-dicos-tdep.c (_initialize_amd64_dicos_tdep): Add declaration. * amd64-fbsd-nat.c (_initialize_amd64fbsd_nat): Add declaration. * amd64-fbsd-tdep.c (_initialize_amd64fbsd_tdep): Add declaration. * amd64-linux-nat.c (_initialize_amd64_linux_nat): Add declaration. * amd64-linux-tdep.c (_initialize_amd64_linux_tdep): Add declaration. * amd64-nbsd-nat.c (_initialize_amd64nbsd_nat): Add declaration. * amd64-nbsd-tdep.c (_initialize_amd64nbsd_tdep): Add declaration. * amd64-obsd-nat.c (_initialize_amd64obsd_nat): Add declaration. * amd64-obsd-tdep.c (_initialize_amd64obsd_tdep): Add declaration. * amd64-sol2-tdep.c (_initialize_amd64_sol2_tdep): Add declaration. * amd64-tdep.c (_initialize_amd64_tdep): Add declaration. * amd64-windows-nat.c (_initialize_amd64_windows_nat): Add declaration. * amd64-windows-tdep.c (_initialize_amd64_windows_tdep): Add declaration. * annotate.c (_initialize_annotate): Add declaration. * arc-newlib-tdep.c (_initialize_arc_newlib_tdep): Add declaration. * arc-tdep.c (_initialize_arc_tdep): Add declaration. * arch-utils.c (_initialize_gdbarch_utils): Add declaration. * arm-fbsd-nat.c (_initialize_arm_fbsd_nat): Add declaration. * arm-fbsd-tdep.c (_initialize_arm_fbsd_tdep): Add declaration. * arm-linux-nat.c (_initialize_arm_linux_nat): Add declaration. * arm-linux-tdep.c (_initialize_arm_linux_tdep): Add declaration. * arm-nbsd-nat.c (_initialize_arm_netbsd_nat): Add declaration. * arm-nbsd-tdep.c (_initialize_arm_netbsd_tdep): Add declaration. * arm-obsd-tdep.c (_initialize_armobsd_tdep): Add declaration. * arm-pikeos-tdep.c (_initialize_arm_pikeos_tdep): Add declaration. * arm-symbian-tdep.c (_initialize_arm_symbian_tdep): Add declaration. * arm-tdep.c (_initialize_arm_tdep): Add declaration. * arm-wince-tdep.c (_initialize_arm_wince_tdep): Add declaration. * auto-load.c (_initialize_auto_load): Add declaration. * auxv.c (_initialize_auxv): Add declaration. * avr-tdep.c (_initialize_avr_tdep): Add declaration. * ax-gdb.c (_initialize_ax_gdb): Add declaration. * bfin-linux-tdep.c (_initialize_bfin_linux_tdep): Add declaration. * bfin-tdep.c (_initialize_bfin_tdep): Add declaration. * break-catch-sig.c (_initialize_break_catch_sig): Add declaration. * break-catch-syscall.c (_initialize_break_catch_syscall): Add declaration. * break-catch-throw.c (_initialize_break_catch_throw): Add declaration. * breakpoint.c (_initialize_breakpoint): Add declaration. * bsd-uthread.c (_initialize_bsd_uthread): Add declaration. * btrace.c (_initialize_btrace): Add declaration. * charset.c (_initialize_charset): Add declaration. * cli/cli-cmds.c (_initialize_cli_cmds): Add declaration. * cli/cli-dump.c (_initialize_cli_dump): Add declaration. * cli/cli-interp.c (_initialize_cli_interp): Add declaration. * cli/cli-logging.c (_initialize_cli_logging): Add declaration. * cli/cli-script.c (_initialize_cli_script): Add declaration. * cli/cli-style.c (_initialize_cli_style): Add declaration. * coff-pe-read.c (_initialize_coff_pe_read): Add declaration. * coffread.c (_initialize_coffread): Add declaration. * compile/compile-cplus-types.c (_initialize_compile_cplus_types): Add declaration. * compile/compile.c (_initialize_compile): Add declaration. * complaints.c (_initialize_complaints): Add declaration. * completer.c (_initialize_completer): Add declaration. * copying.c (_initialize_copying): Add declaration. * corefile.c (_initialize_core): Add declaration. * corelow.c (_initialize_corelow): Add declaration. * cp-abi.c (_initialize_cp_abi): Add declaration. * cp-namespace.c (_initialize_cp_namespace): Add declaration. * cp-support.c (_initialize_cp_support): Add declaration. * cp-valprint.c (_initialize_cp_valprint): Add declaration. * cris-linux-tdep.c (_initialize_cris_linux_tdep): Add declaration. * cris-tdep.c (_initialize_cris_tdep): Add declaration. * csky-linux-tdep.c (_initialize_csky_linux_tdep): Add declaration. * csky-tdep.c (_initialize_csky_tdep): Add declaration. * ctfread.c (_initialize_ctfread): Add declaration. * d-lang.c (_initialize_d_language): Add declaration. * darwin-nat-info.c (_initialize_darwin_info_commands): Add declaration. * darwin-nat.c (_initialize_darwin_nat): Add declaration. * dbxread.c (_initialize_dbxread): Add declaration. * dcache.c (_initialize_dcache): Add declaration. * disasm-selftests.c (_initialize_disasm_selftests): Add declaration. * disasm.c (_initialize_disasm): Add declaration. * dtrace-probe.c (_initialize_dtrace_probe): Add declaration. * dummy-frame.c (_initialize_dummy_frame): Add declaration. * dwarf-index-cache.c (_initialize_index_cache): Add declaration. * dwarf-index-write.c (_initialize_dwarf_index_write): Add declaration. * dwarf2-frame-tailcall.c (_initialize_tailcall_frame): Add declaration. * dwarf2-frame.c (_initialize_dwarf2_frame): Add declaration. * dwarf2expr.c (_initialize_dwarf2expr): Add declaration. * dwarf2loc.c (_initialize_dwarf2loc): Add declaration. * dwarf2read.c (_initialize_dwarf2_read): Add declaration. * elfread.c (_initialize_elfread): Add declaration. * exec.c (_initialize_exec): Add declaration. * extension.c (_initialize_extension): Add declaration. * f-lang.c (_initialize_f_language): Add declaration. * f-valprint.c (_initialize_f_valprint): Add declaration. * fbsd-nat.c (_initialize_fbsd_nat): Add declaration. * fbsd-tdep.c (_initialize_fbsd_tdep): Add declaration. * filesystem.c (_initialize_filesystem): Add declaration. * findcmd.c (_initialize_mem_search): Add declaration. * findvar.c (_initialize_findvar): Add declaration. * fork-child.c (_initialize_fork_child): Add declaration. * frame-base.c (_initialize_frame_base): Add declaration. * frame-unwind.c (_initialize_frame_unwind): Add declaration. * frame.c (_initialize_frame): Add declaration. * frv-linux-tdep.c (_initialize_frv_linux_tdep): Add declaration. * frv-tdep.c (_initialize_frv_tdep): Add declaration. * ft32-tdep.c (_initialize_ft32_tdep): Add declaration. * gcore.c (_initialize_gcore): Add declaration. * gdb-demangle.c (_initialize_gdb_demangle): Add declaration. * gdb_bfd.c (_initialize_gdb_bfd): Add declaration. * gdbarch-selftests.c (_initialize_gdbarch_selftests): Add declaration. * gdbarch.c (_initialize_gdbarch): Add declaration. * gdbtypes.c (_initialize_gdbtypes): Add declaration. * gnu-nat.c (_initialize_gnu_nat): Add declaration. * gnu-v2-abi.c (_initialize_gnu_v2_abi): Add declaration. * gnu-v3-abi.c (_initialize_gnu_v3_abi): Add declaration. * go-lang.c (_initialize_go_language): Add declaration. * go32-nat.c (_initialize_go32_nat): Add declaration. * guile/guile.c (_initialize_guile): Add declaration. * h8300-tdep.c (_initialize_h8300_tdep): Add declaration. * hppa-linux-nat.c (_initialize_hppa_linux_nat): Add declaration. * hppa-linux-tdep.c (_initialize_hppa_linux_tdep): Add declaration. * hppa-nbsd-nat.c (_initialize_hppanbsd_nat): Add declaration. * hppa-nbsd-tdep.c (_initialize_hppanbsd_tdep): Add declaration. * hppa-obsd-nat.c (_initialize_hppaobsd_nat): Add declaration. * hppa-obsd-tdep.c (_initialize_hppabsd_tdep): Add declaration. * hppa-tdep.c (_initialize_hppa_tdep): Add declaration. * i386-bsd-nat.c (_initialize_i386bsd_nat): Add declaration. * i386-cygwin-tdep.c (_initialize_i386_cygwin_tdep): Add declaration. * i386-darwin-nat.c (_initialize_i386_darwin_nat): Add declaration. * i386-darwin-tdep.c (_initialize_i386_darwin_tdep): Add declaration. * i386-dicos-tdep.c (_initialize_i386_dicos_tdep): Add declaration. * i386-fbsd-nat.c (_initialize_i386fbsd_nat): Add declaration. * i386-fbsd-tdep.c (_initialize_i386fbsd_tdep): Add declaration. * i386-gnu-nat.c (_initialize_i386gnu_nat): Add declaration. * i386-gnu-tdep.c (_initialize_i386gnu_tdep): Add declaration. * i386-go32-tdep.c (_initialize_i386_go32_tdep): Add declaration. * i386-linux-nat.c (_initialize_i386_linux_nat): Add declaration. * i386-linux-tdep.c (_initialize_i386_linux_tdep): Add declaration. * i386-nbsd-nat.c (_initialize_i386nbsd_nat): Add declaration. * i386-nbsd-tdep.c (_initialize_i386nbsd_tdep): Add declaration. * i386-nto-tdep.c (_initialize_i386nto_tdep): Add declaration. * i386-obsd-nat.c (_initialize_i386obsd_nat): Add declaration. * i386-obsd-tdep.c (_initialize_i386obsd_tdep): Add declaration. * i386-sol2-nat.c (_initialize_amd64_sol2_nat): Add declaration. * i386-sol2-tdep.c (_initialize_i386_sol2_tdep): Add declaration. * i386-tdep.c (_initialize_i386_tdep): Add declaration. * i386-windows-nat.c (_initialize_i386_windows_nat): Add declaration. * ia64-libunwind-tdep.c (_initialize_libunwind_frame): Add declaration. * ia64-linux-nat.c (_initialize_ia64_linux_nat): Add declaration. * ia64-linux-tdep.c (_initialize_ia64_linux_tdep): Add declaration. * ia64-tdep.c (_initialize_ia64_tdep): Add declaration. * ia64-vms-tdep.c (_initialize_ia64_vms_tdep): Add declaration. * infcall.c (_initialize_infcall): Add declaration. * infcmd.c (_initialize_infcmd): Add declaration. * inflow.c (_initialize_inflow): Add declaration. * infrun.c (_initialize_infrun): Add declaration. * interps.c (_initialize_interpreter): Add declaration. * iq2000-tdep.c (_initialize_iq2000_tdep): Add declaration. * jit.c (_initialize_jit): Add declaration. * language.c (_initialize_language): Add declaration. * linux-fork.c (_initialize_linux_fork): Add declaration. * linux-nat.c (_initialize_linux_nat): Add declaration. * linux-tdep.c (_initialize_linux_tdep): Add declaration. * linux-thread-db.c (_initialize_thread_db): Add declaration. * lm32-tdep.c (_initialize_lm32_tdep): Add declaration. * m2-lang.c (_initialize_m2_language): Add declaration. * m32c-tdep.c (_initialize_m32c_tdep): Add declaration. * m32r-linux-nat.c (_initialize_m32r_linux_nat): Add declaration. * m32r-linux-tdep.c (_initialize_m32r_linux_tdep): Add declaration. * m32r-tdep.c (_initialize_m32r_tdep): Add declaration. * m68hc11-tdep.c (_initialize_m68hc11_tdep): Add declaration. * m68k-bsd-nat.c (_initialize_m68kbsd_nat): Add declaration. * m68k-bsd-tdep.c (_initialize_m68kbsd_tdep): Add declaration. * m68k-linux-nat.c (_initialize_m68k_linux_nat): Add declaration. * m68k-linux-tdep.c (_initialize_m68k_linux_tdep): Add declaration. * m68k-tdep.c (_initialize_m68k_tdep): Add declaration. * machoread.c (_initialize_machoread): Add declaration. * macrocmd.c (_initialize_macrocmd): Add declaration. * macroscope.c (_initialize_macroscope): Add declaration. * maint-test-options.c (_initialize_maint_test_options): Add declaration. * maint-test-settings.c (_initialize_maint_test_settings): Add declaration. * maint.c (_initialize_maint_cmds): Add declaration. * mdebugread.c (_initialize_mdebugread): Add declaration. * memattr.c (_initialize_mem): Add declaration. * mep-tdep.c (_initialize_mep_tdep): Add declaration. * mi/mi-cmd-env.c (_initialize_mi_cmd_env): Add declaration. * mi/mi-cmds.c (_initialize_mi_cmds): Add declaration. * mi/mi-interp.c (_initialize_mi_interp): Add declaration. * mi/mi-main.c (_initialize_mi_main): Add declaration. * microblaze-linux-tdep.c (_initialize_microblaze_linux_tdep): Add declaration. * microblaze-tdep.c (_initialize_microblaze_tdep): Add declaration. * mips-fbsd-nat.c (_initialize_mips_fbsd_nat): Add declaration. * mips-fbsd-tdep.c (_initialize_mips_fbsd_tdep): Add declaration. * mips-linux-nat.c (_initialize_mips_linux_nat): Add declaration. * mips-linux-tdep.c (_initialize_mips_linux_tdep): Add declaration. * mips-nbsd-nat.c (_initialize_mipsnbsd_nat): Add declaration. * mips-nbsd-tdep.c (_initialize_mipsnbsd_tdep): Add declaration. * mips-sde-tdep.c (_initialize_mips_sde_tdep): Add declaration. * mips-tdep.c (_initialize_mips_tdep): Add declaration. * mips64-obsd-nat.c (_initialize_mips64obsd_nat): Add declaration. * mips64-obsd-tdep.c (_initialize_mips64obsd_tdep): Add declaration. * mipsread.c (_initialize_mipsread): Add declaration. * mn10300-linux-tdep.c (_initialize_mn10300_linux_tdep): Add declaration. * mn10300-tdep.c (_initialize_mn10300_tdep): Add declaration. * moxie-tdep.c (_initialize_moxie_tdep): Add declaration. * msp430-tdep.c (_initialize_msp430_tdep): Add declaration. * nds32-tdep.c (_initialize_nds32_tdep): Add declaration. * nios2-linux-tdep.c (_initialize_nios2_linux_tdep): Add declaration. * nios2-tdep.c (_initialize_nios2_tdep): Add declaration. * nto-procfs.c (_initialize_procfs): Add declaration. * objc-lang.c (_initialize_objc_language): Add declaration. * observable.c (_initialize_observer): Add declaration. * opencl-lang.c (_initialize_opencl_language): Add declaration. * or1k-linux-tdep.c (_initialize_or1k_linux_tdep): Add declaration. * or1k-tdep.c (_initialize_or1k_tdep): Add declaration. * osabi.c (_initialize_gdb_osabi): Add declaration. * osdata.c (_initialize_osdata): Add declaration. * p-valprint.c (_initialize_pascal_valprint): Add declaration. * parse.c (_initialize_parse): Add declaration. * ppc-fbsd-nat.c (_initialize_ppcfbsd_nat): Add declaration. * ppc-fbsd-tdep.c (_initialize_ppcfbsd_tdep): Add declaration. * ppc-linux-nat.c (_initialize_ppc_linux_nat): Add declaration. * ppc-linux-tdep.c (_initialize_ppc_linux_tdep): Add declaration. * ppc-nbsd-nat.c (_initialize_ppcnbsd_nat): Add declaration. * ppc-nbsd-tdep.c (_initialize_ppcnbsd_tdep): Add declaration. * ppc-obsd-nat.c (_initialize_ppcobsd_nat): Add declaration. * ppc-obsd-tdep.c (_initialize_ppcobsd_tdep): Add declaration. * printcmd.c (_initialize_printcmd): Add declaration. * probe.c (_initialize_probe): Add declaration. * proc-api.c (_initialize_proc_api): Add declaration. * proc-events.c (_initialize_proc_events): Add declaration. * proc-service.c (_initialize_proc_service): Add declaration. * procfs.c (_initialize_procfs): Add declaration. * producer.c (_initialize_producer): Add declaration. * psymtab.c (_initialize_psymtab): Add declaration. * python/python.c (_initialize_python): Add declaration. * ravenscar-thread.c (_initialize_ravenscar): Add declaration. * record-btrace.c (_initialize_record_btrace): Add declaration. * record-full.c (_initialize_record_full): Add declaration. * record.c (_initialize_record): Add declaration. * regcache-dump.c (_initialize_regcache_dump): Add declaration. * regcache.c (_initialize_regcache): Add declaration. * reggroups.c (_initialize_reggroup): Add declaration. * remote-notif.c (_initialize_notif): Add declaration. * remote-sim.c (_initialize_remote_sim): Add declaration. * remote.c (_initialize_remote): Add declaration. * reverse.c (_initialize_reverse): Add declaration. * riscv-fbsd-nat.c (_initialize_riscv_fbsd_nat): Add declaration. * riscv-fbsd-tdep.c (_initialize_riscv_fbsd_tdep): Add declaration. * riscv-linux-nat.c (_initialize_riscv_linux_nat): Add declaration. * riscv-linux-tdep.c (_initialize_riscv_linux_tdep): Add declaration. * riscv-tdep.c (_initialize_riscv_tdep): Add declaration. * rl78-tdep.c (_initialize_rl78_tdep): Add declaration. * rs6000-aix-tdep.c (_initialize_rs6000_aix_tdep): Add declaration. * rs6000-lynx178-tdep.c (_initialize_rs6000_lynx178_tdep): Add declaration. * rs6000-nat.c (_initialize_rs6000_nat): Add declaration. * rs6000-tdep.c (_initialize_rs6000_tdep): Add declaration. * run-on-main-thread.c (_initialize_run_on_main_thread): Add declaration. * rust-exp.y (_initialize_rust_exp): Add declaration. * rx-tdep.c (_initialize_rx_tdep): Add declaration. * s12z-tdep.c (_initialize_s12z_tdep): Add declaration. * s390-linux-nat.c (_initialize_s390_nat): Add declaration. * s390-linux-tdep.c (_initialize_s390_linux_tdep): Add declaration. * s390-tdep.c (_initialize_s390_tdep): Add declaration. * score-tdep.c (_initialize_score_tdep): Add declaration. * ser-go32.c (_initialize_ser_dos): Add declaration. * ser-mingw.c (_initialize_ser_windows): Add declaration. * ser-pipe.c (_initialize_ser_pipe): Add declaration. * ser-tcp.c (_initialize_ser_tcp): Add declaration. * ser-uds.c (_initialize_ser_socket): Add declaration. * ser-unix.c (_initialize_ser_hardwire): Add declaration. * serial.c (_initialize_serial): Add declaration. * sh-linux-tdep.c (_initialize_sh_linux_tdep): Add declaration. * sh-nbsd-nat.c (_initialize_shnbsd_nat): Add declaration. * sh-nbsd-tdep.c (_initialize_shnbsd_tdep): Add declaration. * sh-tdep.c (_initialize_sh_tdep): Add declaration. * skip.c (_initialize_step_skip): Add declaration. * sol-thread.c (_initialize_sol_thread): Add declaration. * solib-aix.c (_initialize_solib_aix): Add declaration. * solib-darwin.c (_initialize_darwin_solib): Add declaration. * solib-dsbt.c (_initialize_dsbt_solib): Add declaration. * solib-frv.c (_initialize_frv_solib): Add declaration. * solib-svr4.c (_initialize_svr4_solib): Add declaration. * solib-target.c (_initialize_solib_target): Add declaration. * solib.c (_initialize_solib): Add declaration. * source-cache.c (_initialize_source_cache): Add declaration. * source.c (_initialize_source): Add declaration. * sparc-linux-nat.c (_initialize_sparc_linux_nat): Add declaration. * sparc-linux-tdep.c (_initialize_sparc_linux_tdep): Add declaration. * sparc-nat.c (_initialize_sparc_nat): Add declaration. * sparc-nbsd-nat.c (_initialize_sparcnbsd_nat): Add declaration. * sparc-nbsd-tdep.c (_initialize_sparcnbsd_tdep): Add declaration. * sparc-obsd-tdep.c (_initialize_sparc32obsd_tdep): Add declaration. * sparc-sol2-tdep.c (_initialize_sparc_sol2_tdep): Add declaration. * sparc-tdep.c (_initialize_sparc_tdep): Add declaration. * sparc64-fbsd-nat.c (_initialize_sparc64fbsd_nat): Add declaration. * sparc64-fbsd-tdep.c (_initialize_sparc64fbsd_tdep): Add declaration. * sparc64-linux-nat.c (_initialize_sparc64_linux_nat): Add declaration. * sparc64-linux-tdep.c (_initialize_sparc64_linux_tdep): Add declaration. * sparc64-nat.c (_initialize_sparc64_nat): Add declaration. * sparc64-nbsd-nat.c (_initialize_sparc64nbsd_nat): Add declaration. * sparc64-nbsd-tdep.c (_initialize_sparc64nbsd_tdep): Add declaration. * sparc64-obsd-nat.c (_initialize_sparc64obsd_nat): Add declaration. * sparc64-obsd-tdep.c (_initialize_sparc64obsd_tdep): Add declaration. * sparc64-sol2-tdep.c (_initialize_sparc64_sol2_tdep): Add declaration. * sparc64-tdep.c (_initialize_sparc64_adi_tdep): Add declaration. * stabsread.c (_initialize_stabsread): Add declaration. * stack.c (_initialize_stack): Add declaration. * stap-probe.c (_initialize_stap_probe): Add declaration. * std-regs.c (_initialize_frame_reg): Add declaration. * symfile-debug.c (_initialize_symfile_debug): Add declaration. * symfile-mem.c (_initialize_symfile_mem): Add declaration. * symfile.c (_initialize_symfile): Add declaration. * symmisc.c (_initialize_symmisc): Add declaration. * symtab.c (_initialize_symtab): Add declaration. * target.c (_initialize_target): Add declaration. * target-connection.c (_initialize_target_connection): Add declaration. * target-dcache.c (_initialize_target_dcache): Add declaration. * target-descriptions.c (_initialize_target_descriptions): Add declaration. * thread.c (_initialize_thread): Add declaration. * tic6x-linux-tdep.c (_initialize_tic6x_linux_tdep): Add declaration. * tic6x-tdep.c (_initialize_tic6x_tdep): Add declaration. * tilegx-linux-nat.c (_initialize_tile_linux_nat): Add declaration. * tilegx-linux-tdep.c (_initialize_tilegx_linux_tdep): Add declaration. * tilegx-tdep.c (_initialize_tilegx_tdep): Add declaration. * tracectf.c (_initialize_ctf): Add declaration. * tracefile-tfile.c (_initialize_tracefile_tfile): Add declaration. * tracefile.c (_initialize_tracefile): Add declaration. * tracepoint.c (_initialize_tracepoint): Add declaration. * tui/tui-hooks.c (_initialize_tui_hooks): Add declaration. * tui/tui-interp.c (_initialize_tui_interp): Add declaration. * tui/tui-layout.c (_initialize_tui_layout): Add declaration. * tui/tui-regs.c (_initialize_tui_regs): Add declaration. * tui/tui-stack.c (_initialize_tui_stack): Add declaration. * tui/tui-win.c (_initialize_tui_win): Add declaration. * tui/tui.c (_initialize_tui): Add declaration. * typeprint.c (_initialize_typeprint): Add declaration. * ui-style.c (_initialize_ui_style): Add declaration. * unittests/array-view-selftests.c (_initialize_array_view_selftests): Add declaration. * unittests/child-path-selftests.c (_initialize_child_path_selftests): Add declaration. * unittests/cli-utils-selftests.c (_initialize_cli_utils_selftests): Add declaration. * unittests/common-utils-selftests.c (_initialize_common_utils_selftests): Add declaration. * unittests/copy_bitwise-selftests.c (_initialize_copy_bitwise_utils_selftests): Add declaration. * unittests/environ-selftests.c (_initialize_environ_selftests): Add declaration. * unittests/filtered_iterator-selftests.c (_initialize_filtered_iterator_selftests): Add declaration. * unittests/format_pieces-selftests.c (_initialize_format_pieces_selftests): Add declaration. * unittests/function-view-selftests.c (_initialize_function_view_selftests): Add declaration. * unittests/help-doc-selftests.c (_initialize_help_doc_selftests): Add declaration. * unittests/lookup_name_info-selftests.c (_initialize_lookup_name_info_selftests): Add declaration. * unittests/main-thread-selftests.c (_initialize_main_thread_selftests): Add declaration. * unittests/memory-map-selftests.c (_initialize_memory_map_selftests): Add declaration. * unittests/memrange-selftests.c (_initialize_memrange_selftests): Add declaration. * unittests/mkdir-recursive-selftests.c (_initialize_mkdir_recursive_selftests): Add declaration. * unittests/observable-selftests.c (_initialize_observer_selftest): Add declaration. * unittests/offset-type-selftests.c (_initialize_offset_type_selftests): Add declaration. * unittests/optional-selftests.c (_initialize_optional_selftests): Add declaration. * unittests/parse-connection-spec-selftests.c (_initialize_parse_connection_spec_selftests): Add declaration. * unittests/rsp-low-selftests.c (_initialize_rsp_low_selftests): Add declaration. * unittests/scoped_fd-selftests.c (_initialize_scoped_fd_selftests): Add declaration. * unittests/scoped_mmap-selftests.c (_initialize_scoped_mmap_selftests): Add declaration. * unittests/scoped_restore-selftests.c (_initialize_scoped_restore_selftests): Add declaration. * unittests/string_view-selftests.c (_initialize_string_view_selftests): Add declaration. * unittests/style-selftests.c (_initialize_style_selftest): Add declaration. * unittests/tracepoint-selftests.c (_initialize_tracepoint_selftests): Add declaration. * unittests/tui-selftests.c (_initialize_tui_selftest): Add declaration. * unittests/unpack-selftests.c (_initialize_unpack_selftests): Add declaration. * unittests/utils-selftests.c (_initialize_utils_selftests): Add declaration. * unittests/vec-utils-selftests.c (_initialize_vec_utils_selftests): Add declaration. * unittests/xml-utils-selftests.c (_initialize_xml_utils): Add declaration. * user-regs.c (_initialize_user_regs): Add declaration. * utils.c (_initialize_utils): Add declaration. * v850-tdep.c (_initialize_v850_tdep): Add declaration. * valops.c (_initialize_valops): Add declaration. * valprint.c (_initialize_valprint): Add declaration. * value.c (_initialize_values): Add declaration. * varobj.c (_initialize_varobj): Add declaration. * vax-bsd-nat.c (_initialize_vaxbsd_nat): Add declaration. * vax-nbsd-tdep.c (_initialize_vaxnbsd_tdep): Add declaration. * vax-tdep.c (_initialize_vax_tdep): Add declaration. * windows-nat.c (_initialize_windows_nat): Add declaration. (_initialize_check_for_gdb_ini): Add declaration. (_initialize_loadable): Add declaration. * windows-tdep.c (_initialize_windows_tdep): Add declaration. * x86-bsd-nat.c (_initialize_x86_bsd_nat): Add declaration. * x86-linux-nat.c (_initialize_x86_linux_nat): Add declaration. * xcoffread.c (_initialize_xcoffread): Add declaration. * xml-support.c (_initialize_xml_support): Add declaration. * xstormy16-tdep.c (_initialize_xstormy16_tdep): Add declaration. * xtensa-linux-nat.c (_initialize_xtensa_linux_nat): Add declaration. * xtensa-linux-tdep.c (_initialize_xtensa_linux_tdep): Add declaration. * xtensa-tdep.c (_initialize_xtensa_tdep): Add declaration. Change-Id: I13eec7e0ed2b3c427377a7bdb055cf46da64def9
2020-01-13 20:01:38 +01:00
_initialize_riscv_tdep ()
{
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
riscv_create_csr_aliases ();
riscv_init_reggroups ();
gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
/* Add root prefix command for all "set debug riscv" and "show debug
riscv" commands. */
add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
_("RISC-V specific debug commands."),
&setdebugriscvcmdlist, "set debug riscv ", 0,
&setdebuglist);
add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
_("RISC-V specific debug commands."),
&showdebugriscvcmdlist, "show debug riscv ", 0,
&showdebuglist);
Use the existing instruction to determine the RISC-V breakpoint kind. RISC-V supports instructions of varying lengths. Standard existing instructions in the base ISA are 4 bytes in length, but the 'C' extension adds support for compressed, 2 byte instructions. RISC-V supports two different breakpoint instructions: EBREAK is a 4 byte instruction in the base ISA, and C.EBREAK is a 2 byte instruction only available on processors implementing the 'C' extension. Using EBREAK to set breakpoints on compressed instructions causes problems as the second half of EBREAK will overwrite the first 2 bytes of the following instruction breaking other threads in the process if their PC is the following instruction. Thus, breakpoints on compressed instructions need to use C.EBREAK instead of EBREAK. Previously, the riscv architecture checked the MISA register to determine if the 'C' extension was available. If so, it used C.EBREAK for all breakpoints. However, the MISA register is not necessarily available to supervisor mode operating systems. While native targets could provide a fake MISA register value, this patch instead examines the existing instruction at a breakpoint target to determine which breakpoint instruction to use. If the existing instruction is a compressed instruction, C.EBREAK is used, otherwise EBREAK is used. gdb/ChangeLog: * disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to case with explicit breakpoint kind. * riscv-tdep.c (show_use_compressed_breakpoints): Remove 'additional_info' and related logic. (riscv_debug_breakpoints): New variable. (riscv_breakpoint_kind_from_pc): Use the length of the existing instruction to determine the breakpoint kind. (_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints' flag. Update description of 'set/show riscv use-compressed-breakpoints' flag.
2018-09-28 23:15:54 +02:00
add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
&riscv_debug_breakpoints, _("\
Set riscv breakpoint debugging."), _("\
Show riscv breakpoint debugging."), _("\
When non-zero, print debugging information for the riscv specific parts\n\
of the breakpoint mechanism."),
NULL,
show_riscv_debug_variable,
&setdebugriscvcmdlist, &showdebugriscvcmdlist);
add_setshow_zuinteger_cmd ("infcall", class_maintenance,
&riscv_debug_infcall, _("\
Set riscv inferior call debugging."), _("\
Show riscv inferior call debugging."), _("\
When non-zero, print debugging information for the riscv specific parts\n\
of the inferior call mechanism."),
NULL,
show_riscv_debug_variable,
&setdebugriscvcmdlist, &showdebugriscvcmdlist);
add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
&riscv_debug_unwinder, _("\
Set riscv stack unwinding debugging."), _("\
Show riscv stack unwinding debugging."), _("\
When non-zero, print debugging information for the riscv specific parts\n\
of the stack unwinding mechanism."),
NULL,
show_riscv_debug_variable,
&setdebugriscvcmdlist, &showdebugriscvcmdlist);
gdb/riscv: Add target description support This commit adds target description support for riscv. I've used the split feature approach for specifying the architectural features, and the CSR feature is auto-generated from the riscv-opc.h header file. If the target doesn't provide a suitable target description then GDB will build one by looking at the bfd headers. This commit does not implement target description creation for the Linux or FreeBSD native targets, both of these will need to add read_description methods into their respective target classes, which probe the target features, and then call riscv_create_target_description to build a suitable target description. Until this is done Linux and FreeBSD will get the same default target description based on the bfd that bare-metal targets get. I've only added feature descriptions for 32 and 64 bit registers, 128 bit registers (for RISC-V) are not supported in the reset of GDB yet. This commit removes the special reading of the MISA register in order to establish the target features, this was only used for figuring out the f-register size, and even that wasn't done consistently. We now rely on the target to tell us what size of registers it has (or look in the BFD as a last resort). The result of this is that we should now support RV64 targets with 32-bit float, though I have not extensively tested this combination yet. * Makefile.in (ALL_TARGET_OBS): Add arch/riscv.o. (HFILES_NO_SRCDIR): Add arch/riscv.h. * arch/riscv.c: New file. * arch/riscv.h: New file. * configure.tgt: Add cpu_obs list of riscv, move riscv-tdep.o into this list, and add arch/riscv.o. * features/Makefile: Add riscv features. * features/riscv/32bit-cpu.c: New file. * features/riscv/32bit-cpu.xml: New file. * features/riscv/32bit-csr.c: New file. * features/riscv/32bit-csr.xml: New file. * features/riscv/32bit-fpu.c: New file. * features/riscv/32bit-fpu.xml: New file. * features/riscv/64bit-cpu.c: New file. * features/riscv/64bit-cpu.xml: New file. * features/riscv/64bit-csr.c: New file. * features/riscv/64bit-csr.xml: New file. * features/riscv/64bit-fpu.c: New file. * features/riscv/64bit-fpu.xml: New file. * features/riscv/rebuild-csr-xml.sh: New file. * riscv-tdep.c: Add 'arch/riscv.h' include. (riscv_gdb_reg_names): Delete. (csr_reggroup): New global. (struct riscv_register_alias): Delete. (struct riscv_register_feature): New structure. (riscv_register_aliases): Delete. (riscv_xreg_feature): New global. (riscv_freg_feature): New global. (riscv_virtual_feature): New global. (riscv_csr_feature): New global. (riscv_create_csr_aliases): New function. (riscv_read_misa_reg): Delete. (riscv_has_feature): Delete. (riscv_isa_xlen): Simplify, just return cached xlen. (riscv_isa_flen): Simplify, just return cached flen. (riscv_has_fp_abi): Update for changes in struct gdbarch_tdep. (riscv_register_name): Update to make use of tdesc_register_name. Look up xreg and freg names in the new globals riscv_xreg_feature and riscv_freg_feature. Don't supply csr aliases here. (riscv_fpreg_q_type): Delete. (riscv_register_type): Use tdesc_register_type in almost all cases, override the returned type in a few specific cases only. (riscv_print_one_register_info): Handle errors reading registers. (riscv_register_reggroup_p): Use tdesc_register_in_reggroup_p for registers that are otherwise unknown to GDB. Also check the csr_reggroup. (riscv_print_registers_info): Remove assert about upper register number, and use gdbarch_register_reggroup_p instead of short-cutting. (riscv_find_default_target_description): New function. (riscv_check_tdesc_feature): New function. (riscv_add_reggroups): New function. (riscv_setup_register_aliases): New function. (riscv_init_reggroups): New function. (_initialize_riscv_tdep): Add calls to setup CSR aliases, and setup register groups. Register new riscv debug variable. * riscv-tdep.h: Add 'arch/riscv.h' include. (struct gdbarch_tdep): Remove abi union, and add riscv_gdbarch_features field. Remove cached quad floating point type, and provide initialisation for double type field. * target-descriptions.c (maint_print_c_tdesc_cmd): Add riscv to the list of targets using the feature based target descriptions. * NEWS: Mention target description support. gdb/doc/ChangeLog: * gdb.texinfo (Standard Target Features): Add RISC-V Features sub-section.
2018-10-29 16:10:52 +01:00
add_setshow_zuinteger_cmd ("gdbarch", class_maintenance,
&riscv_debug_gdbarch, _("\
Set riscv gdbarch initialisation debugging."), _("\
Show riscv gdbarch initialisation debugging."), _("\
When non-zero, print debugging information for the riscv gdbarch\n\
initialisation process."),
NULL,
show_riscv_debug_variable,
&setdebugriscvcmdlist, &showdebugriscvcmdlist);
/* Add root prefix command for all "set riscv" and "show riscv" commands. */
add_prefix_cmd ("riscv", no_class, set_riscv_command,
_("RISC-V specific commands."),
&setriscvcmdlist, "set riscv ", 0, &setlist);
add_prefix_cmd ("riscv", no_class, show_riscv_command,
_("RISC-V specific commands."),
&showriscvcmdlist, "show riscv ", 0, &showlist);
use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
&use_compressed_breakpoints,
_("\
Set debugger's use of compressed breakpoints."), _(" \
Show debugger's use of compressed breakpoints."), _("\
Use the existing instruction to determine the RISC-V breakpoint kind. RISC-V supports instructions of varying lengths. Standard existing instructions in the base ISA are 4 bytes in length, but the 'C' extension adds support for compressed, 2 byte instructions. RISC-V supports two different breakpoint instructions: EBREAK is a 4 byte instruction in the base ISA, and C.EBREAK is a 2 byte instruction only available on processors implementing the 'C' extension. Using EBREAK to set breakpoints on compressed instructions causes problems as the second half of EBREAK will overwrite the first 2 bytes of the following instruction breaking other threads in the process if their PC is the following instruction. Thus, breakpoints on compressed instructions need to use C.EBREAK instead of EBREAK. Previously, the riscv architecture checked the MISA register to determine if the 'C' extension was available. If so, it used C.EBREAK for all breakpoints. However, the MISA register is not necessarily available to supervisor mode operating systems. While native targets could provide a fake MISA register value, this patch instead examines the existing instruction at a breakpoint target to determine which breakpoint instruction to use. If the existing instruction is a compressed instruction, C.EBREAK is used, otherwise EBREAK is used. gdb/ChangeLog: * disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to case with explicit breakpoint kind. * riscv-tdep.c (show_use_compressed_breakpoints): Remove 'additional_info' and related logic. (riscv_debug_breakpoints): New variable. (riscv_breakpoint_kind_from_pc): Use the length of the existing instruction to determine the breakpoint kind. (_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints' flag. Update description of 'set/show riscv use-compressed-breakpoints' flag.
2018-09-28 23:15:54 +02:00
Debugging compressed code requires compressed breakpoints to be used. If\n\
left to 'auto' then gdb will use them if the existing instruction is a\n\
compressed instruction. If that doesn't give the correct behavior, then\n\
this option can be used."),
NULL,
show_use_compressed_breakpoints,
&setriscvcmdlist,
&showriscvcmdlist);
}