2015-05-15 18:47:39 +02:00
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2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
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PR binutis/18386
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* i386-dis.c: Add comments for '@'.
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(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
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(enum x86_64_isa): New.
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(isa64): Likewise.
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(print_i386_disassembler_options): Add amd64 and intel64.
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(print_insn): Handle amd64 and intel64.
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(putop): Handle '@'.
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(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
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* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
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* i386-opc.h (AMD64): New.
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(CpuIntel64): Likewise.
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(i386_cpu_flags): Add cpuamd64 and cpuintel64.
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* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
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Mark direct call/jmp without Disp16|Disp32 as Intel64.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Likewise.
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2015-05-15 03:57:50 +02:00
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2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (IH) New define.
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(powerpc_opcodes) <wait>: Do not enable for POWER7.
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<tlbie>: Add RS operand for POWER7.
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<slbia>: Add IH operand for POWER6.
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2015-05-11 23:20:37 +02:00
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2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
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* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
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direct branch.
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(jmp): Likewise.
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* i386-tbl.h: Regenerated.
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2015-05-11 19:47:55 +02:00
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2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
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* configure.ac: Support bfd_iamcu_arch.
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* disassemble.c (disassembler): Support bfd_iamcu_arch.
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* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
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CPU_IAMCU_COMPAT_FLAGS.
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(cpu_flags): Add CpuIAMCU.
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* i386-opc.h (CpuIAMCU): New.
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(i386_cpu_flags): Add cpuiamcu.
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* configure: Regenerated.
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* i386-init.h: Likewise.
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* i386-tbl.h: Likewise.
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2015-05-13 13:33:45 +02:00
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2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
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PR binutis/18386
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* i386-dis.c (X86_64_E8): New.
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(X86_64_E9): Likewise.
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Update comments on 'T', 'U', 'V'. Add comments for '^'.
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(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
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(x86_64_table): Add X86_64_E8 and X86_64_E9.
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(mod_table): Replace {T|} with ^ on Jcall/Jmp.
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(putop): Handle '^'.
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(OP_J): Ignore the operand size prefix in 64-bit. Don't check
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REX_W.
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2015-04-30 21:25:49 +02:00
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2015-04-30 DJ Delorie <dj@redhat.com>
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* disassemble.c (disassembler): Choose suitable disassembler based
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on E_ABI.
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* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
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it to decode mul/div insns.
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* rl78-decode.c: Regenerate.
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* rl78-dis.c (print_insn_rl78): Rename to...
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(print_insn_rl78_common): ...this, take ISA parameter.
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(print_insn_rl78): New.
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(print_insn_rl78_g10): New.
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(print_insn_rl78_g13): New.
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(print_insn_rl78_g14): New.
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(rl78_get_disassembler): New.
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2015-04-29 17:24:52 +02:00
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2015-04-29 Nick Clifton <nickc@redhat.com>
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* po/fr.po: Updated French translation.
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2015-04-27 18:06:54 +02:00
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2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-opc.c (DCBT_EO): New define.
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(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
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<lharx>: Likewise.
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<stbcx.>: Likewise.
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<sthcx.>: Likewise.
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<waitrsv>: Do not enable for POWER7 and later.
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<waitimpl>: Likewise.
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<dcbt>: Default to the two operand form of the instruction for all
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"old" cpus. For "new" cpus, use the operand ordering that matches
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whether the cpu is server or embedded.
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<dcbtst>: Likewise.
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2015-04-27 10:29:16 +02:00
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2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
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* s390-opc.c: New instruction type VV0UU2.
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* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
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and WFC.
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x86: disambiguate disassembly of certain AVX512 insns
Certain conversion operations as well as vfpclassp{d,s} are ambiguous
when the input operand is in memory and no broadcast is being used.
While in Intel mode this gets resolved by printing suitable operand
size modifiers, AT&T mode need mnemonic suffixes to be added.
gas/testsuite/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* gas/i386/avx512dq.d: Add 'z' suffix to vfpclassp{d,s} non-
register, non-broadcast cases.
* gas/i386/x86-64-avx512dq.d: Likewise.
* gas/i386/avx512dq_vl.d: Add 'x' and 'y' suffixes to
vcvt{,u}qq2ps and vfpclassp{d,s} non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512dq_vl.d: Likewise.
* gas/i386/avx512f_vl.d: Add 'x' and 'y' suffixes to
vcvt{,t}pd2{,u}dq and vcvtpd2ps non-register, non-broadcast
cases.
* gas/i386/x86-64-avx512f_vl.d: Likewise.
opcodes/
2015-04-23 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
(vfpclasspd, vfpclassps): Add %XZ.
2015-04-23 16:42:40 +02:00
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2015-04-23 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
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* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
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vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
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(vfpclasspd, vfpclassps): Add %XZ.
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2015-04-16 00:58:45 +02:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (PREFIX_UD_SHIFT): Removed.
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(PREFIX_UD_REPZ): Likewise.
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(PREFIX_UD_REPNZ): Likewise.
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(PREFIX_UD_DATA): Likewise.
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(PREFIX_UD_ADDR): Likewise.
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(PREFIX_UD_LOCK): Likewise.
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2015-04-15 20:28:16 +02:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (prefix_requirement): Removed.
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(print_insn): Don't set prefix_requirement. Check
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dp->prefix_requirement instead of prefix_requirement.
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2015-04-15 18:53:13 +02:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/17898
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* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
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(PREFIX_MOD_0_0FC7_REG_6): This.
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(PREFIX_MOD_3_0FC7_REG_6): New.
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(PREFIX_MOD_3_0FC7_REG_7): Likewise.
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(prefix_table): Replace PREFIX_0FC7_REG_6 with
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PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
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PREFIX_MOD_3_0FC7_REG_7.
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(mod_table): Replace PREFIX_0FC7_REG_6 with
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PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
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PREFIX_MOD_3_0FC7_REG_7.
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2015-04-15 18:24:45 +02:00
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2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
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(PREFIX_MANDATORY_REPNZ): Likewise.
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(PREFIX_MANDATORY_DATA): Likewise.
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(PREFIX_MANDATORY_ADDR): Likewise.
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(PREFIX_MANDATORY_LOCK): Likewise.
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(PREFIX_MANDATORY): Likewise.
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(PREFIX_UD_SHIFT): Set to 8
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(PREFIX_UD_REPZ): Updated.
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(PREFIX_UD_REPNZ): Likewise.
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(PREFIX_UD_DATA): Likewise.
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(PREFIX_UD_ADDR): Likewise.
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(PREFIX_UD_LOCK): Likewise.
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(PREFIX_IGNORED_SHIFT): New.
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(PREFIX_IGNORED_REPZ): Likewise.
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(PREFIX_IGNORED_REPNZ): Likewise.
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(PREFIX_IGNORED_DATA): Likewise.
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(PREFIX_IGNORED_ADDR): Likewise.
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(PREFIX_IGNORED_LOCK): Likewise.
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(PREFIX_OPCODE): Likewise.
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(PREFIX_IGNORED): Likewise.
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(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
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(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
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(three_byte_table): Likewise.
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(mod_table): Likewise.
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(mandatory_prefix): Renamed to ...
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(prefix_requirement): This.
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(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
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Update PREFIX_90 entry.
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(get_valid_dis386): Check prefix_requirement to see if a prefix
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should be ignored.
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(print_insn): Replace mandatory_prefix with prefix_requirement.
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2015-04-15 18:44:03 +02:00
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2015-04-15 Renlin Li <renlin.li@arm.com>
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* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
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use it for ssat and ssat16.
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(print_insn_thumb32): Add handle case for 'D' control code.
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x86: Use individual prefix control for each opcode.
2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_OPTIONAL, PREFIX_MANDATORY):
Define.
(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
Fill prefix_requirement field.
(struct dis386): Add prefix_requirement field.
(dis386): Fill prefix_requirement field.
(dis386_twobyte): Ditto.
(twobyte_has_mandatory_prefix_: Remove.
(reg_table): Fill prefix_requirement field.
(prefix_table): Ditto.
(x86_64_table): Ditto.
(three_byte_table): Ditto.
(xop_table): Ditto.
(vex_table): Ditto.
(vex_len_table): Ditto.
(vex_w_table): Ditto.
(mod_table): Ditto.
(bad_opcode): Ditto.
(print_insn): Use prefix_requirement.
(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
(float_reg): Ditto.
2015-04-06 18:33:01 +02:00
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2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
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H.J. Lu <hongjiu.lu@intel.com>
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* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
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* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
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PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
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PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
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PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
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(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
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Fill prefix_requirement field.
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(struct dis386): Add prefix_requirement field.
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(dis386): Fill prefix_requirement field.
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(dis386_twobyte): Ditto.
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(twobyte_has_mandatory_prefix_: Remove.
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(reg_table): Fill prefix_requirement field.
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(prefix_table): Ditto.
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(x86_64_table): Ditto.
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(three_byte_table): Ditto.
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(xop_table): Ditto.
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(vex_table): Ditto.
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(vex_len_table): Ditto.
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(vex_w_table): Ditto.
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(mod_table): Ditto.
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(bad_opcode): Ditto.
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(print_insn): Use prefix_requirement.
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(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
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FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
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(float_reg): Ditto.
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2015-03-30 07:40:09 +02:00
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2015-03-30 Mike Frysinger <vapier@gentoo.org>
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* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
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2015-03-29 16:46:30 +02:00
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2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
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* Makefile.in: Regenerated.
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2015-03-25 03:44:28 +01:00
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2015-03-25 Anton Blanchard <anton@samba.org>
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|
* ppc-dis.c (disassemble_init_powerpc): Only initialise
|
|
|
|
|
|
powerpc_opcd_indices and vle_opcd_indices once.
|
|
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|
2015-03-25 03:43:18 +01:00
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2015-03-25 Anton Blanchard <anton@samba.org>
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* ppc-opc.c (powerpc_opcodes): Add slbfee.
|
|
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|
2015-03-24 07:08:08 +01:00
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2015-03-24 Terry Guo <terry.guo@arm.com>
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* arm-dis.c (opcode32): Updated to use new arm feature struct.
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(opcode16): Likewise.
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(coprocessor_opcodes): Replace bit with feature struct.
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(neon_opcodes): Likewise.
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|
(arm_opcodes): Likewise.
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(thumb_opcodes): Likewise.
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(thumb32_opcodes): Likewise.
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(print_insn_coprocessor): Likewise.
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(print_insn_arm): Likewise.
|
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(select_arm_features): Follow new feature struct.
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2015-03-17 17:19:15 +01:00
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2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
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* i386-dis.c (rm_table): Add clzero.
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* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
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Add CPU_CLZERO_FLAGS.
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(cpu_flags): Add CpuCLZERO.
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* i386-opc.h: Add CpuCLZERO.
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* i386-opc.tbl: Add clzero.
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* i386-init.h: Re-generated.
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|
* i386-tbl.h: Re-generated.
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|
2015-03-13 23:42:55 +01:00
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2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
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* mips-opc.c (decode_mips_operand): Fix constraint issues
|
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|
with u and y operands.
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|
2015-03-13 23:02:16 +01:00
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|
2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
|
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* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
|
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|
2015-03-10 12:44:54 +01:00
|
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|
|
2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
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|
* s390-opc.c: Add new IBM z13 instructions.
|
|
|
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|
* s390-opc.txt: Likewise.
|
|
|
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|
|
2015-03-10 12:27:56 +01:00
|
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|
2015-03-10 Renlin Li <renlin.li@arm.com>
|
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|
* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
|
|
|
|
|
|
stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
|
|
|
|
|
|
related alias.
|
|
|
|
|
|
* aarch64-asm-2.c: Regenerate.
|
|
|
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|
|
* aarch64-dis-2.c: Likewise.
|
|
|
|
|
|
* aarch64-opc-2.c: Likewise.
|
|
|
|
|
|
|
2015-03-03 16:00:59 +01:00
|
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|
|
2015-03-03 Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
|
|
|
|
|
|
|
2015-02-25 21:22:54 +01:00
|
|
|
|
2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
|
|
|
|
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|
|
|
|
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|
|
* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
|
|
|
|
|
|
arch_sh_up.
|
|
|
|
|
|
(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
|
|
|
|
|
|
arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
|
|
|
|
|
|
|
2015-02-23 18:16:30 +01:00
|
|
|
|
2015-02-23 Vinay <Vinay.G@kpit.com>
|
|
|
|
|
|
|
|
|
|
|
|
* rl78-decode.opc (MOV): Added space between two operands for
|
|
|
|
|
|
'mov' instruction in index addressing mode.
|
|
|
|
|
|
* rl78-decode.c: Regenerate.
|
|
|
|
|
|
|
2015-02-12 10:59:03 +01:00
|
|
|
|
2015-02-19 Pedro Alves <palves@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
|
|
|
|
|
|
|
opcodes/microblaze: Rename 'or', 'and', 'xor' to avoid C++ conflict
Building GDB as a C++ program, we see:
In file included from gdb/microblaze-tdep.c:37:0:
gdb/../opcodes/../opcodes/microblaze-opcm.h: At global scope:
gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected identifier before ‘or’ token
ncget, ncput, muli, bslli, bsrai, bsrli, mului, or, and, xor,
^
gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected ‘}’ before ‘or’ token
gdb/../opcodes/../opcodes/microblaze-opcm.h:32:51: error: expected unqualified-id before ‘or’ token
gdb/../opcodes/../opcodes/microblaze-opcm.h:60:1: error: expected declaration before ‘}’ token
};
^
opcodes/ChangeLog:
2015-02-10 Pedro Alves <palves@redhat.com>
Tom Tromey <tromey@redhat.com>
* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
microblaze_and, microblaze_xor.
* microblaze-opc.h (opcodes): Adjust.
2015-02-10 19:09:39 +01:00
|
|
|
|
2015-02-10 Pedro Alves <palves@redhat.com>
|
|
|
|
|
|
Tom Tromey <tromey@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
|
|
|
|
|
|
microblaze_and, microblaze_xor.
|
|
|
|
|
|
* microblaze-opc.h (opcodes): Adjust.
|
|
|
|
|
|
|
2015-01-28 06:06:43 +01:00
|
|
|
|
2015-01-28 James Bowman <james.bowman@ftdichip.com>
|
|
|
|
|
|
|
|
|
|
|
|
* Makefile.am: Add FT32 files.
|
|
|
|
|
|
* configure.ac: Handle FT32.
|
|
|
|
|
|
* disassemble.c (disassembler): Call print_insn_ft32.
|
|
|
|
|
|
* ft32-dis.c: New file.
|
|
|
|
|
|
* ft32-opc.c: New file.
|
|
|
|
|
|
* Makefile.in: Regenerate.
|
|
|
|
|
|
* configure: Regenerate.
|
|
|
|
|
|
* po/POTFILES.in: Regenerate.
|
|
|
|
|
|
|
2015-01-28 02:12:59 +01:00
|
|
|
|
2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* nds32-asm.c (keyword_sr): Add new system registers.
|
|
|
|
|
|
|
2015-01-16 12:19:21 +01:00
|
|
|
|
2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* s390-dis.c (s390_extract_operand): Support vector register
|
|
|
|
|
|
operands.
|
|
|
|
|
|
(s390_print_insn_with_opcode): Support new operands types and add
|
|
|
|
|
|
new handling of optional operands.
|
|
|
|
|
|
* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
|
|
|
|
|
|
and include opcode/s390.h instead.
|
|
|
|
|
|
(struct op_struct): New field `flags'.
|
|
|
|
|
|
(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
|
|
|
|
|
|
(dumpTable): Dump flags.
|
|
|
|
|
|
(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
|
|
|
|
|
|
string.
|
|
|
|
|
|
* s390-opc.c: Add new operands types, instruction formats, and
|
|
|
|
|
|
instruction masks.
|
|
|
|
|
|
(s390_opformats): Add new formats for .insn.
|
|
|
|
|
|
* s390-opc.txt: Add new instructions.
|
|
|
|
|
|
|
2015-01-01 15:15:26 +01:00
|
|
|
|
2015-01-01 Alan Modra <amodra@gmail.com>
|
2014-12-27 16:57:04 +01:00
|
|
|
|
|
2015-01-01 15:15:26 +01:00
|
|
|
|
Update year range in copyright notice of all files.
|
2014-12-27 16:57:04 +01:00
|
|
|
|
|
2015-01-01 15:15:26 +01:00
|
|
|
|
For older changes see ChangeLog-2014
|
1999-05-03 09:29:11 +02:00
|
|
|
|
|
2015-01-01 15:15:26 +01:00
|
|
|
|
Copyright (C) 2015 Free Software Foundation, Inc.
|
2012-12-10 13:48:03 +01:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
1999-05-03 09:29:11 +02:00
|
|
|
|
Local Variables:
|
2001-01-11 20:01:42 +01:00
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
1999-05-03 09:29:11 +02:00
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
