2017-04-06 18:17:15 +02:00
|
|
|
|
2017-04-06 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h: Add prototypes for wasm32 disassembler.
|
|
|
|
|
|
|
2017-04-05 20:21:33 +02:00
|
|
|
|
2017-04-05 Pedro Alves <palves@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h (disassemble_info) <disassembler_options>: Now a
|
|
|
|
|
|
"const char *".
|
|
|
|
|
|
(next_disassembler_option): Constify.
|
|
|
|
|
|
|
Support ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX
Mark an ALLOC section, which should be placed in special memory area,
with SHF_GNU_MBIND. Its sh_info field indicates the special memory
type. GNU_MBIND section names start with ".mbind" so that they are
placed as orphan sections by linker. All input GNU_MBIND sections
with the same sh_type, sh_flags and sh_info are placed in one output
GNU_MBIND section. In executable and shared object, create a
GNU_MBIND segment for each GNU_MBIND section and its segment type is
PT_GNU_MBIND_LO plus the sh_info value. Each GNU_MBIND segment is
aligned at page boundary.
The assembler syntax:
.section .mbind.foo,"adx",%progbits
^ 0: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.foo,"adx",%progbits,0x1
^ 1: Special memory type.
|
'd' for SHF_GNU_MBIND.
.section .mbind.bar,"adG",%progbits,.foo_group,comdat,0x2
^ 2: Special memory type.
|
'd' for SHF_GNU_MBIND.
bfd/
* elf.c (get_program_header_size): Add a GNU_MBIND segment for
each GNU_MBIND section and align GNU_MBIND section to page size.
(_bfd_elf_map_sections_to_segments): Create a GNU_MBIND
segment for each GNU_MBIND section.
(_bfd_elf_init_private_section_data): Copy sh_info from input
for GNU_MBIND section.
binutils/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* readelf.c (get_segment_type): Handle PT_GNU_MBIND_XXX.
(get_elf_section_flags): Handle SHF_GNU_MBIND.
(process_section_headers): Likewise.
* testsuite/binutils-all/mbind1.s: New file.
* testsuite/binutils-all/objcopy.exp: Run readelf test on
mbind1.s.
gas/
* NEWS: Mention support for ELF SHF_GNU_MBIND.
* config/obj-elf.c (section_match): New.
(get_section): Match both sh_info and group name.
(obj_elf_change_section): Add argument for sh_info. Pass both
sh_info and group name to get_section. Issue an error for
SHF_GNU_MBIND section without SHF_ALLOC. Set sh_info.
(obj_elf_parse_section_letters): Set SHF_GNU_MBIND for 'd'.
(obj_elf_section): Support SHF_GNU_MBIND section info.
* config/obj-elf.h (obj_elf_change_section): Add argument for
sh_info.
* config/tc-arm.c (start_unwind_section): Pass 0 as sh_info to
obj_elf_change_section.
* config/tc-ia64.c (obj_elf_vms_common): Likewise.
* config/tc-microblaze.c (microblaze_s_data): Likewise.
(microblaze_s_sdata): Likewise.
(microblaze_s_rdata): Likewise.
(microblaze_s_bss): Likewise.
* config/tc-mips.c (s_change_section): Likewise.
* config/tc-msp430.c (msp430_profiler): Likewise.
* config/tc-rx.c (parse_rx_section): Likewise.
* config/tc-tic6x.c (tic6x_start_unwind_section): Likewise.
* doc/as.texinfo: Document 'd' for SHF_GNU_MBIND.
* testsuite/gas/elf/elf.exp: Run section12a, section12b and
section13.
* testsuite/gas/elf/section10.d: Updated.
* testsuite/gas/elf/section10.s: Likewise.
* testsuite/gas/elf/section12.s: New file.
* testsuite/gas/elf/section12a.d: Likewise.
* testsuite/gas/elf/section12b.d: Likewise.
* testsuite/gas/elf/section13.l: Likewise.
* testsuite/gas/elf/section13.d: Likewise.
* testsuite/gas/elf/section13.s: Likewise.
include/
* elf/common.h (PT_GNU_MBIND_NUM): New.
(PT_GNU_MBIND_LO): Likewise.
(PT_GNU_MBIND_HI): Likewise.
(SHF_GNU_MBIND): Likewise.
ld/
* NEWS: Mention support for ELF SHF_GNU_MBIND and
PT_GNU_MBIND_XXX.
* emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Place
input GNU_MBIND sections with the same type, attributes and
sh_info field into a single output GNU_MBIND section.
* testsuite/ld-elf/elf.exp: Run mbind2a and mbind2b.
* testsuite/ld-elf/mbind1.s: New file.
* testsuite/ld-elf/mbind1a.d: Likewise.
* testsuite/ld-elf/mbind1b.d: Likewise.
* testsuite/ld-elf/mbind1c.d: Likewise.
* testsuite/ld-elf/mbind2a.s: Likewise.
* testsuite/ld-elf/mbind2b.c: Likewise.
2017-04-04 18:05:48 +02:00
|
|
|
|
2017-04-04 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (PT_GNU_MBIND_NUM): New.
|
|
|
|
|
|
(PT_GNU_MBIND_LO): Likewise.
|
|
|
|
|
|
(PT_GNU_MBIND_HI): Likewise.
|
|
|
|
|
|
(SHF_GNU_MBIND): Likewise.
|
|
|
|
|
|
|
2017-04-03 19:08:29 +02:00
|
|
|
|
2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/riscv.h (RISCV_GP_SYMBOL): New define.
|
|
|
|
|
|
|
2017-03-22 10:09:56 +01:00
|
|
|
|
2017-03-27 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (CSR_PMPCFG0): New define.
|
|
|
|
|
|
(CSR_PMPCFG1): Likewise.
|
|
|
|
|
|
(CSR_PMPCFG2): Likewise.
|
|
|
|
|
|
(CSR_PMPCFG3): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR0): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR1): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR2): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR3): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR4): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR5): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR6): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR7): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR8): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR9): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR10): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR11): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR12): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR13): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR14): Likewise.
|
|
|
|
|
|
(CSR_PMPADDR15): Likewise.
|
|
|
|
|
|
(pmpcfg0): Declare register.
|
|
|
|
|
|
(pmpcfg1): Likewise.
|
|
|
|
|
|
(pmpcfg2): Likewise.
|
|
|
|
|
|
(pmpcfg3): Likewise.
|
|
|
|
|
|
(pmpaddr0): Likewise.
|
|
|
|
|
|
(pmpaddr1): Likewise.
|
|
|
|
|
|
(pmpaddr2): Likewise.
|
|
|
|
|
|
(pmpaddr3): Likewise.
|
|
|
|
|
|
(pmpaddr4): Likewise.
|
|
|
|
|
|
(pmpaddr5): Likewise.
|
|
|
|
|
|
(pmpaddr6): Likewise.
|
|
|
|
|
|
(pmpaddr7): Likewise.
|
|
|
|
|
|
(pmpaddr8): Likewise.
|
|
|
|
|
|
(pmpaddr9): Likewise.
|
|
|
|
|
|
(pmpaddr10): Likewise.
|
|
|
|
|
|
(pmpaddr11): Likewise.
|
|
|
|
|
|
(pmpaddr12): Likewise.
|
|
|
|
|
|
(pmpaddr13): Likewise.
|
|
|
|
|
|
(pmpaddr14): Likewise.
|
|
|
|
|
|
(pmpaddr15): Likewise.
|
|
|
|
|
|
|
2017-03-30 11:57:21 +02:00
|
|
|
|
2017-03-30 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/wasm.h: New file to support wasm32 architecture.
|
|
|
|
|
|
* elf/wasm32.h: Add R_WASM32_32 relocation.
|
|
|
|
|
|
|
2017-03-29 05:13:06 +02:00
|
|
|
|
2017-03-29 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPCODE_RAW): Define.
|
|
|
|
|
|
(PPC_OPCODE_*): Make them all unsigned long long constants.
|
|
|
|
|
|
|
2017-03-27 12:39:50 +02:00
|
|
|
|
2017-03-27 Pip Cet <pipcet@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/wasm32.h: New file to support wasm32 architecture.
|
|
|
|
|
|
|
Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.
opcodes * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
gas * testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-27 12:14:30 +02:00
|
|
|
|
2017-03-27 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
|
|
|
|
|
|
|
2017-03-21 14:21:02 +01:00
|
|
|
|
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.
|
|
|
|
|
|
(S390_INSTR_FLAG_FACILITY_MASK): Adjust value.
|
|
|
|
|
|
|
2017-03-21 12:37:33 +01:00
|
|
|
|
2017-03-21 Rinat Zelig <rinat@mellanox.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/arc.h (insn_class_t): Add DMA class.
|
|
|
|
|
|
|
2017-03-16 17:44:55 +01:00
|
|
|
|
2017-03-16 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (GNU_BUILD_ATTRIBUTE_SHORT_ENUM): New GNU BUILD
|
|
|
|
|
|
note type.
|
|
|
|
|
|
|
2017-03-14 20:56:49 +01:00
|
|
|
|
2017-03-14 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR debug/77589
|
|
|
|
|
|
* dwarf2.def (DW_OP_GNU_variable_value): New opcode.
|
|
|
|
|
|
|
2017-03-13 18:49:32 +01:00
|
|
|
|
2017-03-13 Markus Trippelsdorf <markus@trippelsdorf.de>
|
|
|
|
|
|
|
|
|
|
|
|
PR demangler/70909
|
|
|
|
|
|
PR demangler/67264
|
|
|
|
|
|
* demangle.h (struct demangle_component): Add d_printing field.
|
|
|
|
|
|
(cplus_demangle_print): Remove const qualifier from tree
|
|
|
|
|
|
parameter.
|
|
|
|
|
|
(cplus_demangle_print_callback): Likewise.
|
|
|
|
|
|
|
2017-03-13 10:58:04 +01:00
|
|
|
|
2017-03-13 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21202
|
|
|
|
|
|
* elf/aarch64.h (R_AARCH64_TLSDESC_LD64_LO12_NC): Rename to
|
|
|
|
|
|
R_AARCH64_TLSDESC_LD64_LO12.
|
|
|
|
|
|
(R_AARCH64_TLSDESC_ADD_LO12_NC): Rename to
|
|
|
|
|
|
R_AARCH64_TLSDESC_ADD_LO12_NC.
|
|
|
|
|
|
|
2017-03-10 11:50:34 +01:00
|
|
|
|
2017-03-10 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (EM_LANAI): New machine number.
|
|
|
|
|
|
(EM_BPF): Likewise.
|
|
|
|
|
|
(EM_WEBASSEMBLY): Likewise.
|
|
|
|
|
|
Move low value, deprecated, numbers to their numerical
|
|
|
|
|
|
equivalents.
|
|
|
|
|
|
|
2017-03-08 16:44:04 +01:00
|
|
|
|
2017-03-08 H.J. Lu <hongjiu.lu@intel.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR binutils/21231
|
|
|
|
|
|
* elf/common.h (GNU_PROPERTY_LOPROC): New.
|
|
|
|
|
|
(GNU_PROPERTY_HIPROC): Likewise.
|
|
|
|
|
|
(GNU_PROPERTY_LOUSER): Likewise.
|
|
|
|
|
|
(GNU_PROPERTY_HIUSER): Likewise.
|
|
|
|
|
|
|
2017-03-01 12:09:46 +01:00
|
|
|
|
2017-03-01 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/common.h (SHF_GNU_BUILD_NOTE): Define.
|
|
|
|
|
|
(NT_GNU_PROPERTY_TYPE_0): Define.
|
|
|
|
|
|
(NT_GNU_BUILD_ATTRIBUTE_OPEN): Define.
|
|
|
|
|
|
(NT_GNU_BUILD_ATTRIBUTE_FUN): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_NUMERIC): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_STRING): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_TRUE): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TYPE_BOOL_FALSE): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_VERSION): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_STACK_PROT): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_RELRO): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_STACK_SIZE): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_TOOL): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_ABI): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRIBUTE_PIC): Define.
|
|
|
|
|
|
(NOTE_GNU_PROPERTY_SECTION_NAME): Define.
|
|
|
|
|
|
(GNU_BUILD_ATTRS_SECTION_NAME): Define.
|
|
|
|
|
|
(GNU_PROPERTY_STACK_SIZE): Define.
|
|
|
|
|
|
(GNU_PROPERTY_NO_COPY_ON_PROTECTED): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_USED): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_NEEDED): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_486): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_586): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_686): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE2): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE3): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSSE3): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE4_1): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_SSE4_2): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX2): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512F): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512CD): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512ER): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512PF): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512VL): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512DQ): Define.
|
|
|
|
|
|
(GNU_PROPERTY_X86_ISA_1_AVX512BW): Define.
|
|
|
|
|
|
|
2017-02-28 19:32:07 +01:00
|
|
|
|
2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dis-asm.h (disasm_options_t): New typedef.
|
|
|
|
|
|
(parse_arm_disassembler_option): Remove prototype.
|
|
|
|
|
|
(set_arm_regname_option): Likewise.
|
|
|
|
|
|
(get_arm_regnames): Likewise.
|
|
|
|
|
|
(get_arm_regname_num_options): Likewise.
|
|
|
|
|
|
(disassemble_init_s390): New prototype.
|
|
|
|
|
|
(disassembler_options_powerpc): Likewise.
|
|
|
|
|
|
(disassembler_options_arm): Likewise.
|
|
|
|
|
|
(disassembler_options_s390): Likewise.
|
|
|
|
|
|
(remove_whitespace_and_extra_commas): Likewise.
|
|
|
|
|
|
(disassembler_options_cmp): Likewise.
|
|
|
|
|
|
(next_disassembler_option): New inline function.
|
|
|
|
|
|
(FOR_EACH_DISASSEMBLER_OPTION): New macro.
|
|
|
|
|
|
|
2017-02-27 23:02:36 +01:00
|
|
|
|
2017-02-28 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* elf/ppc64.h (R_PPC64_16DX_HA): New. Expand fake reloc comment.
|
|
|
|
|
|
* elf/ppc.h (R_PPC_16DX_HA): Likewise.
|
|
|
|
|
|
|
[AArch64] Additional SVE instructions
This patch supports some additions to the SVE architecture prior to
its public release.
include/
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
opcodes/
* aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
(OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
(OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
(OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
(OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
(OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
(OP_SVE_V_HSD): New macros.
(OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
(OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
(OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
(aarch64_opcode_table): Add new SVE instructions.
(aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
for rotation operands. Add new SVE operands.
* aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
(ins_sve_quad_index): Likewise.
(ins_imm_rotate): Split into...
(ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
* aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
(aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
functions.
(aarch64_ins_sve_addr_ri_s4): New function.
(aarch64_ins_sve_quad_index): Likewise.
(do_misc_encoding): Handle "MOV Zn.Q, Qm".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
(ext_sve_quad_index): Likewise.
(ext_imm_rotate): Split into...
(ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
* aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
(aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
functions.
(aarch64_ext_sve_addr_ri_s4): New function.
(aarch64_ext_sve_quad_index): Likewise.
(aarch64_ext_sve_index): Allow quad indices.
(do_misc_decoding): Likewise.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
aarch64_field_kinds.
(OPD_F_OD_MASK): Widen by one bit.
(OPD_F_NO_ZR): Bump accordingly.
(get_operand_field_width): New function.
* aarch64-opc.c (fields): Add new SVE fields.
(operand_general_constraint_met_p): Handle new SVE operands.
(aarch64_print_operand): Likewise.
* aarch64-opc-2.c: Regenerate.
gas/
* doc/c-aarch64.texi: Document that sve implies fp16, simd and compnum.
* config/tc-aarch64.c (parse_vector_type_for_operand): Allow .q
to be used with SVE registers.
(parse_operands): Handle new SVE operands.
(aarch64_features): Make "sve" require F16 rather than FP. Also
require COMPNUM.
* testsuite/gas/aarch64/sve.s: Add tests for new instructions.
Include compnum tests.
* testsuite/gas/aarch64/sve.d: Update accordingly.
* testsuite/gas/aarch64/sve-invalid.s: Add tests for new instructions.
* testsuite/gas/aarch64/sve-invalid.l: Update accordingly. Also
update expected output for new FMOV and MOV alternatives.
2017-02-24 19:29:00 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_OPND_SVE_ADDR_RI_S4x16)
|
|
|
|
|
|
(AARCH64_OPND_SVE_IMM_ROT1, AARCH64_OPND_SVE_IMM_ROT2)
|
|
|
|
|
|
(AARCH64_OPND_SVE_Zm3_INDEX, AARCH64_OPND_SVE_Zm3_22_INDEX)
|
|
|
|
|
|
(AARCH64_OPND_SVE_Zm4_INDEX): New aarch64_opnds.
|
|
|
|
|
|
|
2017-02-24 19:27:26 +01:00
|
|
|
|
2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_FEATURE_COMPNUM): New macro.
|
|
|
|
|
|
(AARCH64_ARCH_V8_3): Include AARCH64_FEATURE_COMPNUM.
|
|
|
|
|
|
|
2017-02-23 06:23:05 +01:00
|
|
|
|
2017-02-22 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
|
|
|
|
|
|
(CSR_MCOUNTEREN): Likewise.
|
|
|
|
|
|
(scounteren): Declare register.
|
|
|
|
|
|
(mcounteren): Likewise.
|
|
|
|
|
|
|
2017-02-15 00:37:04 +01:00
|
|
|
|
2017-02-14 Andrew Waterman <andrew@sifive.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
|
|
|
|
|
|
(MASK_SFENCE_VMA): Likewise.
|
|
|
|
|
|
(sfence_vma): Declare instruction.
|
|
|
|
|
|
|
2017-02-14 11:08:21 +01:00
|
|
|
|
2017-02-14 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR 21118
|
|
|
|
|
|
* opcode/ppc.h (PPC_OPERAND_*): Reassign values, regs first.
|
|
|
|
|
|
(PPC_OPERAND_SPR, PPC_OPERAND_GQR): Define.
|
|
|
|
|
|
|
2017-01-25 13:19:27 +01:00
|
|
|
|
2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/hppa.h: Clarify that file is part of GNU opcodes.
|
|
|
|
|
|
* opcode/i860.h: Ditto.
|
|
|
|
|
|
* opcode/nios2.h: Ditto.
|
|
|
|
|
|
* opcode/nios2r1.h: Ditto.
|
|
|
|
|
|
* opcode/nios2r2.h: Ditto.
|
|
|
|
|
|
* opcode/pru.h: Ditto.
|
|
|
|
|
|
|
2017-01-25 13:24:02 +01:00
|
|
|
|
2017-01-24 Alan Hayward <alan.hayward@arm.com>
|
2017-01-24 11:37:13 +01:00
|
|
|
|
|
|
|
|
|
|
* elf/common.h (NT_ARM_SVE): Define.
|
|
|
|
|
|
|
2017-01-04 15:27:52 +01:00
|
|
|
|
2017-01-04 Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def: Sync with mainline gcc sources.
|
|
|
|
|
|
|
|
|
|
|
|
2017-01-04 Richard Earnshaw <rearnsha@arm.com>
|
|
|
|
|
|
Jiong Wang <jiong.wang@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def (DW_OP_AARCH64_operation): Reserve the number 0xea.
|
|
|
|
|
|
(DW_CFA_GNU_window_save): Comments the multiplexing on AArch64.
|
|
|
|
|
|
|
2017-01-04 13:27:10 +01:00
|
|
|
|
2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/aarch64.h (AARCH64_FEATURE_RCPC): Define.
|
|
|
|
|
|
(AARCH64_ARCH_V8_3): Update.
|
|
|
|
|
|
|
2017-01-03 18:42:01 +01:00
|
|
|
|
2017-01-03 Kito Cheng <kito.cheng@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
* opcode/riscv-opc.h: Add support for the "q" ISA extension.
|
|
|
|
|
|
|
2017-01-03 16:17:48 +01:00
|
|
|
|
2017-01-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def: Sync with mainline gcc sources
|
|
|
|
|
|
* dwarf2.h: Likewise.
|
|
|
|
|
|
|
|
|
|
|
|
2016-12-21 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def (DW_FORM_ref_sup): Renamed to ...
|
|
|
|
|
|
(DW_FORM_ref_sup4): ... this. New form.
|
|
|
|
|
|
(DW_FORM_ref_sup8): New form.
|
|
|
|
|
|
|
|
|
|
|
|
2016-10-17 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.h (enum dwarf_calling_convention): Add new DWARF5
|
|
|
|
|
|
calling convention codes.
|
|
|
|
|
|
(enum dwarf_line_number_content_type): New.
|
|
|
|
|
|
(enum dwarf_location_list_entry_type): Add DWARF5 DW_LLE_*
|
|
|
|
|
|
codes.
|
|
|
|
|
|
(enum dwarf_source_language): Add new DWARF5 DW_LANG_* codes.
|
|
|
|
|
|
(enum dwarf_macro_record_type): Add DWARF5 DW_MACRO_* codes.
|
|
|
|
|
|
(enum dwarf_name_index_attribute): New.
|
|
|
|
|
|
(enum dwarf_range_list_entry): New.
|
|
|
|
|
|
(enum dwarf_unit_type): New.
|
|
|
|
|
|
* dwarf2.def: Add new DWARF5 DW_TAG_*, DW_FORM_*, DW_AT_*,
|
|
|
|
|
|
DW_OP_* and DW_ATE_* entries.
|
|
|
|
|
|
|
|
|
|
|
|
2016-08-15 Jakub Jelinek <jakub@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
* dwarf2.def (DW_AT_string_length_bit_size,
|
|
|
|
|
|
DW_AT_string_length_byte_size): New attributes.
|
|
|
|
|
|
|
|
|
|
|
|
2016-08-12 Alexandre Oliva <aoliva@redhat.com>
|
|
|
|
|
|
|
|
|
|
|
|
PR debug/63240
|
|
|
|
|
|
* dwarf2.def (DW_AT_deleted, DW_AT_defaulted): New.
|
|
|
|
|
|
* dwarf2.h (enum dwarf_defaulted_attribute): New.
|
|
|
|
|
|
|
2017-01-02 04:36:43 +01:00
|
|
|
|
2017-01-02 Alan Modra <amodra@gmail.com>
|
|
|
|
|
|
|
|
|
|
|
|
Update year range in copyright notice of all files.
|
|
|
|
|
|
|
2017-01-02 04:25:05 +01:00
|
|
|
|
For older changes see ChangeLog-2016
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
2017-01-02 04:25:05 +01:00
|
|
|
|
Copyright (C) 2017 Free Software Foundation, Inc.
|
2016-01-01 11:44:31 +01:00
|
|
|
|
|
|
|
|
|
|
Copying and distribution of this file, with or without modification,
|
|
|
|
|
|
are permitted in any medium without royalty provided the copyright
|
|
|
|
|
|
notice and this notice are preserved.
|
|
|
|
|
|
|
|
|
|
|
|
Local Variables:
|
|
|
|
|
|
mode: change-log
|
|
|
|
|
|
left-margin: 8
|
|
|
|
|
|
fill-column: 74
|
|
|
|
|
|
version-control: never
|
|
|
|
|
|
End:
|
